1 /* 2 * Copyright 2011, Marvell Semiconductor Inc. 3 * Lei Wen <leiwen@marvell.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 * 7 * Back ported to the 8xx platform (from the 8260 platform) by 8 * Murray.Jensen@cmst.csiro.au, 27-Jan-01. 9 */ 10 11 #include <common.h> 12 #include <command.h> 13 #include <config.h> 14 #include <net.h> 15 #include <malloc.h> 16 #include <asm/byteorder.h> 17 #include <asm/errno.h> 18 #include <asm/io.h> 19 #include <asm/unaligned.h> 20 #include <linux/types.h> 21 #include <linux/usb/ch9.h> 22 #include <linux/usb/gadget.h> 23 #include <usb/ci_udc.h> 24 #include "../host/ehci.h" 25 #include "ci_udc.h" 26 27 /* 28 * Check if the system has too long cachelines. If the cachelines are 29 * longer then 128b, the driver will not be able flush/invalidate data 30 * cache over separate QH entries. We use 128b because one QH entry is 31 * 64b long and there are always two QH list entries for each endpoint. 32 */ 33 #if ARCH_DMA_MINALIGN > 128 34 #error This driver can not work on systems with caches longer than 128b 35 #endif 36 37 #ifndef DEBUG 38 #define DBG(x...) do {} while (0) 39 #else 40 #define DBG(x...) printf(x) 41 static const char *reqname(unsigned r) 42 { 43 switch (r) { 44 case USB_REQ_GET_STATUS: return "GET_STATUS"; 45 case USB_REQ_CLEAR_FEATURE: return "CLEAR_FEATURE"; 46 case USB_REQ_SET_FEATURE: return "SET_FEATURE"; 47 case USB_REQ_SET_ADDRESS: return "SET_ADDRESS"; 48 case USB_REQ_GET_DESCRIPTOR: return "GET_DESCRIPTOR"; 49 case USB_REQ_SET_DESCRIPTOR: return "SET_DESCRIPTOR"; 50 case USB_REQ_GET_CONFIGURATION: return "GET_CONFIGURATION"; 51 case USB_REQ_SET_CONFIGURATION: return "SET_CONFIGURATION"; 52 case USB_REQ_GET_INTERFACE: return "GET_INTERFACE"; 53 case USB_REQ_SET_INTERFACE: return "SET_INTERFACE"; 54 default: return "*UNKNOWN*"; 55 } 56 } 57 #endif 58 59 static struct usb_endpoint_descriptor ep0_desc = { 60 .bLength = sizeof(struct usb_endpoint_descriptor), 61 .bDescriptorType = USB_DT_ENDPOINT, 62 .bEndpointAddress = USB_DIR_IN, 63 .bmAttributes = USB_ENDPOINT_XFER_CONTROL, 64 }; 65 66 static int ci_pullup(struct usb_gadget *gadget, int is_on); 67 static int ci_ep_enable(struct usb_ep *ep, 68 const struct usb_endpoint_descriptor *desc); 69 static int ci_ep_disable(struct usb_ep *ep); 70 static int ci_ep_queue(struct usb_ep *ep, 71 struct usb_request *req, gfp_t gfp_flags); 72 static struct usb_request * 73 ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags); 74 static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *_req); 75 76 static struct usb_gadget_ops ci_udc_ops = { 77 .pullup = ci_pullup, 78 }; 79 80 static struct usb_ep_ops ci_ep_ops = { 81 .enable = ci_ep_enable, 82 .disable = ci_ep_disable, 83 .queue = ci_ep_queue, 84 .alloc_request = ci_ep_alloc_request, 85 .free_request = ci_ep_free_request, 86 }; 87 88 /* Init values for USB endpoints. */ 89 static const struct usb_ep ci_ep_init[2] = { 90 [0] = { /* EP 0 */ 91 .maxpacket = 64, 92 .name = "ep0", 93 .ops = &ci_ep_ops, 94 }, 95 [1] = { /* EP 1..n */ 96 .maxpacket = 512, 97 .name = "ep-", 98 .ops = &ci_ep_ops, 99 }, 100 }; 101 102 static struct ci_drv controller = { 103 .gadget = { 104 .name = "ci_udc", 105 .ops = &ci_udc_ops, 106 .is_dualspeed = 1, 107 }, 108 }; 109 110 /** 111 * ci_get_qh() - return queue head for endpoint 112 * @ep_num: Endpoint number 113 * @dir_in: Direction of the endpoint (IN = 1, OUT = 0) 114 * 115 * This function returns the QH associated with particular endpoint 116 * and it's direction. 117 */ 118 static struct ept_queue_head *ci_get_qh(int ep_num, int dir_in) 119 { 120 return &controller.epts[(ep_num * 2) + dir_in]; 121 } 122 123 /** 124 * ci_get_qtd() - return queue item for endpoint 125 * @ep_num: Endpoint number 126 * @dir_in: Direction of the endpoint (IN = 1, OUT = 0) 127 * 128 * This function returns the QH associated with particular endpoint 129 * and it's direction. 130 */ 131 static struct ept_queue_item *ci_get_qtd(int ep_num, int dir_in) 132 { 133 return controller.items[(ep_num * 2) + dir_in]; 134 } 135 136 /** 137 * ci_flush_qh - flush cache over queue head 138 * @ep_num: Endpoint number 139 * 140 * This function flushes cache over QH for particular endpoint. 141 */ 142 static void ci_flush_qh(int ep_num) 143 { 144 struct ept_queue_head *head = ci_get_qh(ep_num, 0); 145 const uint32_t start = (uint32_t)head; 146 const uint32_t end = start + 2 * sizeof(*head); 147 148 flush_dcache_range(start, end); 149 } 150 151 /** 152 * ci_invalidate_qh - invalidate cache over queue head 153 * @ep_num: Endpoint number 154 * 155 * This function invalidates cache over QH for particular endpoint. 156 */ 157 static void ci_invalidate_qh(int ep_num) 158 { 159 struct ept_queue_head *head = ci_get_qh(ep_num, 0); 160 uint32_t start = (uint32_t)head; 161 uint32_t end = start + 2 * sizeof(*head); 162 163 invalidate_dcache_range(start, end); 164 } 165 166 /** 167 * ci_flush_qtd - flush cache over queue item 168 * @ep_num: Endpoint number 169 * 170 * This function flushes cache over qTD pair for particular endpoint. 171 */ 172 static void ci_flush_qtd(int ep_num) 173 { 174 struct ept_queue_item *item = ci_get_qtd(ep_num, 0); 175 const uint32_t start = (uint32_t)item; 176 const uint32_t end_raw = start + 2 * sizeof(*item); 177 const uint32_t end = roundup(end_raw, ARCH_DMA_MINALIGN); 178 179 flush_dcache_range(start, end); 180 } 181 182 /** 183 * ci_invalidate_qtd - invalidate cache over queue item 184 * @ep_num: Endpoint number 185 * 186 * This function invalidates cache over qTD pair for particular endpoint. 187 */ 188 static void ci_invalidate_qtd(int ep_num) 189 { 190 struct ept_queue_item *item = ci_get_qtd(ep_num, 0); 191 const uint32_t start = (uint32_t)item; 192 const uint32_t end_raw = start + 2 * sizeof(*item); 193 const uint32_t end = roundup(end_raw, ARCH_DMA_MINALIGN); 194 195 invalidate_dcache_range(start, end); 196 } 197 198 static struct usb_request * 199 ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags) 200 { 201 struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep); 202 int num; 203 struct ci_req *ci_req; 204 205 num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; 206 if (num == 0 && controller.ep0_req) 207 return &controller.ep0_req->req; 208 209 ci_req = memalign(ARCH_DMA_MINALIGN, sizeof(*ci_req)); 210 if (!ci_req) 211 return NULL; 212 213 INIT_LIST_HEAD(&ci_req->queue); 214 ci_req->b_buf = 0; 215 216 if (num == 0) 217 controller.ep0_req = ci_req; 218 219 return &ci_req->req; 220 } 221 222 static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *req) 223 { 224 struct ci_req *ci_req; 225 226 ci_req = container_of(req, struct ci_req, req); 227 if (ci_req->b_buf) 228 free(ci_req->b_buf); 229 free(ci_req); 230 } 231 232 static void ep_enable(int num, int in, int maxpacket) 233 { 234 struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; 235 unsigned n; 236 237 n = readl(&udc->epctrl[num]); 238 if (in) 239 n |= (CTRL_TXE | CTRL_TXR | CTRL_TXT_BULK); 240 else 241 n |= (CTRL_RXE | CTRL_RXR | CTRL_RXT_BULK); 242 243 if (num != 0) { 244 struct ept_queue_head *head = ci_get_qh(num, in); 245 246 head->config = CONFIG_MAX_PKT(maxpacket) | CONFIG_ZLT; 247 ci_flush_qh(num); 248 } 249 writel(n, &udc->epctrl[num]); 250 } 251 252 static int ci_ep_enable(struct usb_ep *ep, 253 const struct usb_endpoint_descriptor *desc) 254 { 255 struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep); 256 int num, in; 257 num = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; 258 in = (desc->bEndpointAddress & USB_DIR_IN) != 0; 259 ci_ep->desc = desc; 260 261 if (num) { 262 int max = get_unaligned_le16(&desc->wMaxPacketSize); 263 264 if ((max > 64) && (controller.gadget.speed == USB_SPEED_FULL)) 265 max = 64; 266 if (ep->maxpacket != max) { 267 DBG("%s: from %d to %d\n", __func__, 268 ep->maxpacket, max); 269 ep->maxpacket = max; 270 } 271 } 272 ep_enable(num, in, ep->maxpacket); 273 DBG("%s: num=%d maxpacket=%d\n", __func__, num, ep->maxpacket); 274 return 0; 275 } 276 277 static int ci_ep_disable(struct usb_ep *ep) 278 { 279 struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep); 280 281 ci_ep->desc = NULL; 282 return 0; 283 } 284 285 static int ci_bounce(struct ci_req *ci_req, int in) 286 { 287 struct usb_request *req = &ci_req->req; 288 uint32_t addr = (uint32_t)req->buf; 289 uint32_t hwaddr; 290 uint32_t aligned_used_len; 291 292 /* Input buffer address is not aligned. */ 293 if (addr & (ARCH_DMA_MINALIGN - 1)) 294 goto align; 295 296 /* Input buffer length is not aligned. */ 297 if (req->length & (ARCH_DMA_MINALIGN - 1)) 298 goto align; 299 300 /* The buffer is well aligned, only flush cache. */ 301 ci_req->hw_len = req->length; 302 ci_req->hw_buf = req->buf; 303 goto flush; 304 305 align: 306 if (ci_req->b_buf && req->length > ci_req->b_len) { 307 free(ci_req->b_buf); 308 ci_req->b_buf = 0; 309 } 310 if (!ci_req->b_buf) { 311 ci_req->b_len = roundup(req->length, ARCH_DMA_MINALIGN); 312 ci_req->b_buf = memalign(ARCH_DMA_MINALIGN, ci_req->b_len); 313 if (!ci_req->b_buf) 314 return -ENOMEM; 315 } 316 ci_req->hw_len = ci_req->b_len; 317 ci_req->hw_buf = ci_req->b_buf; 318 319 if (in) 320 memcpy(ci_req->hw_buf, req->buf, req->length); 321 322 flush: 323 hwaddr = (uint32_t)ci_req->hw_buf; 324 aligned_used_len = roundup(req->length, ARCH_DMA_MINALIGN); 325 flush_dcache_range(hwaddr, hwaddr + aligned_used_len); 326 327 return 0; 328 } 329 330 static void ci_debounce(struct ci_req *ci_req, int in) 331 { 332 struct usb_request *req = &ci_req->req; 333 uint32_t addr = (uint32_t)req->buf; 334 uint32_t hwaddr = (uint32_t)ci_req->hw_buf; 335 uint32_t aligned_used_len; 336 337 if (in) 338 return; 339 340 aligned_used_len = roundup(req->actual, ARCH_DMA_MINALIGN); 341 invalidate_dcache_range(hwaddr, hwaddr + aligned_used_len); 342 343 if (addr == hwaddr) 344 return; /* not a bounce */ 345 346 memcpy(req->buf, ci_req->hw_buf, req->actual); 347 } 348 349 static void ci_ep_submit_next_request(struct ci_ep *ci_ep) 350 { 351 struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; 352 struct ept_queue_item *item; 353 struct ept_queue_head *head; 354 int bit, num, len, in; 355 struct ci_req *ci_req; 356 357 ci_ep->req_primed = true; 358 359 num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; 360 in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0; 361 item = ci_get_qtd(num, in); 362 head = ci_get_qh(num, in); 363 364 ci_req = list_first_entry(&ci_ep->queue, struct ci_req, queue); 365 len = ci_req->req.length; 366 367 item->next = TERMINATE; 368 item->info = INFO_BYTES(len) | INFO_IOC | INFO_ACTIVE; 369 item->page0 = (uint32_t)ci_req->hw_buf; 370 item->page1 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x1000; 371 item->page2 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x2000; 372 item->page3 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x3000; 373 item->page4 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x4000; 374 ci_flush_qtd(num); 375 376 head->next = (unsigned) item; 377 head->info = 0; 378 379 DBG("ept%d %s queue len %x, req %p, buffer %p\n", 380 num, in ? "in" : "out", len, ci_req, ci_req->hw_buf); 381 ci_flush_qh(num); 382 383 if (in) 384 bit = EPT_TX(num); 385 else 386 bit = EPT_RX(num); 387 388 writel(bit, &udc->epprime); 389 } 390 391 static int ci_ep_queue(struct usb_ep *ep, 392 struct usb_request *req, gfp_t gfp_flags) 393 { 394 struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep); 395 struct ci_req *ci_req = container_of(req, struct ci_req, req); 396 int in, ret; 397 int __maybe_unused num; 398 399 num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; 400 in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0; 401 402 if (!num && ci_ep->req_primed) { 403 /* 404 * The flipping of ep0 between IN and OUT relies on 405 * ci_ep_queue consuming the current IN/OUT setting 406 * immediately. If this is deferred to a later point when the 407 * req is pulled out of ci_req->queue, then the IN/OUT setting 408 * may have been changed since the req was queued, and state 409 * will get out of sync. This condition doesn't occur today, 410 * but could if bugs were introduced later, and this error 411 * check will save a lot of debugging time. 412 */ 413 printf("%s: ep0 transaction already in progress\n", __func__); 414 return -EPROTO; 415 } 416 417 ret = ci_bounce(ci_req, in); 418 if (ret) 419 return ret; 420 421 DBG("ept%d %s pre-queue req %p, buffer %p\n", 422 num, in ? "in" : "out", ci_req, ci_req->hw_buf); 423 list_add_tail(&ci_req->queue, &ci_ep->queue); 424 425 if (!ci_ep->req_primed) 426 ci_ep_submit_next_request(ci_ep); 427 428 return 0; 429 } 430 431 static void handle_ep_complete(struct ci_ep *ep) 432 { 433 struct ept_queue_item *item; 434 int num, in, len; 435 struct ci_req *ci_req; 436 437 num = ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; 438 in = (ep->desc->bEndpointAddress & USB_DIR_IN) != 0; 439 if (num == 0) 440 ep0_desc.bEndpointAddress = 0; 441 item = ci_get_qtd(num, in); 442 ci_invalidate_qtd(num); 443 444 len = (item->info >> 16) & 0x7fff; 445 if (item->info & 0xff) 446 printf("EP%d/%s FAIL info=%x pg0=%x\n", 447 num, in ? "in" : "out", item->info, item->page0); 448 449 ci_req = list_first_entry(&ep->queue, struct ci_req, queue); 450 list_del_init(&ci_req->queue); 451 ep->req_primed = false; 452 453 if (!list_empty(&ep->queue)) 454 ci_ep_submit_next_request(ep); 455 456 ci_req->req.actual = ci_req->req.length - len; 457 ci_debounce(ci_req, in); 458 459 DBG("ept%d %s req %p, complete %x\n", 460 num, in ? "in" : "out", ci_req, len); 461 ci_req->req.complete(&ep->ep, &ci_req->req); 462 if (num == 0) { 463 ci_req->req.length = 0; 464 usb_ep_queue(&ep->ep, &ci_req->req, 0); 465 ep0_desc.bEndpointAddress = USB_DIR_IN; 466 } 467 } 468 469 #define SETUP(type, request) (((type) << 8) | (request)) 470 471 static void handle_setup(void) 472 { 473 struct ci_ep *ci_ep = &controller.ep[0]; 474 struct ci_req *ci_req; 475 struct usb_request *req; 476 struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; 477 struct ept_queue_head *head; 478 struct usb_ctrlrequest r; 479 int status = 0; 480 int num, in, _num, _in, i; 481 char *buf; 482 483 ci_req = controller.ep0_req; 484 req = &ci_req->req; 485 head = ci_get_qh(0, 0); /* EP0 OUT */ 486 487 ci_invalidate_qh(0); 488 memcpy(&r, head->setup_data, sizeof(struct usb_ctrlrequest)); 489 #ifdef CONFIG_CI_UDC_HAS_HOSTPC 490 writel(EPT_RX(0), &udc->epsetupstat); 491 #else 492 writel(EPT_RX(0), &udc->epstat); 493 #endif 494 DBG("handle setup %s, %x, %x index %x value %x\n", reqname(r.bRequest), 495 r.bRequestType, r.bRequest, r.wIndex, r.wValue); 496 497 list_del_init(&ci_req->queue); 498 ci_ep->req_primed = false; 499 500 switch (SETUP(r.bRequestType, r.bRequest)) { 501 case SETUP(USB_RECIP_ENDPOINT, USB_REQ_CLEAR_FEATURE): 502 _num = r.wIndex & 15; 503 _in = !!(r.wIndex & 0x80); 504 505 if ((r.wValue == 0) && (r.wLength == 0)) { 506 req->length = 0; 507 for (i = 0; i < NUM_ENDPOINTS; i++) { 508 struct ci_ep *ep = &controller.ep[i]; 509 510 if (!ep->desc) 511 continue; 512 num = ep->desc->bEndpointAddress 513 & USB_ENDPOINT_NUMBER_MASK; 514 in = (ep->desc->bEndpointAddress 515 & USB_DIR_IN) != 0; 516 if ((num == _num) && (in == _in)) { 517 ep_enable(num, in, ep->ep.maxpacket); 518 usb_ep_queue(controller.gadget.ep0, 519 req, 0); 520 break; 521 } 522 } 523 } 524 return; 525 526 case SETUP(USB_RECIP_DEVICE, USB_REQ_SET_ADDRESS): 527 /* 528 * write address delayed (will take effect 529 * after the next IN txn) 530 */ 531 writel((r.wValue << 25) | (1 << 24), &udc->devaddr); 532 req->length = 0; 533 usb_ep_queue(controller.gadget.ep0, req, 0); 534 return; 535 536 case SETUP(USB_DIR_IN | USB_RECIP_DEVICE, USB_REQ_GET_STATUS): 537 req->length = 2; 538 buf = (char *)req->buf; 539 buf[0] = 1 << USB_DEVICE_SELF_POWERED; 540 buf[1] = 0; 541 usb_ep_queue(controller.gadget.ep0, req, 0); 542 return; 543 } 544 /* pass request up to the gadget driver */ 545 if (controller.driver) 546 status = controller.driver->setup(&controller.gadget, &r); 547 else 548 status = -ENODEV; 549 550 if (!status) 551 return; 552 DBG("STALL reqname %s type %x value %x, index %x\n", 553 reqname(r.bRequest), r.bRequestType, r.wValue, r.wIndex); 554 writel((1<<16) | (1 << 0), &udc->epctrl[0]); 555 } 556 557 static void stop_activity(void) 558 { 559 int i, num, in; 560 struct ept_queue_head *head; 561 struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; 562 writel(readl(&udc->epcomp), &udc->epcomp); 563 #ifdef CONFIG_CI_UDC_HAS_HOSTPC 564 writel(readl(&udc->epsetupstat), &udc->epsetupstat); 565 #endif 566 writel(readl(&udc->epstat), &udc->epstat); 567 writel(0xffffffff, &udc->epflush); 568 569 /* error out any pending reqs */ 570 for (i = 0; i < NUM_ENDPOINTS; i++) { 571 if (i != 0) 572 writel(0, &udc->epctrl[i]); 573 if (controller.ep[i].desc) { 574 num = controller.ep[i].desc->bEndpointAddress 575 & USB_ENDPOINT_NUMBER_MASK; 576 in = (controller.ep[i].desc->bEndpointAddress 577 & USB_DIR_IN) != 0; 578 head = ci_get_qh(num, in); 579 head->info = INFO_ACTIVE; 580 ci_flush_qh(num); 581 } 582 } 583 } 584 585 void udc_irq(void) 586 { 587 struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; 588 unsigned n = readl(&udc->usbsts); 589 writel(n, &udc->usbsts); 590 int bit, i, num, in; 591 592 n &= (STS_SLI | STS_URI | STS_PCI | STS_UI | STS_UEI); 593 if (n == 0) 594 return; 595 596 if (n & STS_URI) { 597 DBG("-- reset --\n"); 598 stop_activity(); 599 } 600 if (n & STS_SLI) 601 DBG("-- suspend --\n"); 602 603 if (n & STS_PCI) { 604 int max = 64; 605 int speed = USB_SPEED_FULL; 606 607 #ifdef CONFIG_CI_UDC_HAS_HOSTPC 608 bit = (readl(&udc->hostpc1_devlc) >> 25) & 3; 609 #else 610 bit = (readl(&udc->portsc) >> 26) & 3; 611 #endif 612 DBG("-- portchange %x %s\n", bit, (bit == 2) ? "High" : "Full"); 613 if (bit == 2) { 614 speed = USB_SPEED_HIGH; 615 max = 512; 616 } 617 controller.gadget.speed = speed; 618 for (i = 1; i < NUM_ENDPOINTS; i++) { 619 if (controller.ep[i].ep.maxpacket > max) 620 controller.ep[i].ep.maxpacket = max; 621 } 622 } 623 624 if (n & STS_UEI) 625 printf("<UEI %x>\n", readl(&udc->epcomp)); 626 627 if ((n & STS_UI) || (n & STS_UEI)) { 628 #ifdef CONFIG_CI_UDC_HAS_HOSTPC 629 n = readl(&udc->epsetupstat); 630 #else 631 n = readl(&udc->epstat); 632 #endif 633 if (n & EPT_RX(0)) 634 handle_setup(); 635 636 n = readl(&udc->epcomp); 637 if (n != 0) 638 writel(n, &udc->epcomp); 639 640 for (i = 0; i < NUM_ENDPOINTS && n; i++) { 641 if (controller.ep[i].desc) { 642 num = controller.ep[i].desc->bEndpointAddress 643 & USB_ENDPOINT_NUMBER_MASK; 644 in = (controller.ep[i].desc->bEndpointAddress 645 & USB_DIR_IN) != 0; 646 bit = (in) ? EPT_TX(num) : EPT_RX(num); 647 if (n & bit) 648 handle_ep_complete(&controller.ep[i]); 649 } 650 } 651 } 652 } 653 654 int usb_gadget_handle_interrupts(void) 655 { 656 u32 value; 657 struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; 658 659 value = readl(&udc->usbsts); 660 if (value) 661 udc_irq(); 662 663 return value; 664 } 665 666 static int ci_pullup(struct usb_gadget *gadget, int is_on) 667 { 668 struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; 669 if (is_on) { 670 /* RESET */ 671 writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RST, &udc->usbcmd); 672 udelay(200); 673 674 writel((unsigned)controller.epts, &udc->epinitaddr); 675 676 /* select DEVICE mode */ 677 writel(USBMODE_DEVICE, &udc->usbmode); 678 679 writel(0xffffffff, &udc->epflush); 680 681 /* Turn on the USB connection by enabling the pullup resistor */ 682 writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RUN, &udc->usbcmd); 683 } else { 684 stop_activity(); 685 writel(USBCMD_FS2, &udc->usbcmd); 686 udelay(800); 687 if (controller.driver) 688 controller.driver->disconnect(gadget); 689 } 690 691 return 0; 692 } 693 694 void udc_disconnect(void) 695 { 696 struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; 697 /* disable pullup */ 698 stop_activity(); 699 writel(USBCMD_FS2, &udc->usbcmd); 700 udelay(800); 701 if (controller.driver) 702 controller.driver->disconnect(&controller.gadget); 703 } 704 705 static int ci_udc_probe(void) 706 { 707 struct ept_queue_head *head; 708 uint8_t *imem; 709 int i; 710 711 const int num = 2 * NUM_ENDPOINTS; 712 713 const int eplist_min_align = 4096; 714 const int eplist_align = roundup(eplist_min_align, ARCH_DMA_MINALIGN); 715 const int eplist_raw_sz = num * sizeof(struct ept_queue_head); 716 const int eplist_sz = roundup(eplist_raw_sz, ARCH_DMA_MINALIGN); 717 718 const int ilist_align = roundup(ARCH_DMA_MINALIGN, 32); 719 const int ilist_ent_raw_sz = 2 * sizeof(struct ept_queue_item); 720 const int ilist_ent_sz = roundup(ilist_ent_raw_sz, ARCH_DMA_MINALIGN); 721 const int ilist_sz = NUM_ENDPOINTS * ilist_ent_sz; 722 723 /* The QH list must be aligned to 4096 bytes. */ 724 controller.epts = memalign(eplist_align, eplist_sz); 725 if (!controller.epts) 726 return -ENOMEM; 727 memset(controller.epts, 0, eplist_sz); 728 729 /* 730 * Each qTD item must be 32-byte aligned, each qTD touple must be 731 * cacheline aligned. There are two qTD items for each endpoint and 732 * only one of them is used for the endpoint at time, so we can group 733 * them together. 734 */ 735 controller.items_mem = memalign(ilist_align, ilist_sz); 736 if (!controller.items_mem) { 737 free(controller.epts); 738 return -ENOMEM; 739 } 740 memset(controller.items_mem, 0, ilist_sz); 741 742 for (i = 0; i < 2 * NUM_ENDPOINTS; i++) { 743 /* 744 * Configure QH for each endpoint. The structure of the QH list 745 * is such that each two subsequent fields, N and N+1 where N is 746 * even, in the QH list represent QH for one endpoint. The Nth 747 * entry represents OUT configuration and the N+1th entry does 748 * represent IN configuration of the endpoint. 749 */ 750 head = controller.epts + i; 751 if (i < 2) 752 head->config = CONFIG_MAX_PKT(EP0_MAX_PACKET_SIZE) 753 | CONFIG_ZLT | CONFIG_IOS; 754 else 755 head->config = CONFIG_MAX_PKT(EP_MAX_PACKET_SIZE) 756 | CONFIG_ZLT; 757 head->next = TERMINATE; 758 head->info = 0; 759 760 imem = controller.items_mem + ((i >> 1) * ilist_ent_sz); 761 if (i & 1) 762 imem += sizeof(struct ept_queue_item); 763 764 controller.items[i] = (struct ept_queue_item *)imem; 765 766 if (i & 1) { 767 ci_flush_qh(i - 1); 768 ci_flush_qtd(i - 1); 769 } 770 } 771 772 INIT_LIST_HEAD(&controller.gadget.ep_list); 773 774 /* Init EP 0 */ 775 memcpy(&controller.ep[0].ep, &ci_ep_init[0], sizeof(*ci_ep_init)); 776 controller.ep[0].desc = &ep0_desc; 777 INIT_LIST_HEAD(&controller.ep[0].queue); 778 controller.ep[0].req_primed = false; 779 controller.gadget.ep0 = &controller.ep[0].ep; 780 INIT_LIST_HEAD(&controller.gadget.ep0->ep_list); 781 782 /* Init EP 1..n */ 783 for (i = 1; i < NUM_ENDPOINTS; i++) { 784 memcpy(&controller.ep[i].ep, &ci_ep_init[1], 785 sizeof(*ci_ep_init)); 786 INIT_LIST_HEAD(&controller.ep[i].queue); 787 controller.ep[i].req_primed = false; 788 list_add_tail(&controller.ep[i].ep.ep_list, 789 &controller.gadget.ep_list); 790 } 791 792 ci_ep_alloc_request(&controller.ep[0].ep, 0); 793 if (!controller.ep0_req) { 794 free(controller.epts); 795 return -ENOMEM; 796 } 797 798 return 0; 799 } 800 801 int usb_gadget_register_driver(struct usb_gadget_driver *driver) 802 { 803 int ret; 804 805 if (!driver) 806 return -EINVAL; 807 if (!driver->bind || !driver->setup || !driver->disconnect) 808 return -EINVAL; 809 if (driver->speed != USB_SPEED_FULL && driver->speed != USB_SPEED_HIGH) 810 return -EINVAL; 811 812 ret = usb_lowlevel_init(0, USB_INIT_DEVICE, (void **)&controller.ctrl); 813 if (ret) 814 return ret; 815 816 ret = ci_udc_probe(); 817 #if defined(CONFIG_USB_EHCI_MX6) || defined(CONFIG_USB_EHCI_MXS) 818 /* 819 * FIXME: usb_lowlevel_init()->ehci_hcd_init() should be doing all 820 * HW-specific initialization, e.g. ULPI-vs-UTMI PHY selection 821 */ 822 if (!ret) { 823 struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; 824 825 /* select ULPI phy */ 826 writel(PTS(PTS_ENABLE) | PFSC, &udc->portsc); 827 } 828 #endif 829 830 ret = driver->bind(&controller.gadget); 831 if (ret) { 832 DBG("driver->bind() returned %d\n", ret); 833 return ret; 834 } 835 controller.driver = driver; 836 837 return 0; 838 } 839 840 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) 841 { 842 return 0; 843 } 844