1 /* 2 * Copyright 2011, Marvell Semiconductor Inc. 3 * Lei Wen <leiwen@marvell.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 * 7 * Back ported to the 8xx platform (from the 8260 platform) by 8 * Murray.Jensen@cmst.csiro.au, 27-Jan-01. 9 */ 10 11 #include <common.h> 12 #include <command.h> 13 #include <config.h> 14 #include <net.h> 15 #include <malloc.h> 16 #include <asm/byteorder.h> 17 #include <asm/errno.h> 18 #include <asm/io.h> 19 #include <asm/unaligned.h> 20 #include <linux/types.h> 21 #include <linux/usb/ch9.h> 22 #include <linux/usb/gadget.h> 23 #include <usb/ci_udc.h> 24 #include "../host/ehci.h" 25 #include "ci_udc.h" 26 27 /* 28 * Check if the system has too long cachelines. If the cachelines are 29 * longer then 128b, the driver will not be able flush/invalidate data 30 * cache over separate QH entries. We use 128b because one QH entry is 31 * 64b long and there are always two QH list entries for each endpoint. 32 */ 33 #if ARCH_DMA_MINALIGN > 128 34 #error This driver can not work on systems with caches longer than 128b 35 #endif 36 37 /* 38 * Every QTD must be individually aligned, since we can program any 39 * QTD's address into HW. Cache flushing requires ARCH_DMA_MINALIGN, 40 * and the USB HW requires 32-byte alignment. Align to both: 41 */ 42 #define ILIST_ALIGN roundup(ARCH_DMA_MINALIGN, 32) 43 /* Each QTD is this size */ 44 #define ILIST_ENT_RAW_SZ sizeof(struct ept_queue_item) 45 /* 46 * Align the size of the QTD too, so we can add this value to each 47 * QTD's address to get another aligned address. 48 */ 49 #define ILIST_ENT_SZ roundup(ILIST_ENT_RAW_SZ, ILIST_ALIGN) 50 /* For each endpoint, we need 2 QTDs, one for each of IN and OUT */ 51 #define ILIST_SZ (NUM_ENDPOINTS * 2 * ILIST_ENT_SZ) 52 53 #ifndef DEBUG 54 #define DBG(x...) do {} while (0) 55 #else 56 #define DBG(x...) printf(x) 57 static const char *reqname(unsigned r) 58 { 59 switch (r) { 60 case USB_REQ_GET_STATUS: return "GET_STATUS"; 61 case USB_REQ_CLEAR_FEATURE: return "CLEAR_FEATURE"; 62 case USB_REQ_SET_FEATURE: return "SET_FEATURE"; 63 case USB_REQ_SET_ADDRESS: return "SET_ADDRESS"; 64 case USB_REQ_GET_DESCRIPTOR: return "GET_DESCRIPTOR"; 65 case USB_REQ_SET_DESCRIPTOR: return "SET_DESCRIPTOR"; 66 case USB_REQ_GET_CONFIGURATION: return "GET_CONFIGURATION"; 67 case USB_REQ_SET_CONFIGURATION: return "SET_CONFIGURATION"; 68 case USB_REQ_GET_INTERFACE: return "GET_INTERFACE"; 69 case USB_REQ_SET_INTERFACE: return "SET_INTERFACE"; 70 default: return "*UNKNOWN*"; 71 } 72 } 73 #endif 74 75 static struct usb_endpoint_descriptor ep0_desc = { 76 .bLength = sizeof(struct usb_endpoint_descriptor), 77 .bDescriptorType = USB_DT_ENDPOINT, 78 .bEndpointAddress = USB_DIR_IN, 79 .bmAttributes = USB_ENDPOINT_XFER_CONTROL, 80 }; 81 82 static int ci_pullup(struct usb_gadget *gadget, int is_on); 83 static int ci_ep_enable(struct usb_ep *ep, 84 const struct usb_endpoint_descriptor *desc); 85 static int ci_ep_disable(struct usb_ep *ep); 86 static int ci_ep_queue(struct usb_ep *ep, 87 struct usb_request *req, gfp_t gfp_flags); 88 static struct usb_request * 89 ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags); 90 static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *_req); 91 92 static struct usb_gadget_ops ci_udc_ops = { 93 .pullup = ci_pullup, 94 }; 95 96 static struct usb_ep_ops ci_ep_ops = { 97 .enable = ci_ep_enable, 98 .disable = ci_ep_disable, 99 .queue = ci_ep_queue, 100 .alloc_request = ci_ep_alloc_request, 101 .free_request = ci_ep_free_request, 102 }; 103 104 /* Init values for USB endpoints. */ 105 static const struct usb_ep ci_ep_init[2] = { 106 [0] = { /* EP 0 */ 107 .maxpacket = 64, 108 .name = "ep0", 109 .ops = &ci_ep_ops, 110 }, 111 [1] = { /* EP 1..n */ 112 .maxpacket = 512, 113 .name = "ep-", 114 .ops = &ci_ep_ops, 115 }, 116 }; 117 118 static struct ci_drv controller = { 119 .gadget = { 120 .name = "ci_udc", 121 .ops = &ci_udc_ops, 122 .is_dualspeed = 1, 123 }, 124 }; 125 126 /** 127 * ci_get_qh() - return queue head for endpoint 128 * @ep_num: Endpoint number 129 * @dir_in: Direction of the endpoint (IN = 1, OUT = 0) 130 * 131 * This function returns the QH associated with particular endpoint 132 * and it's direction. 133 */ 134 static struct ept_queue_head *ci_get_qh(int ep_num, int dir_in) 135 { 136 return &controller.epts[(ep_num * 2) + dir_in]; 137 } 138 139 /** 140 * ci_get_qtd() - return queue item for endpoint 141 * @ep_num: Endpoint number 142 * @dir_in: Direction of the endpoint (IN = 1, OUT = 0) 143 * 144 * This function returns the QH associated with particular endpoint 145 * and it's direction. 146 */ 147 static struct ept_queue_item *ci_get_qtd(int ep_num, int dir_in) 148 { 149 return controller.items[(ep_num * 2) + dir_in]; 150 } 151 152 /** 153 * ci_flush_qh - flush cache over queue head 154 * @ep_num: Endpoint number 155 * 156 * This function flushes cache over QH for particular endpoint. 157 */ 158 static void ci_flush_qh(int ep_num) 159 { 160 struct ept_queue_head *head = ci_get_qh(ep_num, 0); 161 const uint32_t start = (uint32_t)head; 162 const uint32_t end = start + 2 * sizeof(*head); 163 164 flush_dcache_range(start, end); 165 } 166 167 /** 168 * ci_invalidate_qh - invalidate cache over queue head 169 * @ep_num: Endpoint number 170 * 171 * This function invalidates cache over QH for particular endpoint. 172 */ 173 static void ci_invalidate_qh(int ep_num) 174 { 175 struct ept_queue_head *head = ci_get_qh(ep_num, 0); 176 uint32_t start = (uint32_t)head; 177 uint32_t end = start + 2 * sizeof(*head); 178 179 invalidate_dcache_range(start, end); 180 } 181 182 /** 183 * ci_flush_qtd - flush cache over queue item 184 * @ep_num: Endpoint number 185 * 186 * This function flushes cache over qTD pair for particular endpoint. 187 */ 188 static void ci_flush_qtd(int ep_num) 189 { 190 struct ept_queue_item *item = ci_get_qtd(ep_num, 0); 191 const uint32_t start = (uint32_t)item; 192 const uint32_t end = start + 2 * ILIST_ENT_SZ; 193 194 flush_dcache_range(start, end); 195 } 196 197 /** 198 * ci_invalidate_qtd - invalidate cache over queue item 199 * @ep_num: Endpoint number 200 * 201 * This function invalidates cache over qTD pair for particular endpoint. 202 */ 203 static void ci_invalidate_qtd(int ep_num) 204 { 205 struct ept_queue_item *item = ci_get_qtd(ep_num, 0); 206 const uint32_t start = (uint32_t)item; 207 const uint32_t end = start + 2 * ILIST_ENT_SZ; 208 209 invalidate_dcache_range(start, end); 210 } 211 212 static struct usb_request * 213 ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags) 214 { 215 struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep); 216 int num; 217 struct ci_req *ci_req; 218 219 num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; 220 if (num == 0 && controller.ep0_req) 221 return &controller.ep0_req->req; 222 223 ci_req = memalign(ARCH_DMA_MINALIGN, sizeof(*ci_req)); 224 if (!ci_req) 225 return NULL; 226 227 INIT_LIST_HEAD(&ci_req->queue); 228 ci_req->b_buf = 0; 229 230 if (num == 0) 231 controller.ep0_req = ci_req; 232 233 return &ci_req->req; 234 } 235 236 static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *req) 237 { 238 struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep); 239 struct ci_req *ci_req = container_of(req, struct ci_req, req); 240 int num; 241 242 num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; 243 if (num == 0) { 244 if (!controller.ep0_req) 245 return; 246 controller.ep0_req = 0; 247 } 248 249 if (ci_req->b_buf) 250 free(ci_req->b_buf); 251 free(ci_req); 252 } 253 254 static void ep_enable(int num, int in, int maxpacket) 255 { 256 struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; 257 unsigned n; 258 259 n = readl(&udc->epctrl[num]); 260 if (in) 261 n |= (CTRL_TXE | CTRL_TXR | CTRL_TXT_BULK); 262 else 263 n |= (CTRL_RXE | CTRL_RXR | CTRL_RXT_BULK); 264 265 if (num != 0) { 266 struct ept_queue_head *head = ci_get_qh(num, in); 267 268 head->config = CONFIG_MAX_PKT(maxpacket) | CONFIG_ZLT; 269 ci_flush_qh(num); 270 } 271 writel(n, &udc->epctrl[num]); 272 } 273 274 static int ci_ep_enable(struct usb_ep *ep, 275 const struct usb_endpoint_descriptor *desc) 276 { 277 struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep); 278 int num, in; 279 num = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; 280 in = (desc->bEndpointAddress & USB_DIR_IN) != 0; 281 ci_ep->desc = desc; 282 283 if (num) { 284 int max = get_unaligned_le16(&desc->wMaxPacketSize); 285 286 if ((max > 64) && (controller.gadget.speed == USB_SPEED_FULL)) 287 max = 64; 288 if (ep->maxpacket != max) { 289 DBG("%s: from %d to %d\n", __func__, 290 ep->maxpacket, max); 291 ep->maxpacket = max; 292 } 293 } 294 ep_enable(num, in, ep->maxpacket); 295 DBG("%s: num=%d maxpacket=%d\n", __func__, num, ep->maxpacket); 296 return 0; 297 } 298 299 static int ci_ep_disable(struct usb_ep *ep) 300 { 301 struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep); 302 303 ci_ep->desc = NULL; 304 return 0; 305 } 306 307 static int ci_bounce(struct ci_req *ci_req, int in) 308 { 309 struct usb_request *req = &ci_req->req; 310 uint32_t addr = (uint32_t)req->buf; 311 uint32_t hwaddr; 312 uint32_t aligned_used_len; 313 314 /* Input buffer address is not aligned. */ 315 if (addr & (ARCH_DMA_MINALIGN - 1)) 316 goto align; 317 318 /* Input buffer length is not aligned. */ 319 if (req->length & (ARCH_DMA_MINALIGN - 1)) 320 goto align; 321 322 /* The buffer is well aligned, only flush cache. */ 323 ci_req->hw_len = req->length; 324 ci_req->hw_buf = req->buf; 325 goto flush; 326 327 align: 328 if (ci_req->b_buf && req->length > ci_req->b_len) { 329 free(ci_req->b_buf); 330 ci_req->b_buf = 0; 331 } 332 if (!ci_req->b_buf) { 333 ci_req->b_len = roundup(req->length, ARCH_DMA_MINALIGN); 334 ci_req->b_buf = memalign(ARCH_DMA_MINALIGN, ci_req->b_len); 335 if (!ci_req->b_buf) 336 return -ENOMEM; 337 } 338 ci_req->hw_len = ci_req->b_len; 339 ci_req->hw_buf = ci_req->b_buf; 340 341 if (in) 342 memcpy(ci_req->hw_buf, req->buf, req->length); 343 344 flush: 345 hwaddr = (uint32_t)ci_req->hw_buf; 346 aligned_used_len = roundup(req->length, ARCH_DMA_MINALIGN); 347 flush_dcache_range(hwaddr, hwaddr + aligned_used_len); 348 349 return 0; 350 } 351 352 static void ci_debounce(struct ci_req *ci_req, int in) 353 { 354 struct usb_request *req = &ci_req->req; 355 uint32_t addr = (uint32_t)req->buf; 356 uint32_t hwaddr = (uint32_t)ci_req->hw_buf; 357 uint32_t aligned_used_len; 358 359 if (in) 360 return; 361 362 aligned_used_len = roundup(req->actual, ARCH_DMA_MINALIGN); 363 invalidate_dcache_range(hwaddr, hwaddr + aligned_used_len); 364 365 if (addr == hwaddr) 366 return; /* not a bounce */ 367 368 memcpy(req->buf, ci_req->hw_buf, req->actual); 369 } 370 371 static void ci_ep_submit_next_request(struct ci_ep *ci_ep) 372 { 373 struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; 374 struct ept_queue_item *item; 375 struct ept_queue_head *head; 376 int bit, num, len, in; 377 struct ci_req *ci_req; 378 379 ci_ep->req_primed = true; 380 381 num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; 382 in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0; 383 item = ci_get_qtd(num, in); 384 head = ci_get_qh(num, in); 385 386 ci_req = list_first_entry(&ci_ep->queue, struct ci_req, queue); 387 len = ci_req->req.length; 388 389 item->info = INFO_BYTES(len) | INFO_ACTIVE; 390 item->page0 = (uint32_t)ci_req->hw_buf; 391 item->page1 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x1000; 392 item->page2 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x2000; 393 item->page3 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x3000; 394 item->page4 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x4000; 395 396 head->next = (unsigned) item; 397 head->info = 0; 398 399 /* 400 * When sending the data for an IN transaction, the attached host 401 * knows that all data for the IN is sent when one of the following 402 * occurs: 403 * a) A zero-length packet is transmitted. 404 * b) A packet with length that isn't an exact multiple of the ep's 405 * maxpacket is transmitted. 406 * c) Enough data is sent to exactly fill the host's maximum expected 407 * IN transaction size. 408 * 409 * One of these conditions MUST apply at the end of an IN transaction, 410 * or the transaction will not be considered complete by the host. If 411 * none of (a)..(c) already applies, then we must force (a) to apply 412 * by explicitly sending an extra zero-length packet. 413 */ 414 /* IN !a !b !c */ 415 if (in && len && !(len % ci_ep->ep.maxpacket) && ci_req->req.zero) { 416 /* 417 * Each endpoint has 2 items allocated, even though typically 418 * only 1 is used at a time since either an IN or an OUT but 419 * not both is queued. For an IN transaction, item currently 420 * points at the second of these items, so we know that we 421 * can use the other to transmit the extra zero-length packet. 422 */ 423 struct ept_queue_item *other_item = ci_get_qtd(num, 0); 424 item->next = (unsigned)other_item; 425 item = other_item; 426 item->info = INFO_ACTIVE; 427 } 428 429 item->next = TERMINATE; 430 item->info |= INFO_IOC; 431 432 ci_flush_qtd(num); 433 434 DBG("ept%d %s queue len %x, req %p, buffer %p\n", 435 num, in ? "in" : "out", len, ci_req, ci_req->hw_buf); 436 ci_flush_qh(num); 437 438 if (in) 439 bit = EPT_TX(num); 440 else 441 bit = EPT_RX(num); 442 443 writel(bit, &udc->epprime); 444 } 445 446 static int ci_ep_queue(struct usb_ep *ep, 447 struct usb_request *req, gfp_t gfp_flags) 448 { 449 struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep); 450 struct ci_req *ci_req = container_of(req, struct ci_req, req); 451 int in, ret; 452 int __maybe_unused num; 453 454 num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; 455 in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0; 456 457 if (!num && ci_ep->req_primed) { 458 /* 459 * The flipping of ep0 between IN and OUT relies on 460 * ci_ep_queue consuming the current IN/OUT setting 461 * immediately. If this is deferred to a later point when the 462 * req is pulled out of ci_req->queue, then the IN/OUT setting 463 * may have been changed since the req was queued, and state 464 * will get out of sync. This condition doesn't occur today, 465 * but could if bugs were introduced later, and this error 466 * check will save a lot of debugging time. 467 */ 468 printf("%s: ep0 transaction already in progress\n", __func__); 469 return -EPROTO; 470 } 471 472 ret = ci_bounce(ci_req, in); 473 if (ret) 474 return ret; 475 476 DBG("ept%d %s pre-queue req %p, buffer %p\n", 477 num, in ? "in" : "out", ci_req, ci_req->hw_buf); 478 list_add_tail(&ci_req->queue, &ci_ep->queue); 479 480 if (!ci_ep->req_primed) 481 ci_ep_submit_next_request(ci_ep); 482 483 return 0; 484 } 485 486 static void flip_ep0_direction(void) 487 { 488 if (ep0_desc.bEndpointAddress == USB_DIR_IN) { 489 DBG("%s: Flipping ep0 to OUT\n", __func__); 490 ep0_desc.bEndpointAddress = 0; 491 } else { 492 DBG("%s: Flipping ep0 to IN\n", __func__); 493 ep0_desc.bEndpointAddress = USB_DIR_IN; 494 } 495 } 496 497 static void handle_ep_complete(struct ci_ep *ep) 498 { 499 struct ept_queue_item *item; 500 int num, in, len; 501 struct ci_req *ci_req; 502 503 num = ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; 504 in = (ep->desc->bEndpointAddress & USB_DIR_IN) != 0; 505 item = ci_get_qtd(num, in); 506 ci_invalidate_qtd(num); 507 508 len = (item->info >> 16) & 0x7fff; 509 if (item->info & 0xff) 510 printf("EP%d/%s FAIL info=%x pg0=%x\n", 511 num, in ? "in" : "out", item->info, item->page0); 512 513 ci_req = list_first_entry(&ep->queue, struct ci_req, queue); 514 list_del_init(&ci_req->queue); 515 ep->req_primed = false; 516 517 if (!list_empty(&ep->queue)) 518 ci_ep_submit_next_request(ep); 519 520 ci_req->req.actual = ci_req->req.length - len; 521 ci_debounce(ci_req, in); 522 523 DBG("ept%d %s req %p, complete %x\n", 524 num, in ? "in" : "out", ci_req, len); 525 if (num != 0 || controller.ep0_data_phase) 526 ci_req->req.complete(&ep->ep, &ci_req->req); 527 if (num == 0 && controller.ep0_data_phase) { 528 /* 529 * Data Stage is complete, so flip ep0 dir for Status Stage, 530 * which always transfers a packet in the opposite direction. 531 */ 532 DBG("%s: flip ep0 dir for Status Stage\n", __func__); 533 flip_ep0_direction(); 534 controller.ep0_data_phase = false; 535 ci_req->req.length = 0; 536 usb_ep_queue(&ep->ep, &ci_req->req, 0); 537 } 538 } 539 540 #define SETUP(type, request) (((type) << 8) | (request)) 541 542 static void handle_setup(void) 543 { 544 struct ci_ep *ci_ep = &controller.ep[0]; 545 struct ci_req *ci_req; 546 struct usb_request *req; 547 struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; 548 struct ept_queue_head *head; 549 struct usb_ctrlrequest r; 550 int status = 0; 551 int num, in, _num, _in, i; 552 char *buf; 553 554 ci_req = controller.ep0_req; 555 req = &ci_req->req; 556 head = ci_get_qh(0, 0); /* EP0 OUT */ 557 558 ci_invalidate_qh(0); 559 memcpy(&r, head->setup_data, sizeof(struct usb_ctrlrequest)); 560 #ifdef CONFIG_CI_UDC_HAS_HOSTPC 561 writel(EPT_RX(0), &udc->epsetupstat); 562 #else 563 writel(EPT_RX(0), &udc->epstat); 564 #endif 565 DBG("handle setup %s, %x, %x index %x value %x length %x\n", 566 reqname(r.bRequest), r.bRequestType, r.bRequest, r.wIndex, 567 r.wValue, r.wLength); 568 569 /* Set EP0 dir for Data Stage based on Setup Stage data */ 570 if (r.bRequestType & USB_DIR_IN) { 571 DBG("%s: Set ep0 to IN for Data Stage\n", __func__); 572 ep0_desc.bEndpointAddress = USB_DIR_IN; 573 } else { 574 DBG("%s: Set ep0 to OUT for Data Stage\n", __func__); 575 ep0_desc.bEndpointAddress = 0; 576 } 577 if (r.wLength) { 578 controller.ep0_data_phase = true; 579 } else { 580 /* 0 length -> no Data Stage. Flip dir for Status Stage */ 581 DBG("%s: 0 length: flip ep0 dir for Status Stage\n", __func__); 582 flip_ep0_direction(); 583 controller.ep0_data_phase = false; 584 } 585 586 list_del_init(&ci_req->queue); 587 ci_ep->req_primed = false; 588 589 switch (SETUP(r.bRequestType, r.bRequest)) { 590 case SETUP(USB_RECIP_ENDPOINT, USB_REQ_CLEAR_FEATURE): 591 _num = r.wIndex & 15; 592 _in = !!(r.wIndex & 0x80); 593 594 if ((r.wValue == 0) && (r.wLength == 0)) { 595 req->length = 0; 596 for (i = 0; i < NUM_ENDPOINTS; i++) { 597 struct ci_ep *ep = &controller.ep[i]; 598 599 if (!ep->desc) 600 continue; 601 num = ep->desc->bEndpointAddress 602 & USB_ENDPOINT_NUMBER_MASK; 603 in = (ep->desc->bEndpointAddress 604 & USB_DIR_IN) != 0; 605 if ((num == _num) && (in == _in)) { 606 ep_enable(num, in, ep->ep.maxpacket); 607 usb_ep_queue(controller.gadget.ep0, 608 req, 0); 609 break; 610 } 611 } 612 } 613 return; 614 615 case SETUP(USB_RECIP_DEVICE, USB_REQ_SET_ADDRESS): 616 /* 617 * write address delayed (will take effect 618 * after the next IN txn) 619 */ 620 writel((r.wValue << 25) | (1 << 24), &udc->devaddr); 621 req->length = 0; 622 usb_ep_queue(controller.gadget.ep0, req, 0); 623 return; 624 625 case SETUP(USB_DIR_IN | USB_RECIP_DEVICE, USB_REQ_GET_STATUS): 626 req->length = 2; 627 buf = (char *)req->buf; 628 buf[0] = 1 << USB_DEVICE_SELF_POWERED; 629 buf[1] = 0; 630 usb_ep_queue(controller.gadget.ep0, req, 0); 631 return; 632 } 633 /* pass request up to the gadget driver */ 634 if (controller.driver) 635 status = controller.driver->setup(&controller.gadget, &r); 636 else 637 status = -ENODEV; 638 639 if (!status) 640 return; 641 DBG("STALL reqname %s type %x value %x, index %x\n", 642 reqname(r.bRequest), r.bRequestType, r.wValue, r.wIndex); 643 writel((1<<16) | (1 << 0), &udc->epctrl[0]); 644 } 645 646 static void stop_activity(void) 647 { 648 int i, num, in; 649 struct ept_queue_head *head; 650 struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; 651 writel(readl(&udc->epcomp), &udc->epcomp); 652 #ifdef CONFIG_CI_UDC_HAS_HOSTPC 653 writel(readl(&udc->epsetupstat), &udc->epsetupstat); 654 #endif 655 writel(readl(&udc->epstat), &udc->epstat); 656 writel(0xffffffff, &udc->epflush); 657 658 /* error out any pending reqs */ 659 for (i = 0; i < NUM_ENDPOINTS; i++) { 660 if (i != 0) 661 writel(0, &udc->epctrl[i]); 662 if (controller.ep[i].desc) { 663 num = controller.ep[i].desc->bEndpointAddress 664 & USB_ENDPOINT_NUMBER_MASK; 665 in = (controller.ep[i].desc->bEndpointAddress 666 & USB_DIR_IN) != 0; 667 head = ci_get_qh(num, in); 668 head->info = INFO_ACTIVE; 669 ci_flush_qh(num); 670 } 671 } 672 } 673 674 void udc_irq(void) 675 { 676 struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; 677 unsigned n = readl(&udc->usbsts); 678 writel(n, &udc->usbsts); 679 int bit, i, num, in; 680 681 n &= (STS_SLI | STS_URI | STS_PCI | STS_UI | STS_UEI); 682 if (n == 0) 683 return; 684 685 if (n & STS_URI) { 686 DBG("-- reset --\n"); 687 stop_activity(); 688 } 689 if (n & STS_SLI) 690 DBG("-- suspend --\n"); 691 692 if (n & STS_PCI) { 693 int max = 64; 694 int speed = USB_SPEED_FULL; 695 696 #ifdef CONFIG_CI_UDC_HAS_HOSTPC 697 bit = (readl(&udc->hostpc1_devlc) >> 25) & 3; 698 #else 699 bit = (readl(&udc->portsc) >> 26) & 3; 700 #endif 701 DBG("-- portchange %x %s\n", bit, (bit == 2) ? "High" : "Full"); 702 if (bit == 2) { 703 speed = USB_SPEED_HIGH; 704 max = 512; 705 } 706 controller.gadget.speed = speed; 707 for (i = 1; i < NUM_ENDPOINTS; i++) { 708 if (controller.ep[i].ep.maxpacket > max) 709 controller.ep[i].ep.maxpacket = max; 710 } 711 } 712 713 if (n & STS_UEI) 714 printf("<UEI %x>\n", readl(&udc->epcomp)); 715 716 if ((n & STS_UI) || (n & STS_UEI)) { 717 #ifdef CONFIG_CI_UDC_HAS_HOSTPC 718 n = readl(&udc->epsetupstat); 719 #else 720 n = readl(&udc->epstat); 721 #endif 722 if (n & EPT_RX(0)) 723 handle_setup(); 724 725 n = readl(&udc->epcomp); 726 if (n != 0) 727 writel(n, &udc->epcomp); 728 729 for (i = 0; i < NUM_ENDPOINTS && n; i++) { 730 if (controller.ep[i].desc) { 731 num = controller.ep[i].desc->bEndpointAddress 732 & USB_ENDPOINT_NUMBER_MASK; 733 in = (controller.ep[i].desc->bEndpointAddress 734 & USB_DIR_IN) != 0; 735 bit = (in) ? EPT_TX(num) : EPT_RX(num); 736 if (n & bit) 737 handle_ep_complete(&controller.ep[i]); 738 } 739 } 740 } 741 } 742 743 int usb_gadget_handle_interrupts(void) 744 { 745 u32 value; 746 struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; 747 748 value = readl(&udc->usbsts); 749 if (value) 750 udc_irq(); 751 752 return value; 753 } 754 755 void udc_disconnect(void) 756 { 757 struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; 758 /* disable pullup */ 759 stop_activity(); 760 writel(USBCMD_FS2, &udc->usbcmd); 761 udelay(800); 762 if (controller.driver) 763 controller.driver->disconnect(&controller.gadget); 764 } 765 766 static int ci_pullup(struct usb_gadget *gadget, int is_on) 767 { 768 struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; 769 if (is_on) { 770 /* RESET */ 771 writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RST, &udc->usbcmd); 772 udelay(200); 773 774 writel((unsigned)controller.epts, &udc->epinitaddr); 775 776 /* select DEVICE mode */ 777 writel(USBMODE_DEVICE, &udc->usbmode); 778 779 writel(0xffffffff, &udc->epflush); 780 781 /* Turn on the USB connection by enabling the pullup resistor */ 782 writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RUN, &udc->usbcmd); 783 } else { 784 udc_disconnect(); 785 } 786 787 return 0; 788 } 789 790 static int ci_udc_probe(void) 791 { 792 struct ept_queue_head *head; 793 uint8_t *imem; 794 int i; 795 796 const int num = 2 * NUM_ENDPOINTS; 797 798 const int eplist_min_align = 4096; 799 const int eplist_align = roundup(eplist_min_align, ARCH_DMA_MINALIGN); 800 const int eplist_raw_sz = num * sizeof(struct ept_queue_head); 801 const int eplist_sz = roundup(eplist_raw_sz, ARCH_DMA_MINALIGN); 802 803 /* The QH list must be aligned to 4096 bytes. */ 804 controller.epts = memalign(eplist_align, eplist_sz); 805 if (!controller.epts) 806 return -ENOMEM; 807 memset(controller.epts, 0, eplist_sz); 808 809 controller.items_mem = memalign(ILIST_ALIGN, ILIST_SZ); 810 if (!controller.items_mem) { 811 free(controller.epts); 812 return -ENOMEM; 813 } 814 memset(controller.items_mem, 0, ILIST_SZ); 815 816 for (i = 0; i < 2 * NUM_ENDPOINTS; i++) { 817 /* 818 * Configure QH for each endpoint. The structure of the QH list 819 * is such that each two subsequent fields, N and N+1 where N is 820 * even, in the QH list represent QH for one endpoint. The Nth 821 * entry represents OUT configuration and the N+1th entry does 822 * represent IN configuration of the endpoint. 823 */ 824 head = controller.epts + i; 825 if (i < 2) 826 head->config = CONFIG_MAX_PKT(EP0_MAX_PACKET_SIZE) 827 | CONFIG_ZLT | CONFIG_IOS; 828 else 829 head->config = CONFIG_MAX_PKT(EP_MAX_PACKET_SIZE) 830 | CONFIG_ZLT; 831 head->next = TERMINATE; 832 head->info = 0; 833 834 imem = controller.items_mem + (i * ILIST_ENT_SZ); 835 controller.items[i] = (struct ept_queue_item *)imem; 836 837 if (i & 1) { 838 ci_flush_qh(i / 2); 839 ci_flush_qtd(i / 2); 840 } 841 } 842 843 INIT_LIST_HEAD(&controller.gadget.ep_list); 844 845 /* Init EP 0 */ 846 memcpy(&controller.ep[0].ep, &ci_ep_init[0], sizeof(*ci_ep_init)); 847 controller.ep[0].desc = &ep0_desc; 848 INIT_LIST_HEAD(&controller.ep[0].queue); 849 controller.ep[0].req_primed = false; 850 controller.gadget.ep0 = &controller.ep[0].ep; 851 INIT_LIST_HEAD(&controller.gadget.ep0->ep_list); 852 853 /* Init EP 1..n */ 854 for (i = 1; i < NUM_ENDPOINTS; i++) { 855 memcpy(&controller.ep[i].ep, &ci_ep_init[1], 856 sizeof(*ci_ep_init)); 857 INIT_LIST_HEAD(&controller.ep[i].queue); 858 controller.ep[i].req_primed = false; 859 list_add_tail(&controller.ep[i].ep.ep_list, 860 &controller.gadget.ep_list); 861 } 862 863 ci_ep_alloc_request(&controller.ep[0].ep, 0); 864 if (!controller.ep0_req) { 865 free(controller.items_mem); 866 free(controller.epts); 867 return -ENOMEM; 868 } 869 870 return 0; 871 } 872 873 int usb_gadget_register_driver(struct usb_gadget_driver *driver) 874 { 875 int ret; 876 877 if (!driver) 878 return -EINVAL; 879 if (!driver->bind || !driver->setup || !driver->disconnect) 880 return -EINVAL; 881 if (driver->speed != USB_SPEED_FULL && driver->speed != USB_SPEED_HIGH) 882 return -EINVAL; 883 884 ret = usb_lowlevel_init(0, USB_INIT_DEVICE, (void **)&controller.ctrl); 885 if (ret) 886 return ret; 887 888 ret = ci_udc_probe(); 889 #if defined(CONFIG_USB_EHCI_MX6) || defined(CONFIG_USB_EHCI_MXS) 890 /* 891 * FIXME: usb_lowlevel_init()->ehci_hcd_init() should be doing all 892 * HW-specific initialization, e.g. ULPI-vs-UTMI PHY selection 893 */ 894 if (!ret) { 895 struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; 896 897 /* select ULPI phy */ 898 writel(PTS(PTS_ENABLE) | PFSC, &udc->portsc); 899 } 900 #endif 901 902 ret = driver->bind(&controller.gadget); 903 if (ret) { 904 DBG("driver->bind() returned %d\n", ret); 905 return ret; 906 } 907 controller.driver = driver; 908 909 return 0; 910 } 911 912 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) 913 { 914 udc_disconnect(); 915 916 driver->unbind(&controller.gadget); 917 controller.driver = NULL; 918 919 ci_ep_free_request(&controller.ep[0].ep, &controller.ep0_req->req); 920 free(controller.items_mem); 921 free(controller.epts); 922 923 return 0; 924 } 925