1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * Copyright (C) 2009 NVIDIA, Corporation 4 * Copyright (C) 2007-2008 SMSC (Steve Glendinning) 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <errno.h> 11 #include <malloc.h> 12 #include <usb.h> 13 #include <asm/unaligned.h> 14 #include <linux/mii.h> 15 #include "usb_ether.h" 16 17 /* SMSC LAN95xx based USB 2.0 Ethernet Devices */ 18 19 /* LED defines */ 20 #define LED_GPIO_CFG (0x24) 21 #define LED_GPIO_CFG_SPD_LED (0x01000000) 22 #define LED_GPIO_CFG_LNK_LED (0x00100000) 23 #define LED_GPIO_CFG_FDX_LED (0x00010000) 24 25 /* Tx command words */ 26 #define TX_CMD_A_FIRST_SEG_ 0x00002000 27 #define TX_CMD_A_LAST_SEG_ 0x00001000 28 29 /* Rx status word */ 30 #define RX_STS_FL_ 0x3FFF0000 /* Frame Length */ 31 #define RX_STS_ES_ 0x00008000 /* Error Summary */ 32 33 /* SCSRs */ 34 #define ID_REV 0x00 35 36 #define INT_STS 0x08 37 38 #define TX_CFG 0x10 39 #define TX_CFG_ON_ 0x00000004 40 41 #define HW_CFG 0x14 42 #define HW_CFG_BIR_ 0x00001000 43 #define HW_CFG_RXDOFF_ 0x00000600 44 #define HW_CFG_MEF_ 0x00000020 45 #define HW_CFG_BCE_ 0x00000002 46 #define HW_CFG_LRST_ 0x00000008 47 48 #define PM_CTRL 0x20 49 #define PM_CTL_PHY_RST_ 0x00000010 50 51 #define AFC_CFG 0x2C 52 53 /* 54 * Hi watermark = 15.5Kb (~10 mtu pkts) 55 * low watermark = 3k (~2 mtu pkts) 56 * backpressure duration = ~ 350us 57 * Apply FC on any frame. 58 */ 59 #define AFC_CFG_DEFAULT 0x00F830A1 60 61 #define E2P_CMD 0x30 62 #define E2P_CMD_BUSY_ 0x80000000 63 #define E2P_CMD_READ_ 0x00000000 64 #define E2P_CMD_TIMEOUT_ 0x00000400 65 #define E2P_CMD_LOADED_ 0x00000200 66 #define E2P_CMD_ADDR_ 0x000001FF 67 68 #define E2P_DATA 0x34 69 70 #define BURST_CAP 0x38 71 72 #define INT_EP_CTL 0x68 73 #define INT_EP_CTL_PHY_INT_ 0x00008000 74 75 #define BULK_IN_DLY 0x6C 76 77 /* MAC CSRs */ 78 #define MAC_CR 0x100 79 #define MAC_CR_MCPAS_ 0x00080000 80 #define MAC_CR_PRMS_ 0x00040000 81 #define MAC_CR_HPFILT_ 0x00002000 82 #define MAC_CR_TXEN_ 0x00000008 83 #define MAC_CR_RXEN_ 0x00000004 84 85 #define ADDRH 0x104 86 87 #define ADDRL 0x108 88 89 #define MII_ADDR 0x114 90 #define MII_WRITE_ 0x02 91 #define MII_BUSY_ 0x01 92 #define MII_READ_ 0x00 /* ~of MII Write bit */ 93 94 #define MII_DATA 0x118 95 96 #define FLOW 0x11C 97 98 #define VLAN1 0x120 99 100 #define COE_CR 0x130 101 #define Tx_COE_EN_ 0x00010000 102 #define Rx_COE_EN_ 0x00000001 103 104 /* Vendor-specific PHY Definitions */ 105 #define PHY_INT_SRC 29 106 107 #define PHY_INT_MASK 30 108 #define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040) 109 #define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010) 110 #define PHY_INT_MASK_DEFAULT_ (PHY_INT_MASK_ANEG_COMP_ | \ 111 PHY_INT_MASK_LINK_DOWN_) 112 113 /* USB Vendor Requests */ 114 #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0 115 #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1 116 117 /* Some extra defines */ 118 #define HS_USB_PKT_SIZE 512 119 #define FS_USB_PKT_SIZE 64 120 #define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE) 121 #define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE) 122 #define DEFAULT_BULK_IN_DELAY 0x00002000 123 #define MAX_SINGLE_PACKET_SIZE 2048 124 #define EEPROM_MAC_OFFSET 0x01 125 #define SMSC95XX_INTERNAL_PHY_ID 1 126 #define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */ 127 128 /* local defines */ 129 #define SMSC95XX_BASE_NAME "sms" 130 #define USB_CTRL_SET_TIMEOUT 5000 131 #define USB_CTRL_GET_TIMEOUT 5000 132 #define USB_BULK_SEND_TIMEOUT 5000 133 #define USB_BULK_RECV_TIMEOUT 5000 134 135 #define RX_URB_SIZE 2048 136 #define PHY_CONNECT_TIMEOUT 5000 137 138 #define TURBO_MODE 139 140 /* local vars */ 141 static int curr_eth_dev; /* index for name of next device detected */ 142 143 /* driver private */ 144 struct smsc95xx_private { 145 size_t rx_urb_size; /* maximum USB URB size */ 146 u32 mac_cr; /* MAC control register value */ 147 int have_hwaddr; /* 1 if we have a hardware MAC address */ 148 }; 149 150 /* 151 * Smsc95xx infrastructure commands 152 */ 153 static int smsc95xx_write_reg(struct usb_device *udev, u32 index, u32 data) 154 { 155 int len; 156 ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1); 157 158 cpu_to_le32s(&data); 159 tmpbuf[0] = data; 160 161 len = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 162 USB_VENDOR_REQUEST_WRITE_REGISTER, 163 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 164 0, index, tmpbuf, sizeof(data), 165 USB_CTRL_SET_TIMEOUT); 166 if (len != sizeof(data)) { 167 debug("smsc95xx_write_reg failed: index=%d, data=%d, len=%d", 168 index, data, len); 169 return -EIO; 170 } 171 return 0; 172 } 173 174 static int smsc95xx_read_reg(struct usb_device *udev, u32 index, u32 *data) 175 { 176 int len; 177 ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1); 178 179 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 180 USB_VENDOR_REQUEST_READ_REGISTER, 181 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 182 0, index, tmpbuf, sizeof(data), 183 USB_CTRL_GET_TIMEOUT); 184 *data = tmpbuf[0]; 185 if (len != sizeof(data)) { 186 debug("smsc95xx_read_reg failed: index=%d, len=%d", 187 index, len); 188 return -EIO; 189 } 190 191 le32_to_cpus(data); 192 return 0; 193 } 194 195 /* Loop until the read is completed with timeout */ 196 static int smsc95xx_phy_wait_not_busy(struct usb_device *udev) 197 { 198 unsigned long start_time = get_timer(0); 199 u32 val; 200 201 do { 202 smsc95xx_read_reg(udev, MII_ADDR, &val); 203 if (!(val & MII_BUSY_)) 204 return 0; 205 } while (get_timer(start_time) < 1000); 206 207 return -ETIMEDOUT; 208 } 209 210 static int smsc95xx_mdio_read(struct usb_device *udev, int phy_id, int idx) 211 { 212 u32 val, addr; 213 214 /* confirm MII not busy */ 215 if (smsc95xx_phy_wait_not_busy(udev)) { 216 debug("MII is busy in smsc95xx_mdio_read\n"); 217 return -ETIMEDOUT; 218 } 219 220 /* set the address, index & direction (read from PHY) */ 221 addr = (phy_id << 11) | (idx << 6) | MII_READ_; 222 smsc95xx_write_reg(udev, MII_ADDR, addr); 223 224 if (smsc95xx_phy_wait_not_busy(udev)) { 225 debug("Timed out reading MII reg %02X\n", idx); 226 return -ETIMEDOUT; 227 } 228 229 smsc95xx_read_reg(udev, MII_DATA, &val); 230 231 return (u16)(val & 0xFFFF); 232 } 233 234 static void smsc95xx_mdio_write(struct usb_device *udev, int phy_id, int idx, 235 int regval) 236 { 237 u32 val, addr; 238 239 /* confirm MII not busy */ 240 if (smsc95xx_phy_wait_not_busy(udev)) { 241 debug("MII is busy in smsc95xx_mdio_write\n"); 242 return; 243 } 244 245 val = regval; 246 smsc95xx_write_reg(udev, MII_DATA, val); 247 248 /* set the address, index & direction (write to PHY) */ 249 addr = (phy_id << 11) | (idx << 6) | MII_WRITE_; 250 smsc95xx_write_reg(udev, MII_ADDR, addr); 251 252 if (smsc95xx_phy_wait_not_busy(udev)) 253 debug("Timed out writing MII reg %02X\n", idx); 254 } 255 256 static int smsc95xx_eeprom_confirm_not_busy(struct usb_device *udev) 257 { 258 unsigned long start_time = get_timer(0); 259 u32 val; 260 261 do { 262 smsc95xx_read_reg(udev, E2P_CMD, &val); 263 if (!(val & E2P_CMD_BUSY_)) 264 return 0; 265 udelay(40); 266 } while (get_timer(start_time) < 1 * 1000 * 1000); 267 268 debug("EEPROM is busy\n"); 269 return -ETIMEDOUT; 270 } 271 272 static int smsc95xx_wait_eeprom(struct usb_device *udev) 273 { 274 unsigned long start_time = get_timer(0); 275 u32 val; 276 277 do { 278 smsc95xx_read_reg(udev, E2P_CMD, &val); 279 if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_)) 280 break; 281 udelay(40); 282 } while (get_timer(start_time) < 1 * 1000 * 1000); 283 284 if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) { 285 debug("EEPROM read operation timeout\n"); 286 return -ETIMEDOUT; 287 } 288 return 0; 289 } 290 291 static int smsc95xx_read_eeprom(struct usb_device *udev, u32 offset, u32 length, 292 u8 *data) 293 { 294 u32 val; 295 int i, ret; 296 297 ret = smsc95xx_eeprom_confirm_not_busy(udev); 298 if (ret) 299 return ret; 300 301 for (i = 0; i < length; i++) { 302 val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_); 303 smsc95xx_write_reg(udev, E2P_CMD, val); 304 305 ret = smsc95xx_wait_eeprom(udev); 306 if (ret < 0) 307 return ret; 308 309 smsc95xx_read_reg(udev, E2P_DATA, &val); 310 data[i] = val & 0xFF; 311 offset++; 312 } 313 return 0; 314 } 315 316 /* 317 * mii_nway_restart - restart NWay (autonegotiation) for this interface 318 * 319 * Returns 0 on success, negative on error. 320 */ 321 static int mii_nway_restart(struct usb_device *udev, struct ueth_data *dev) 322 { 323 int bmcr; 324 int r = -1; 325 326 /* if autoneg is off, it's an error */ 327 bmcr = smsc95xx_mdio_read(udev, dev->phy_id, MII_BMCR); 328 329 if (bmcr & BMCR_ANENABLE) { 330 bmcr |= BMCR_ANRESTART; 331 smsc95xx_mdio_write(udev, dev->phy_id, MII_BMCR, bmcr); 332 r = 0; 333 } 334 return r; 335 } 336 337 static int smsc95xx_phy_initialize(struct usb_device *udev, 338 struct ueth_data *dev) 339 { 340 smsc95xx_mdio_write(udev, dev->phy_id, MII_BMCR, BMCR_RESET); 341 smsc95xx_mdio_write(udev, dev->phy_id, MII_ADVERTISE, 342 ADVERTISE_ALL | ADVERTISE_CSMA | 343 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); 344 345 /* read to clear */ 346 smsc95xx_mdio_read(udev, dev->phy_id, PHY_INT_SRC); 347 348 smsc95xx_mdio_write(udev, dev->phy_id, PHY_INT_MASK, 349 PHY_INT_MASK_DEFAULT_); 350 mii_nway_restart(udev, dev); 351 352 debug("phy initialised succesfully\n"); 353 return 0; 354 } 355 356 static int smsc95xx_init_mac_address(unsigned char *enetaddr, 357 struct usb_device *udev) 358 { 359 int ret; 360 361 /* try reading mac address from EEPROM */ 362 ret = smsc95xx_read_eeprom(udev, EEPROM_MAC_OFFSET, ETH_ALEN, enetaddr); 363 if (ret) 364 return ret; 365 366 if (is_valid_ethaddr(enetaddr)) { 367 /* eeprom values are valid so use them */ 368 debug("MAC address read from EEPROM\n"); 369 return 0; 370 } 371 372 /* 373 * No eeprom, or eeprom values are invalid. Generating a random MAC 374 * address is not safe. Just return an error. 375 */ 376 debug("Invalid MAC address read from EEPROM\n"); 377 378 return -ENXIO; 379 } 380 381 static int smsc95xx_write_hwaddr_common(struct usb_device *udev, 382 struct smsc95xx_private *priv, 383 unsigned char *enetaddr) 384 { 385 u32 addr_lo = __get_unaligned_le32(&enetaddr[0]); 386 u32 addr_hi = __get_unaligned_le16(&enetaddr[4]); 387 int ret; 388 389 /* set hardware address */ 390 debug("** %s()\n", __func__); 391 ret = smsc95xx_write_reg(udev, ADDRL, addr_lo); 392 if (ret < 0) 393 return ret; 394 395 ret = smsc95xx_write_reg(udev, ADDRH, addr_hi); 396 if (ret < 0) 397 return ret; 398 399 debug("MAC %pM\n", enetaddr); 400 priv->have_hwaddr = 1; 401 402 return 0; 403 } 404 405 /* Enable or disable Tx & Rx checksum offload engines */ 406 static int smsc95xx_set_csums(struct usb_device *udev, int use_tx_csum, 407 int use_rx_csum) 408 { 409 u32 read_buf; 410 int ret = smsc95xx_read_reg(udev, COE_CR, &read_buf); 411 if (ret < 0) 412 return ret; 413 414 if (use_tx_csum) 415 read_buf |= Tx_COE_EN_; 416 else 417 read_buf &= ~Tx_COE_EN_; 418 419 if (use_rx_csum) 420 read_buf |= Rx_COE_EN_; 421 else 422 read_buf &= ~Rx_COE_EN_; 423 424 ret = smsc95xx_write_reg(udev, COE_CR, read_buf); 425 if (ret < 0) 426 return ret; 427 428 debug("COE_CR = 0x%08x\n", read_buf); 429 return 0; 430 } 431 432 static void smsc95xx_set_multicast(struct smsc95xx_private *priv) 433 { 434 /* No multicast in u-boot */ 435 priv->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_); 436 } 437 438 /* starts the TX path */ 439 static void smsc95xx_start_tx_path(struct usb_device *udev, 440 struct smsc95xx_private *priv) 441 { 442 u32 reg_val; 443 444 /* Enable Tx at MAC */ 445 priv->mac_cr |= MAC_CR_TXEN_; 446 447 smsc95xx_write_reg(udev, MAC_CR, priv->mac_cr); 448 449 /* Enable Tx at SCSRs */ 450 reg_val = TX_CFG_ON_; 451 smsc95xx_write_reg(udev, TX_CFG, reg_val); 452 } 453 454 /* Starts the Receive path */ 455 static void smsc95xx_start_rx_path(struct usb_device *udev, 456 struct smsc95xx_private *priv) 457 { 458 priv->mac_cr |= MAC_CR_RXEN_; 459 smsc95xx_write_reg(udev, MAC_CR, priv->mac_cr); 460 } 461 462 static int smsc95xx_init_common(struct usb_device *udev, struct ueth_data *dev, 463 struct smsc95xx_private *priv, 464 unsigned char *enetaddr) 465 { 466 int ret; 467 u32 write_buf; 468 u32 read_buf; 469 u32 burst_cap; 470 int timeout; 471 #define TIMEOUT_RESOLUTION 50 /* ms */ 472 int link_detected; 473 474 debug("** %s()\n", __func__); 475 dev->phy_id = SMSC95XX_INTERNAL_PHY_ID; /* fixed phy id */ 476 477 write_buf = HW_CFG_LRST_; 478 ret = smsc95xx_write_reg(udev, HW_CFG, write_buf); 479 if (ret < 0) 480 return ret; 481 482 timeout = 0; 483 do { 484 ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf); 485 if (ret < 0) 486 return ret; 487 udelay(10 * 1000); 488 timeout++; 489 } while ((read_buf & HW_CFG_LRST_) && (timeout < 100)); 490 491 if (timeout >= 100) { 492 debug("timeout waiting for completion of Lite Reset\n"); 493 return -ETIMEDOUT; 494 } 495 496 write_buf = PM_CTL_PHY_RST_; 497 ret = smsc95xx_write_reg(udev, PM_CTRL, write_buf); 498 if (ret < 0) 499 return ret; 500 501 timeout = 0; 502 do { 503 ret = smsc95xx_read_reg(udev, PM_CTRL, &read_buf); 504 if (ret < 0) 505 return ret; 506 udelay(10 * 1000); 507 timeout++; 508 } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100)); 509 if (timeout >= 100) { 510 debug("timeout waiting for PHY Reset\n"); 511 return -ETIMEDOUT; 512 } 513 if (!priv->have_hwaddr && smsc95xx_init_mac_address(enetaddr, udev) == 514 0) 515 priv->have_hwaddr = 1; 516 if (!priv->have_hwaddr) { 517 puts("Error: SMSC95xx: No MAC address set - set usbethaddr\n"); 518 return -EADDRNOTAVAIL; 519 } 520 ret = smsc95xx_write_hwaddr_common(udev, priv, enetaddr); 521 if (ret < 0) 522 return ret; 523 524 ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf); 525 if (ret < 0) 526 return ret; 527 debug("Read Value from HW_CFG : 0x%08x\n", read_buf); 528 529 read_buf |= HW_CFG_BIR_; 530 ret = smsc95xx_write_reg(udev, HW_CFG, read_buf); 531 if (ret < 0) 532 return ret; 533 534 ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf); 535 if (ret < 0) 536 return ret; 537 debug("Read Value from HW_CFG after writing " 538 "HW_CFG_BIR_: 0x%08x\n", read_buf); 539 540 #ifdef TURBO_MODE 541 if (dev->pusb_dev->speed == USB_SPEED_HIGH) { 542 burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE; 543 priv->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE; 544 } else { 545 burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE; 546 priv->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE; 547 } 548 #else 549 burst_cap = 0; 550 priv->rx_urb_size = MAX_SINGLE_PACKET_SIZE; 551 #endif 552 debug("rx_urb_size=%ld\n", (ulong)priv->rx_urb_size); 553 554 ret = smsc95xx_write_reg(udev, BURST_CAP, burst_cap); 555 if (ret < 0) 556 return ret; 557 558 ret = smsc95xx_read_reg(udev, BURST_CAP, &read_buf); 559 if (ret < 0) 560 return ret; 561 debug("Read Value from BURST_CAP after writing: 0x%08x\n", read_buf); 562 563 read_buf = DEFAULT_BULK_IN_DELAY; 564 ret = smsc95xx_write_reg(udev, BULK_IN_DLY, read_buf); 565 if (ret < 0) 566 return ret; 567 568 ret = smsc95xx_read_reg(udev, BULK_IN_DLY, &read_buf); 569 if (ret < 0) 570 return ret; 571 debug("Read Value from BULK_IN_DLY after writing: " 572 "0x%08x\n", read_buf); 573 574 ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf); 575 if (ret < 0) 576 return ret; 577 debug("Read Value from HW_CFG: 0x%08x\n", read_buf); 578 579 #ifdef TURBO_MODE 580 read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_); 581 #endif 582 read_buf &= ~HW_CFG_RXDOFF_; 583 584 #define NET_IP_ALIGN 0 585 read_buf |= NET_IP_ALIGN << 9; 586 587 ret = smsc95xx_write_reg(udev, HW_CFG, read_buf); 588 if (ret < 0) 589 return ret; 590 591 ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf); 592 if (ret < 0) 593 return ret; 594 debug("Read Value from HW_CFG after writing: 0x%08x\n", read_buf); 595 596 write_buf = 0xFFFFFFFF; 597 ret = smsc95xx_write_reg(udev, INT_STS, write_buf); 598 if (ret < 0) 599 return ret; 600 601 ret = smsc95xx_read_reg(udev, ID_REV, &read_buf); 602 if (ret < 0) 603 return ret; 604 debug("ID_REV = 0x%08x\n", read_buf); 605 606 /* Configure GPIO pins as LED outputs */ 607 write_buf = LED_GPIO_CFG_SPD_LED | LED_GPIO_CFG_LNK_LED | 608 LED_GPIO_CFG_FDX_LED; 609 ret = smsc95xx_write_reg(udev, LED_GPIO_CFG, write_buf); 610 if (ret < 0) 611 return ret; 612 debug("LED_GPIO_CFG set\n"); 613 614 /* Init Tx */ 615 write_buf = 0; 616 ret = smsc95xx_write_reg(udev, FLOW, write_buf); 617 if (ret < 0) 618 return ret; 619 620 read_buf = AFC_CFG_DEFAULT; 621 ret = smsc95xx_write_reg(udev, AFC_CFG, read_buf); 622 if (ret < 0) 623 return ret; 624 625 ret = smsc95xx_read_reg(udev, MAC_CR, &priv->mac_cr); 626 if (ret < 0) 627 return ret; 628 629 /* Init Rx. Set Vlan */ 630 write_buf = (u32)ETH_P_8021Q; 631 ret = smsc95xx_write_reg(udev, VLAN1, write_buf); 632 if (ret < 0) 633 return ret; 634 635 /* Disable checksum offload engines */ 636 ret = smsc95xx_set_csums(udev, 0, 0); 637 if (ret < 0) { 638 debug("Failed to set csum offload: %d\n", ret); 639 return ret; 640 } 641 smsc95xx_set_multicast(priv); 642 643 ret = smsc95xx_phy_initialize(udev, dev); 644 if (ret < 0) 645 return ret; 646 ret = smsc95xx_read_reg(udev, INT_EP_CTL, &read_buf); 647 if (ret < 0) 648 return ret; 649 650 /* enable PHY interrupts */ 651 read_buf |= INT_EP_CTL_PHY_INT_; 652 653 ret = smsc95xx_write_reg(udev, INT_EP_CTL, read_buf); 654 if (ret < 0) 655 return ret; 656 657 smsc95xx_start_tx_path(udev, priv); 658 smsc95xx_start_rx_path(udev, priv); 659 660 timeout = 0; 661 do { 662 link_detected = smsc95xx_mdio_read(udev, dev->phy_id, MII_BMSR) 663 & BMSR_LSTATUS; 664 if (!link_detected) { 665 if (timeout == 0) 666 printf("Waiting for Ethernet connection... "); 667 udelay(TIMEOUT_RESOLUTION * 1000); 668 timeout += TIMEOUT_RESOLUTION; 669 } 670 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT); 671 if (link_detected) { 672 if (timeout != 0) 673 printf("done.\n"); 674 } else { 675 printf("unable to connect.\n"); 676 return -EIO; 677 } 678 return 0; 679 } 680 681 static int smsc95xx_send_common(struct ueth_data *dev, void *packet, int length) 682 { 683 int err; 684 int actual_len; 685 u32 tx_cmd_a; 686 u32 tx_cmd_b; 687 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg, 688 PKTSIZE + sizeof(tx_cmd_a) + sizeof(tx_cmd_b)); 689 690 debug("** %s(), len %d, buf %#x\n", __func__, length, (int)msg); 691 if (length > PKTSIZE) 692 return -ENOSPC; 693 694 tx_cmd_a = (u32)length | TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_; 695 tx_cmd_b = (u32)length; 696 cpu_to_le32s(&tx_cmd_a); 697 cpu_to_le32s(&tx_cmd_b); 698 699 /* prepend cmd_a and cmd_b */ 700 memcpy(msg, &tx_cmd_a, sizeof(tx_cmd_a)); 701 memcpy(msg + sizeof(tx_cmd_a), &tx_cmd_b, sizeof(tx_cmd_b)); 702 memcpy(msg + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), (void *)packet, 703 length); 704 err = usb_bulk_msg(dev->pusb_dev, 705 usb_sndbulkpipe(dev->pusb_dev, dev->ep_out), 706 (void *)msg, 707 length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), 708 &actual_len, 709 USB_BULK_SEND_TIMEOUT); 710 debug("Tx: len = %u, actual = %u, err = %d\n", 711 length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), 712 actual_len, err); 713 714 return err; 715 } 716 717 /* 718 * Smsc95xx callbacks 719 */ 720 static int smsc95xx_init(struct eth_device *eth, bd_t *bd) 721 { 722 struct ueth_data *dev = (struct ueth_data *)eth->priv; 723 struct usb_device *udev = dev->pusb_dev; 724 struct smsc95xx_private *priv = 725 (struct smsc95xx_private *)dev->dev_priv; 726 727 return smsc95xx_init_common(udev, dev, priv, eth->enetaddr); 728 } 729 730 static int smsc95xx_send(struct eth_device *eth, void *packet, int length) 731 { 732 struct ueth_data *dev = (struct ueth_data *)eth->priv; 733 734 return smsc95xx_send_common(dev, packet, length); 735 } 736 737 static int smsc95xx_recv(struct eth_device *eth) 738 { 739 struct ueth_data *dev = (struct ueth_data *)eth->priv; 740 DEFINE_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, RX_URB_SIZE); 741 unsigned char *buf_ptr; 742 int err; 743 int actual_len; 744 u32 packet_len; 745 int cur_buf_align; 746 747 debug("** %s()\n", __func__); 748 err = usb_bulk_msg(dev->pusb_dev, 749 usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in), 750 (void *)recv_buf, RX_URB_SIZE, &actual_len, 751 USB_BULK_RECV_TIMEOUT); 752 debug("Rx: len = %u, actual = %u, err = %d\n", RX_URB_SIZE, 753 actual_len, err); 754 if (err != 0) { 755 debug("Rx: failed to receive\n"); 756 return -err; 757 } 758 if (actual_len > RX_URB_SIZE) { 759 debug("Rx: received too many bytes %d\n", actual_len); 760 return -ENOSPC; 761 } 762 763 buf_ptr = recv_buf; 764 while (actual_len > 0) { 765 /* 766 * 1st 4 bytes contain the length of the actual data plus error 767 * info. Extract data length. 768 */ 769 if (actual_len < sizeof(packet_len)) { 770 debug("Rx: incomplete packet length\n"); 771 return -EIO; 772 } 773 memcpy(&packet_len, buf_ptr, sizeof(packet_len)); 774 le32_to_cpus(&packet_len); 775 if (packet_len & RX_STS_ES_) { 776 debug("Rx: Error header=%#x", packet_len); 777 return -EIO; 778 } 779 packet_len = ((packet_len & RX_STS_FL_) >> 16); 780 781 if (packet_len > actual_len - sizeof(packet_len)) { 782 debug("Rx: too large packet: %d\n", packet_len); 783 return -EIO; 784 } 785 786 /* Notify net stack */ 787 net_process_received_packet(buf_ptr + sizeof(packet_len), 788 packet_len - 4); 789 790 /* Adjust for next iteration */ 791 actual_len -= sizeof(packet_len) + packet_len; 792 buf_ptr += sizeof(packet_len) + packet_len; 793 cur_buf_align = (int)buf_ptr - (int)recv_buf; 794 795 if (cur_buf_align & 0x03) { 796 int align = 4 - (cur_buf_align & 0x03); 797 798 actual_len -= align; 799 buf_ptr += align; 800 } 801 } 802 return err; 803 } 804 805 static void smsc95xx_halt(struct eth_device *eth) 806 { 807 debug("** %s()\n", __func__); 808 } 809 810 static int smsc95xx_write_hwaddr(struct eth_device *eth) 811 { 812 struct ueth_data *dev = eth->priv; 813 struct usb_device *udev = dev->pusb_dev; 814 struct smsc95xx_private *priv = dev->dev_priv; 815 816 return smsc95xx_write_hwaddr_common(udev, priv, eth->enetaddr); 817 } 818 819 /* 820 * SMSC probing functions 821 */ 822 void smsc95xx_eth_before_probe(void) 823 { 824 curr_eth_dev = 0; 825 } 826 827 struct smsc95xx_dongle { 828 unsigned short vendor; 829 unsigned short product; 830 }; 831 832 static const struct smsc95xx_dongle smsc95xx_dongles[] = { 833 { 0x0424, 0xec00 }, /* LAN9512/LAN9514 Ethernet */ 834 { 0x0424, 0x9500 }, /* LAN9500 Ethernet */ 835 { 0x0424, 0x9730 }, /* LAN9730 Ethernet (HSIC) */ 836 { 0x0424, 0x9900 }, /* SMSC9500 USB Ethernet Device (SAL10) */ 837 { 0x0424, 0x9e00 }, /* LAN9500A Ethernet */ 838 { 0x0000, 0x0000 } /* END - Do not remove */ 839 }; 840 841 /* Probe to see if a new device is actually an SMSC device */ 842 int smsc95xx_eth_probe(struct usb_device *dev, unsigned int ifnum, 843 struct ueth_data *ss) 844 { 845 struct usb_interface *iface; 846 struct usb_interface_descriptor *iface_desc; 847 int i; 848 849 /* let's examine the device now */ 850 iface = &dev->config.if_desc[ifnum]; 851 iface_desc = &dev->config.if_desc[ifnum].desc; 852 853 for (i = 0; smsc95xx_dongles[i].vendor != 0; i++) { 854 if (dev->descriptor.idVendor == smsc95xx_dongles[i].vendor && 855 dev->descriptor.idProduct == smsc95xx_dongles[i].product) 856 /* Found a supported dongle */ 857 break; 858 } 859 if (smsc95xx_dongles[i].vendor == 0) 860 return 0; 861 862 /* At this point, we know we've got a live one */ 863 debug("\n\nUSB Ethernet device detected\n"); 864 memset(ss, '\0', sizeof(struct ueth_data)); 865 866 /* Initialize the ueth_data structure with some useful info */ 867 ss->ifnum = ifnum; 868 ss->pusb_dev = dev; 869 ss->subclass = iface_desc->bInterfaceSubClass; 870 ss->protocol = iface_desc->bInterfaceProtocol; 871 872 /* 873 * We are expecting a minimum of 3 endpoints - in, out (bulk), and int. 874 * We will ignore any others. 875 */ 876 for (i = 0; i < iface_desc->bNumEndpoints; i++) { 877 /* is it an BULK endpoint? */ 878 if ((iface->ep_desc[i].bmAttributes & 879 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) { 880 if (iface->ep_desc[i].bEndpointAddress & USB_DIR_IN) 881 ss->ep_in = 882 iface->ep_desc[i].bEndpointAddress & 883 USB_ENDPOINT_NUMBER_MASK; 884 else 885 ss->ep_out = 886 iface->ep_desc[i].bEndpointAddress & 887 USB_ENDPOINT_NUMBER_MASK; 888 } 889 890 /* is it an interrupt endpoint? */ 891 if ((iface->ep_desc[i].bmAttributes & 892 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) { 893 ss->ep_int = iface->ep_desc[i].bEndpointAddress & 894 USB_ENDPOINT_NUMBER_MASK; 895 ss->irqinterval = iface->ep_desc[i].bInterval; 896 } 897 } 898 debug("Endpoints In %d Out %d Int %d\n", 899 ss->ep_in, ss->ep_out, ss->ep_int); 900 901 /* Do some basic sanity checks, and bail if we find a problem */ 902 if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) || 903 !ss->ep_in || !ss->ep_out || !ss->ep_int) { 904 debug("Problems with device\n"); 905 return 0; 906 } 907 dev->privptr = (void *)ss; 908 909 /* alloc driver private */ 910 ss->dev_priv = calloc(1, sizeof(struct smsc95xx_private)); 911 if (!ss->dev_priv) 912 return 0; 913 914 return 1; 915 } 916 917 int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss, 918 struct eth_device *eth) 919 { 920 debug("** %s()\n", __func__); 921 if (!eth) { 922 debug("%s: missing parameter.\n", __func__); 923 return 0; 924 } 925 sprintf(eth->name, "%s%d", SMSC95XX_BASE_NAME, curr_eth_dev++); 926 eth->init = smsc95xx_init; 927 eth->send = smsc95xx_send; 928 eth->recv = smsc95xx_recv; 929 eth->halt = smsc95xx_halt; 930 eth->write_hwaddr = smsc95xx_write_hwaddr; 931 eth->priv = ss; 932 return 1; 933 } 934