1 /* 2 * Copyright (c) 2014 Rene Griessl <rgriessl@cit-ec.uni-bielefeld.de> 3 * based on the U-Boot Asix driver as well as information 4 * from the Linux AX88179_178a driver 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <usb.h> 11 #include <net.h> 12 #include <linux/mii.h> 13 #include "usb_ether.h" 14 #include <malloc.h> 15 #include <memalign.h> 16 #include <errno.h> 17 18 /* ASIX AX88179 based USB 3.0 Ethernet Devices */ 19 #define AX88179_PHY_ID 0x03 20 #define AX_EEPROM_LEN 0x100 21 #define AX88179_EEPROM_MAGIC 0x17900b95 22 #define AX_MCAST_FLTSIZE 8 23 #define AX_MAX_MCAST 64 24 #define AX_INT_PPLS_LINK (1 << 16) 25 #define AX_RXHDR_L4_TYPE_MASK 0x1c 26 #define AX_RXHDR_L4_TYPE_UDP 4 27 #define AX_RXHDR_L4_TYPE_TCP 16 28 #define AX_RXHDR_L3CSUM_ERR 2 29 #define AX_RXHDR_L4CSUM_ERR 1 30 #define AX_RXHDR_CRC_ERR (1 << 29) 31 #define AX_RXHDR_DROP_ERR (1 << 31) 32 #define AX_ENDPOINT_INT 0x01 33 #define AX_ENDPOINT_IN 0x02 34 #define AX_ENDPOINT_OUT 0x03 35 #define AX_ACCESS_MAC 0x01 36 #define AX_ACCESS_PHY 0x02 37 #define AX_ACCESS_EEPROM 0x04 38 #define AX_ACCESS_EFUS 0x05 39 #define AX_PAUSE_WATERLVL_HIGH 0x54 40 #define AX_PAUSE_WATERLVL_LOW 0x55 41 42 #define PHYSICAL_LINK_STATUS 0x02 43 #define AX_USB_SS (1 << 2) 44 #define AX_USB_HS (1 << 1) 45 46 #define GENERAL_STATUS 0x03 47 #define AX_SECLD (1 << 2) 48 49 #define AX_SROM_ADDR 0x07 50 #define AX_SROM_CMD 0x0a 51 #define EEP_RD (1 << 2) 52 #define EEP_BUSY (1 << 4) 53 54 #define AX_SROM_DATA_LOW 0x08 55 #define AX_SROM_DATA_HIGH 0x09 56 57 #define AX_RX_CTL 0x0b 58 #define AX_RX_CTL_DROPCRCERR (1 << 8) 59 #define AX_RX_CTL_IPE (1 << 9) 60 #define AX_RX_CTL_START (1 << 7) 61 #define AX_RX_CTL_AP (1 << 5) 62 #define AX_RX_CTL_AM (1 << 4) 63 #define AX_RX_CTL_AB (1 << 3) 64 #define AX_RX_CTL_AMALL (1 << 1) 65 #define AX_RX_CTL_PRO (1 << 0) 66 #define AX_RX_CTL_STOP 0 67 68 #define AX_NODE_ID 0x10 69 #define AX_MULFLTARY 0x16 70 71 #define AX_MEDIUM_STATUS_MODE 0x22 72 #define AX_MEDIUM_GIGAMODE (1 << 0) 73 #define AX_MEDIUM_FULL_DUPLEX (1 << 1) 74 #define AX_MEDIUM_EN_125MHZ (1 << 3) 75 #define AX_MEDIUM_RXFLOW_CTRLEN (1 << 4) 76 #define AX_MEDIUM_TXFLOW_CTRLEN (1 << 5) 77 #define AX_MEDIUM_RECEIVE_EN (1 << 8) 78 #define AX_MEDIUM_PS (1 << 9) 79 #define AX_MEDIUM_JUMBO_EN 0x8040 80 81 #define AX_MONITOR_MOD 0x24 82 #define AX_MONITOR_MODE_RWLC (1 << 1) 83 #define AX_MONITOR_MODE_RWMP (1 << 2) 84 #define AX_MONITOR_MODE_PMEPOL (1 << 5) 85 #define AX_MONITOR_MODE_PMETYPE (1 << 6) 86 87 #define AX_GPIO_CTRL 0x25 88 #define AX_GPIO_CTRL_GPIO3EN (1 << 7) 89 #define AX_GPIO_CTRL_GPIO2EN (1 << 6) 90 #define AX_GPIO_CTRL_GPIO1EN (1 << 5) 91 92 #define AX_PHYPWR_RSTCTL 0x26 93 #define AX_PHYPWR_RSTCTL_BZ (1 << 4) 94 #define AX_PHYPWR_RSTCTL_IPRL (1 << 5) 95 #define AX_PHYPWR_RSTCTL_AT (1 << 12) 96 97 #define AX_RX_BULKIN_QCTRL 0x2e 98 #define AX_CLK_SELECT 0x33 99 #define AX_CLK_SELECT_BCS (1 << 0) 100 #define AX_CLK_SELECT_ACS (1 << 1) 101 #define AX_CLK_SELECT_ULR (1 << 3) 102 103 #define AX_RXCOE_CTL 0x34 104 #define AX_RXCOE_IP (1 << 0) 105 #define AX_RXCOE_TCP (1 << 1) 106 #define AX_RXCOE_UDP (1 << 2) 107 #define AX_RXCOE_TCPV6 (1 << 5) 108 #define AX_RXCOE_UDPV6 (1 << 6) 109 110 #define AX_TXCOE_CTL 0x35 111 #define AX_TXCOE_IP (1 << 0) 112 #define AX_TXCOE_TCP (1 << 1) 113 #define AX_TXCOE_UDP (1 << 2) 114 #define AX_TXCOE_TCPV6 (1 << 5) 115 #define AX_TXCOE_UDPV6 (1 << 6) 116 117 #define AX_LEDCTRL 0x73 118 119 #define GMII_PHY_PHYSR 0x11 120 #define GMII_PHY_PHYSR_SMASK 0xc000 121 #define GMII_PHY_PHYSR_GIGA (1 << 15) 122 #define GMII_PHY_PHYSR_100 (1 << 14) 123 #define GMII_PHY_PHYSR_FULL (1 << 13) 124 #define GMII_PHY_PHYSR_LINK (1 << 10) 125 126 #define GMII_LED_ACT 0x1a 127 #define GMII_LED_ACTIVE_MASK 0xff8f 128 #define GMII_LED0_ACTIVE (1 << 4) 129 #define GMII_LED1_ACTIVE (1 << 5) 130 #define GMII_LED2_ACTIVE (1 << 6) 131 132 #define GMII_LED_LINK 0x1c 133 #define GMII_LED_LINK_MASK 0xf888 134 #define GMII_LED0_LINK_10 (1 << 0) 135 #define GMII_LED0_LINK_100 (1 << 1) 136 #define GMII_LED0_LINK_1000 (1 << 2) 137 #define GMII_LED1_LINK_10 (1 << 4) 138 #define GMII_LED1_LINK_100 (1 << 5) 139 #define GMII_LED1_LINK_1000 (1 << 6) 140 #define GMII_LED2_LINK_10 (1 << 8) 141 #define GMII_LED2_LINK_100 (1 << 9) 142 #define GMII_LED2_LINK_1000 (1 << 10) 143 #define LED0_ACTIVE (1 << 0) 144 #define LED0_LINK_10 (1 << 1) 145 #define LED0_LINK_100 (1 << 2) 146 #define LED0_LINK_1000 (1 << 3) 147 #define LED0_FD (1 << 4) 148 #define LED0_USB3_MASK 0x001f 149 #define LED1_ACTIVE (1 << 5) 150 #define LED1_LINK_10 (1 << 6) 151 #define LED1_LINK_100 (1 << 7) 152 #define LED1_LINK_1000 (1 << 8) 153 #define LED1_FD (1 << 9) 154 #define LED1_USB3_MASK 0x03e0 155 #define LED2_ACTIVE (1 << 10) 156 #define LED2_LINK_1000 (1 << 13) 157 #define LED2_LINK_100 (1 << 12) 158 #define LED2_LINK_10 (1 << 11) 159 #define LED2_FD (1 << 14) 160 #define LED_VALID (1 << 15) 161 #define LED2_USB3_MASK 0x7c00 162 163 #define GMII_PHYPAGE 0x1e 164 #define GMII_PHY_PAGE_SELECT 0x1f 165 #define GMII_PHY_PGSEL_EXT 0x0007 166 #define GMII_PHY_PGSEL_PAGE0 0x0000 167 168 /* local defines */ 169 #define ASIX_BASE_NAME "axg" 170 #define USB_CTRL_SET_TIMEOUT 5000 171 #define USB_CTRL_GET_TIMEOUT 5000 172 #define USB_BULK_SEND_TIMEOUT 5000 173 #define USB_BULK_RECV_TIMEOUT 5000 174 175 #define AX_RX_URB_SIZE 1024 * 0x12 176 #define BLK_FRAME_SIZE 0x200 177 #define PHY_CONNECT_TIMEOUT 5000 178 179 #define TIMEOUT_RESOLUTION 50 /* ms */ 180 181 #define FLAG_NONE 0 182 #define FLAG_TYPE_AX88179 (1U << 0) 183 #define FLAG_TYPE_AX88178a (1U << 1) 184 #define FLAG_TYPE_DLINK_DUB1312 (1U << 2) 185 #define FLAG_TYPE_SITECOM (1U << 3) 186 #define FLAG_TYPE_SAMSUNG (1U << 4) 187 #define FLAG_TYPE_LENOVO (1U << 5) 188 #define FLAG_TYPE_GX3 (1U << 6) 189 190 /* local vars */ 191 static const struct { 192 unsigned char ctrl, timer_l, timer_h, size, ifg; 193 } AX88179_BULKIN_SIZE[] = { 194 {7, 0x4f, 0, 0x02, 0xff}, 195 {7, 0x20, 3, 0x03, 0xff}, 196 {7, 0xae, 7, 0x04, 0xff}, 197 {7, 0xcc, 0x4c, 0x04, 8}, 198 }; 199 200 static int curr_eth_dev; /* index for name of next device detected */ 201 202 /* driver private */ 203 struct asix_private { 204 int flags; 205 int rx_urb_size; 206 int maxpacketsize; 207 }; 208 209 /* 210 * Asix infrastructure commands 211 */ 212 static int asix_write_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index, 213 u16 size, void *data) 214 { 215 int len; 216 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, size); 217 218 debug("asix_write_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n", 219 cmd, value, index, size); 220 221 memcpy(buf, data, size); 222 223 len = usb_control_msg( 224 dev->pusb_dev, 225 usb_sndctrlpipe(dev->pusb_dev, 0), 226 cmd, 227 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 228 value, 229 index, 230 buf, 231 size, 232 USB_CTRL_SET_TIMEOUT); 233 234 return len == size ? 0 : ECOMM; 235 } 236 237 static int asix_read_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index, 238 u16 size, void *data) 239 { 240 int len; 241 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, size); 242 243 debug("asix_read_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n", 244 cmd, value, index, size); 245 246 len = usb_control_msg( 247 dev->pusb_dev, 248 usb_rcvctrlpipe(dev->pusb_dev, 0), 249 cmd, 250 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 251 value, 252 index, 253 buf, 254 size, 255 USB_CTRL_GET_TIMEOUT); 256 257 memcpy(data, buf, size); 258 259 return len == size ? 0 : ECOMM; 260 } 261 262 static int asix_read_mac(struct eth_device *eth) 263 { 264 struct ueth_data *dev = (struct ueth_data *)eth->priv; 265 u8 buf[ETH_ALEN]; 266 267 asix_read_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, 6, 6, buf); 268 debug("asix_read_mac() returning %02x:%02x:%02x:%02x:%02x:%02x\n", 269 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); 270 271 memcpy(eth->enetaddr, buf, ETH_ALEN); 272 273 return 0; 274 } 275 276 static int asix_write_mac(struct eth_device *eth) 277 { 278 struct ueth_data *dev = (struct ueth_data *)eth->priv; 279 int ret; 280 281 ret = asix_write_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN, 282 ETH_ALEN, eth->enetaddr); 283 if (ret < 0) 284 debug("Failed to set MAC address: %02x\n", ret); 285 286 return ret; 287 } 288 289 static int asix_basic_reset(struct ueth_data *dev) 290 { 291 struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv; 292 u8 buf[5]; 293 u16 *tmp16; 294 u8 *tmp; 295 296 tmp16 = (u16 *)buf; 297 tmp = (u8 *)buf; 298 299 /* Power up ethernet PHY */ 300 *tmp16 = 0; 301 asix_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16); 302 303 *tmp16 = AX_PHYPWR_RSTCTL_IPRL; 304 asix_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16); 305 mdelay(200); 306 307 *tmp = AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS; 308 asix_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, tmp); 309 mdelay(200); 310 311 /* RX bulk configuration */ 312 memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5); 313 asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp); 314 315 dev_priv->rx_urb_size = 128 * 20; 316 317 /* Water Level configuration */ 318 *tmp = 0x34; 319 asix_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_LOW, 1, 1, tmp); 320 321 *tmp = 0x52; 322 asix_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_HIGH, 1, 1, tmp); 323 324 /* Enable checksum offload */ 325 *tmp = AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP | 326 AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6; 327 asix_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, tmp); 328 329 *tmp = AX_TXCOE_IP | AX_TXCOE_TCP | AX_TXCOE_UDP | 330 AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6; 331 asix_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, tmp); 332 333 /* Configure RX control register => start operation */ 334 *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START | 335 AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB; 336 asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16); 337 338 *tmp = AX_MONITOR_MODE_PMETYPE | AX_MONITOR_MODE_PMEPOL | 339 AX_MONITOR_MODE_RWMP; 340 asix_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 1, 1, tmp); 341 342 /* Configure default medium type => giga */ 343 *tmp16 = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN | 344 AX_MEDIUM_RXFLOW_CTRLEN | AX_MEDIUM_FULL_DUPLEX | 345 AX_MEDIUM_GIGAMODE | AX_MEDIUM_JUMBO_EN; 346 asix_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 2, 2, tmp16); 347 348 u16 adv = 0; 349 adv = ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_LPACK | 350 ADVERTISE_NPAGE | ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP; 351 asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_ADVERTISE, 2, &adv); 352 353 adv = ADVERTISE_1000FULL; 354 asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_CTRL1000, 2, &adv); 355 356 return 0; 357 } 358 359 static int asix_wait_link(struct ueth_data *dev) 360 { 361 int timeout = 0; 362 int link_detected; 363 u8 buf[2]; 364 u16 *tmp16; 365 366 tmp16 = (u16 *)buf; 367 368 do { 369 asix_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 370 MII_BMSR, 2, buf); 371 link_detected = *tmp16 & BMSR_LSTATUS; 372 if (!link_detected) { 373 if (timeout == 0) 374 printf("Waiting for Ethernet connection... "); 375 mdelay(TIMEOUT_RESOLUTION); 376 timeout += TIMEOUT_RESOLUTION; 377 } 378 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT); 379 380 if (link_detected) { 381 if (timeout > 0) 382 printf("done.\n"); 383 return 0; 384 } else { 385 printf("unable to connect.\n"); 386 return -ENETUNREACH; 387 } 388 } 389 390 /* 391 * Asix callbacks 392 */ 393 static int asix_init(struct eth_device *eth, bd_t *bd) 394 { 395 struct ueth_data *dev = (struct ueth_data *)eth->priv; 396 struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv; 397 u8 buf[2], tmp[5], link_sts; 398 u16 *tmp16, mode; 399 400 401 tmp16 = (u16 *)buf; 402 403 debug("** %s()\n", __func__); 404 405 /* Configure RX control register => start operation */ 406 *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START | 407 AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB; 408 if (asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16) != 0) 409 goto out_err; 410 411 if (asix_wait_link(dev) != 0) { 412 /*reset device and try again*/ 413 printf("Reset Ethernet Device\n"); 414 asix_basic_reset(dev); 415 if (asix_wait_link(dev) != 0) 416 goto out_err; 417 } 418 419 /* Configure link */ 420 mode = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN | 421 AX_MEDIUM_RXFLOW_CTRLEN; 422 423 asix_read_cmd(dev, AX_ACCESS_MAC, PHYSICAL_LINK_STATUS, 424 1, 1, &link_sts); 425 426 asix_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 427 GMII_PHY_PHYSR, 2, tmp16); 428 429 if (!(*tmp16 & GMII_PHY_PHYSR_LINK)) { 430 return 0; 431 } else if (GMII_PHY_PHYSR_GIGA == (*tmp16 & GMII_PHY_PHYSR_SMASK)) { 432 mode |= AX_MEDIUM_GIGAMODE | AX_MEDIUM_EN_125MHZ | 433 AX_MEDIUM_JUMBO_EN; 434 435 if (link_sts & AX_USB_SS) 436 memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5); 437 else if (link_sts & AX_USB_HS) 438 memcpy(tmp, &AX88179_BULKIN_SIZE[1], 5); 439 else 440 memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5); 441 } else if (GMII_PHY_PHYSR_100 == (*tmp16 & GMII_PHY_PHYSR_SMASK)) { 442 mode |= AX_MEDIUM_PS; 443 444 if (link_sts & (AX_USB_SS | AX_USB_HS)) 445 memcpy(tmp, &AX88179_BULKIN_SIZE[2], 5); 446 else 447 memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5); 448 } else { 449 memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5); 450 } 451 452 /* RX bulk configuration */ 453 asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp); 454 455 dev_priv->rx_urb_size = (1024 * (tmp[3] + 2)); 456 if (*tmp16 & GMII_PHY_PHYSR_FULL) 457 mode |= AX_MEDIUM_FULL_DUPLEX; 458 asix_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 459 2, 2, &mode); 460 461 return 0; 462 out_err: 463 return -1; 464 } 465 466 static int asix_send(struct eth_device *eth, void *packet, int length) 467 { 468 struct ueth_data *dev = (struct ueth_data *)eth->priv; 469 struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv; 470 471 int err; 472 u32 packet_len, tx_hdr2; 473 int actual_len, framesize; 474 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg, 475 PKTSIZE + (2 * sizeof(packet_len))); 476 477 debug("** %s(), len %d\n", __func__, length); 478 479 packet_len = length; 480 cpu_to_le32s(&packet_len); 481 482 memcpy(msg, &packet_len, sizeof(packet_len)); 483 framesize = dev_priv->maxpacketsize; 484 tx_hdr2 = 0; 485 if (((length + 8) % framesize) == 0) 486 tx_hdr2 |= 0x80008000; /* Enable padding */ 487 488 cpu_to_le32s(&tx_hdr2); 489 490 memcpy(msg + sizeof(packet_len), &tx_hdr2, sizeof(tx_hdr2)); 491 492 memcpy(msg + sizeof(packet_len) + sizeof(tx_hdr2), 493 (void *)packet, length); 494 495 err = usb_bulk_msg(dev->pusb_dev, 496 usb_sndbulkpipe(dev->pusb_dev, dev->ep_out), 497 (void *)msg, 498 length + sizeof(packet_len) + sizeof(tx_hdr2), 499 &actual_len, 500 USB_BULK_SEND_TIMEOUT); 501 debug("Tx: len = %zu, actual = %u, err = %d\n", 502 length + sizeof(packet_len), actual_len, err); 503 504 return err; 505 } 506 507 static int asix_recv(struct eth_device *eth) 508 { 509 struct ueth_data *dev = (struct ueth_data *)eth->priv; 510 struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv; 511 512 u16 frame_pos; 513 int err; 514 int actual_len; 515 516 int pkt_cnt; 517 u32 rx_hdr; 518 u16 hdr_off; 519 u32 *pkt_hdr; 520 ALLOC_CACHE_ALIGN_BUFFER(u8, recv_buf, dev_priv->rx_urb_size); 521 522 actual_len = -1; 523 524 debug("** %s()\n", __func__); 525 526 err = usb_bulk_msg(dev->pusb_dev, 527 usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in), 528 (void *)recv_buf, 529 dev_priv->rx_urb_size, 530 &actual_len, 531 USB_BULK_RECV_TIMEOUT); 532 debug("Rx: len = %u, actual = %u, err = %d\n", dev_priv->rx_urb_size, 533 actual_len, err); 534 535 if (err != 0) { 536 debug("Rx: failed to receive\n"); 537 return -ECOMM; 538 } 539 if (actual_len > dev_priv->rx_urb_size) { 540 debug("Rx: received too many bytes %d\n", actual_len); 541 return -EMSGSIZE; 542 } 543 544 545 rx_hdr = *(u32 *)(recv_buf + actual_len - 4); 546 le32_to_cpus(&rx_hdr); 547 548 pkt_cnt = (u16)rx_hdr; 549 hdr_off = (u16)(rx_hdr >> 16); 550 pkt_hdr = (u32 *)(recv_buf + hdr_off); 551 552 553 frame_pos = 0; 554 555 while (pkt_cnt--) { 556 u16 pkt_len; 557 558 le32_to_cpus(pkt_hdr); 559 pkt_len = (*pkt_hdr >> 16) & 0x1fff; 560 561 frame_pos += 2; 562 563 net_process_received_packet(recv_buf + frame_pos, pkt_len); 564 565 pkt_hdr++; 566 frame_pos += ((pkt_len + 7) & 0xFFF8)-2; 567 568 if (pkt_cnt == 0) 569 return 0; 570 } 571 return err; 572 } 573 574 static void asix_halt(struct eth_device *eth) 575 { 576 debug("** %s()\n", __func__); 577 } 578 579 /* 580 * Asix probing functions 581 */ 582 void ax88179_eth_before_probe(void) 583 { 584 curr_eth_dev = 0; 585 } 586 587 struct asix_dongle { 588 unsigned short vendor; 589 unsigned short product; 590 int flags; 591 }; 592 593 static const struct asix_dongle asix_dongles[] = { 594 { 0x0b95, 0x1790, FLAG_TYPE_AX88179 }, 595 { 0x0b95, 0x178a, FLAG_TYPE_AX88178a }, 596 { 0x2001, 0x4a00, FLAG_TYPE_DLINK_DUB1312 }, 597 { 0x0df6, 0x0072, FLAG_TYPE_SITECOM }, 598 { 0x04e8, 0xa100, FLAG_TYPE_SAMSUNG }, 599 { 0x17ef, 0x304b, FLAG_TYPE_LENOVO }, 600 { 0x04b4, 0x3610, FLAG_TYPE_GX3 }, 601 { 0x0000, 0x0000, FLAG_NONE } /* END - Do not remove */ 602 }; 603 604 /* Probe to see if a new device is actually an asix device */ 605 int ax88179_eth_probe(struct usb_device *dev, unsigned int ifnum, 606 struct ueth_data *ss) 607 { 608 struct usb_interface *iface; 609 struct usb_interface_descriptor *iface_desc; 610 struct asix_private *dev_priv; 611 int ep_in_found = 0, ep_out_found = 0; 612 int i; 613 614 /* let's examine the device now */ 615 iface = &dev->config.if_desc[ifnum]; 616 iface_desc = &dev->config.if_desc[ifnum].desc; 617 618 for (i = 0; asix_dongles[i].vendor != 0; i++) { 619 if (dev->descriptor.idVendor == asix_dongles[i].vendor && 620 dev->descriptor.idProduct == asix_dongles[i].product) 621 /* Found a supported dongle */ 622 break; 623 } 624 625 if (asix_dongles[i].vendor == 0) 626 return 0; 627 628 memset(ss, 0, sizeof(struct ueth_data)); 629 630 /* At this point, we know we've got a live one */ 631 debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n", 632 dev->descriptor.idVendor, dev->descriptor.idProduct); 633 634 /* Initialize the ueth_data structure with some useful info */ 635 ss->ifnum = ifnum; 636 ss->pusb_dev = dev; 637 ss->subclass = iface_desc->bInterfaceSubClass; 638 ss->protocol = iface_desc->bInterfaceProtocol; 639 640 /* alloc driver private */ 641 ss->dev_priv = calloc(1, sizeof(struct asix_private)); 642 if (!ss->dev_priv) 643 return 0; 644 dev_priv = ss->dev_priv; 645 dev_priv->flags = asix_dongles[i].flags; 646 647 /* 648 * We are expecting a minimum of 3 endpoints - in, out (bulk), and 649 * int. We will ignore any others. 650 */ 651 for (i = 0; i < iface_desc->bNumEndpoints; i++) { 652 /* is it an interrupt endpoint? */ 653 if ((iface->ep_desc[i].bmAttributes & 654 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) { 655 ss->ep_int = iface->ep_desc[i].bEndpointAddress & 656 USB_ENDPOINT_NUMBER_MASK; 657 ss->irqinterval = iface->ep_desc[i].bInterval; 658 continue; 659 } 660 661 /* is it an BULK endpoint? */ 662 if (!((iface->ep_desc[i].bmAttributes & 663 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK)) 664 continue; 665 666 u8 ep_addr = iface->ep_desc[i].bEndpointAddress; 667 if ((ep_addr & USB_DIR_IN) && !ep_in_found) { 668 ss->ep_in = ep_addr & 669 USB_ENDPOINT_NUMBER_MASK; 670 ep_in_found = 1; 671 } 672 if (!(ep_addr & USB_DIR_IN) && !ep_out_found) { 673 ss->ep_out = ep_addr & 674 USB_ENDPOINT_NUMBER_MASK; 675 dev_priv->maxpacketsize = 676 dev->epmaxpacketout[AX_ENDPOINT_OUT]; 677 ep_out_found = 1; 678 } 679 } 680 debug("Endpoints In %d Out %d Int %d\n", 681 ss->ep_in, ss->ep_out, ss->ep_int); 682 683 /* Do some basic sanity checks, and bail if we find a problem */ 684 if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) || 685 !ss->ep_in || !ss->ep_out || !ss->ep_int) { 686 debug("Problems with device\n"); 687 return 0; 688 } 689 dev->privptr = (void *)ss; 690 return 1; 691 } 692 693 int ax88179_eth_get_info(struct usb_device *dev, struct ueth_data *ss, 694 struct eth_device *eth) 695 { 696 if (!eth) { 697 debug("%s: missing parameter.\n", __func__); 698 return 0; 699 } 700 sprintf(eth->name, "%s%d", ASIX_BASE_NAME, curr_eth_dev++); 701 eth->init = asix_init; 702 eth->send = asix_send; 703 eth->recv = asix_recv; 704 eth->halt = asix_halt; 705 eth->write_hwaddr = asix_write_mac; 706 eth->priv = ss; 707 708 if (asix_basic_reset(ss)) 709 return 0; 710 711 /* Get the MAC address */ 712 if (asix_read_mac(eth)) 713 return 0; 714 debug("MAC %pM\n", eth->enetaddr); 715 716 return 1; 717 } 718