1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * See file CREDITS for list of people who contributed to this 4 * project. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * MA 02111-1307 USA 20 */ 21 22 #include <common.h> 23 #include <usb.h> 24 #include <linux/mii.h> 25 #include "usb_ether.h" 26 #include <malloc.h> 27 28 29 /* ASIX AX8817X based USB 2.0 Ethernet Devices */ 30 31 #define AX_CMD_SET_SW_MII 0x06 32 #define AX_CMD_READ_MII_REG 0x07 33 #define AX_CMD_WRITE_MII_REG 0x08 34 #define AX_CMD_SET_HW_MII 0x0a 35 #define AX_CMD_READ_RX_CTL 0x0f 36 #define AX_CMD_WRITE_RX_CTL 0x10 37 #define AX_CMD_WRITE_IPG0 0x12 38 #define AX_CMD_READ_NODE_ID 0x13 39 #define AX_CMD_WRITE_NODE_ID 0x14 40 #define AX_CMD_READ_PHY_ID 0x19 41 #define AX_CMD_WRITE_MEDIUM_MODE 0x1b 42 #define AX_CMD_WRITE_GPIOS 0x1f 43 #define AX_CMD_SW_RESET 0x20 44 #define AX_CMD_SW_PHY_SELECT 0x22 45 46 #define AX_SWRESET_CLEAR 0x00 47 #define AX_SWRESET_PRTE 0x04 48 #define AX_SWRESET_PRL 0x08 49 #define AX_SWRESET_IPRL 0x20 50 #define AX_SWRESET_IPPD 0x40 51 52 #define AX88772_IPG0_DEFAULT 0x15 53 #define AX88772_IPG1_DEFAULT 0x0c 54 #define AX88772_IPG2_DEFAULT 0x12 55 56 /* AX88772 & AX88178 Medium Mode Register */ 57 #define AX_MEDIUM_PF 0x0080 58 #define AX_MEDIUM_JFE 0x0040 59 #define AX_MEDIUM_TFC 0x0020 60 #define AX_MEDIUM_RFC 0x0010 61 #define AX_MEDIUM_ENCK 0x0008 62 #define AX_MEDIUM_AC 0x0004 63 #define AX_MEDIUM_FD 0x0002 64 #define AX_MEDIUM_GM 0x0001 65 #define AX_MEDIUM_SM 0x1000 66 #define AX_MEDIUM_SBP 0x0800 67 #define AX_MEDIUM_PS 0x0200 68 #define AX_MEDIUM_RE 0x0100 69 70 #define AX88178_MEDIUM_DEFAULT \ 71 (AX_MEDIUM_PS | AX_MEDIUM_FD | AX_MEDIUM_AC | \ 72 AX_MEDIUM_RFC | AX_MEDIUM_TFC | AX_MEDIUM_JFE | \ 73 AX_MEDIUM_RE) 74 75 #define AX88772_MEDIUM_DEFAULT \ 76 (AX_MEDIUM_FD | AX_MEDIUM_RFC | \ 77 AX_MEDIUM_TFC | AX_MEDIUM_PS | \ 78 AX_MEDIUM_AC | AX_MEDIUM_RE) 79 80 /* AX88772 & AX88178 RX_CTL values */ 81 #define AX_RX_CTL_SO 0x0080 82 #define AX_RX_CTL_AB 0x0008 83 84 #define AX_DEFAULT_RX_CTL \ 85 (AX_RX_CTL_SO | AX_RX_CTL_AB) 86 87 /* GPIO 2 toggles */ 88 #define AX_GPIO_GPO2EN 0x10 /* GPIO2 Output enable */ 89 #define AX_GPIO_GPO_2 0x20 /* GPIO2 Output value */ 90 #define AX_GPIO_RSE 0x80 /* Reload serial EEPROM */ 91 92 /* local defines */ 93 #define ASIX_BASE_NAME "asx" 94 #define USB_CTRL_SET_TIMEOUT 5000 95 #define USB_CTRL_GET_TIMEOUT 5000 96 #define USB_BULK_SEND_TIMEOUT 5000 97 #define USB_BULK_RECV_TIMEOUT 5000 98 99 #define AX_RX_URB_SIZE 2048 100 #define PHY_CONNECT_TIMEOUT 5000 101 102 /* asix_flags defines */ 103 #define FLAG_NONE 0 104 #define FLAG_TYPE_AX88172 (1U << 0) 105 #define FLAG_TYPE_AX88772 (1U << 1) 106 107 /* local vars */ 108 static int curr_eth_dev; /* index for name of next device detected */ 109 110 /* driver private */ 111 struct asix_private { 112 int flags; 113 }; 114 115 /* 116 * Asix infrastructure commands 117 */ 118 static int asix_write_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index, 119 u16 size, void *data) 120 { 121 int len; 122 123 debug("asix_write_cmd() cmd=0x%02x value=0x%04x index=0x%04x " 124 "size=%d\n", cmd, value, index, size); 125 126 len = usb_control_msg( 127 dev->pusb_dev, 128 usb_sndctrlpipe(dev->pusb_dev, 0), 129 cmd, 130 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 131 value, 132 index, 133 data, 134 size, 135 USB_CTRL_SET_TIMEOUT); 136 137 return len == size ? 0 : -1; 138 } 139 140 static int asix_read_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index, 141 u16 size, void *data) 142 { 143 int len; 144 145 debug("asix_read_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n", 146 cmd, value, index, size); 147 148 len = usb_control_msg( 149 dev->pusb_dev, 150 usb_rcvctrlpipe(dev->pusb_dev, 0), 151 cmd, 152 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 153 value, 154 index, 155 data, 156 size, 157 USB_CTRL_GET_TIMEOUT); 158 return len == size ? 0 : -1; 159 } 160 161 static inline int asix_set_sw_mii(struct ueth_data *dev) 162 { 163 int ret; 164 165 ret = asix_write_cmd(dev, AX_CMD_SET_SW_MII, 0x0000, 0, 0, NULL); 166 if (ret < 0) 167 debug("Failed to enable software MII access\n"); 168 return ret; 169 } 170 171 static inline int asix_set_hw_mii(struct ueth_data *dev) 172 { 173 int ret; 174 175 ret = asix_write_cmd(dev, AX_CMD_SET_HW_MII, 0x0000, 0, 0, NULL); 176 if (ret < 0) 177 debug("Failed to enable hardware MII access\n"); 178 return ret; 179 } 180 181 static int asix_mdio_read(struct ueth_data *dev, int phy_id, int loc) 182 { 183 ALLOC_CACHE_ALIGN_BUFFER(__le16, res, 1); 184 185 asix_set_sw_mii(dev); 186 asix_read_cmd(dev, AX_CMD_READ_MII_REG, phy_id, (__u16)loc, 2, res); 187 asix_set_hw_mii(dev); 188 189 debug("asix_mdio_read() phy_id=0x%02x, loc=0x%02x, returns=0x%04x\n", 190 phy_id, loc, le16_to_cpu(*res)); 191 192 return le16_to_cpu(*res); 193 } 194 195 static void 196 asix_mdio_write(struct ueth_data *dev, int phy_id, int loc, int val) 197 { 198 ALLOC_CACHE_ALIGN_BUFFER(__le16, res, 1); 199 *res = cpu_to_le16(val); 200 201 debug("asix_mdio_write() phy_id=0x%02x, loc=0x%02x, val=0x%04x\n", 202 phy_id, loc, val); 203 asix_set_sw_mii(dev); 204 asix_write_cmd(dev, AX_CMD_WRITE_MII_REG, phy_id, (__u16)loc, 2, res); 205 asix_set_hw_mii(dev); 206 } 207 208 /* 209 * Asix "high level" commands 210 */ 211 static int asix_sw_reset(struct ueth_data *dev, u8 flags) 212 { 213 int ret; 214 215 ret = asix_write_cmd(dev, AX_CMD_SW_RESET, flags, 0, 0, NULL); 216 if (ret < 0) 217 debug("Failed to send software reset: %02x\n", ret); 218 else 219 udelay(150 * 1000); 220 221 return ret; 222 } 223 224 static inline int asix_get_phy_addr(struct ueth_data *dev) 225 { 226 ALLOC_CACHE_ALIGN_BUFFER(u8, buf, 2); 227 228 int ret = asix_read_cmd(dev, AX_CMD_READ_PHY_ID, 0, 0, 2, buf); 229 230 debug("asix_get_phy_addr()\n"); 231 232 if (ret < 0) { 233 debug("Error reading PHYID register: %02x\n", ret); 234 goto out; 235 } 236 debug("asix_get_phy_addr() returning 0x%02x%02x\n", buf[0], buf[1]); 237 ret = buf[1]; 238 239 out: 240 return ret; 241 } 242 243 static int asix_write_medium_mode(struct ueth_data *dev, u16 mode) 244 { 245 int ret; 246 247 debug("asix_write_medium_mode() - mode = 0x%04x\n", mode); 248 ret = asix_write_cmd(dev, AX_CMD_WRITE_MEDIUM_MODE, mode, 249 0, 0, NULL); 250 if (ret < 0) { 251 debug("Failed to write Medium Mode mode to 0x%04x: %02x\n", 252 mode, ret); 253 } 254 return ret; 255 } 256 257 static u16 asix_read_rx_ctl(struct ueth_data *dev) 258 { 259 ALLOC_CACHE_ALIGN_BUFFER(__le16, v, 1); 260 261 int ret = asix_read_cmd(dev, AX_CMD_READ_RX_CTL, 0, 0, 2, v); 262 263 if (ret < 0) 264 debug("Error reading RX_CTL register: %02x\n", ret); 265 else 266 ret = le16_to_cpu(*v); 267 return ret; 268 } 269 270 static int asix_write_rx_ctl(struct ueth_data *dev, u16 mode) 271 { 272 int ret; 273 274 debug("asix_write_rx_ctl() - mode = 0x%04x\n", mode); 275 ret = asix_write_cmd(dev, AX_CMD_WRITE_RX_CTL, mode, 0, 0, NULL); 276 if (ret < 0) { 277 debug("Failed to write RX_CTL mode to 0x%04x: %02x\n", 278 mode, ret); 279 } 280 return ret; 281 } 282 283 static int asix_write_gpio(struct ueth_data *dev, u16 value, int sleep) 284 { 285 int ret; 286 287 debug("asix_write_gpio() - value = 0x%04x\n", value); 288 ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS, value, 0, 0, NULL); 289 if (ret < 0) { 290 debug("Failed to write GPIO value 0x%04x: %02x\n", 291 value, ret); 292 } 293 if (sleep) 294 udelay(sleep * 1000); 295 296 return ret; 297 } 298 299 static int asix_write_hwaddr(struct eth_device *eth) 300 { 301 struct ueth_data *dev = (struct ueth_data *)eth->priv; 302 int ret; 303 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, ETH_ALEN); 304 305 memcpy(buf, eth->enetaddr, ETH_ALEN); 306 307 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN, buf); 308 if (ret < 0) 309 debug("Failed to set MAC address: %02x\n", ret); 310 311 return ret; 312 } 313 314 /* 315 * mii commands 316 */ 317 318 /* 319 * mii_nway_restart - restart NWay (autonegotiation) for this interface 320 * 321 * Returns 0 on success, negative on error. 322 */ 323 static int mii_nway_restart(struct ueth_data *dev) 324 { 325 int bmcr; 326 int r = -1; 327 328 /* if autoneg is off, it's an error */ 329 bmcr = asix_mdio_read(dev, dev->phy_id, MII_BMCR); 330 331 if (bmcr & BMCR_ANENABLE) { 332 bmcr |= BMCR_ANRESTART; 333 asix_mdio_write(dev, dev->phy_id, MII_BMCR, bmcr); 334 r = 0; 335 } 336 337 return r; 338 } 339 340 static int asix_basic_reset(struct ueth_data *dev) 341 { 342 int embd_phy; 343 u16 rx_ctl; 344 345 if (asix_write_gpio(dev, 346 AX_GPIO_RSE | AX_GPIO_GPO_2 | AX_GPIO_GPO2EN, 5) < 0) 347 return -1; 348 349 /* 0x10 is the phy id of the embedded 10/100 ethernet phy */ 350 embd_phy = ((asix_get_phy_addr(dev) & 0x1f) == 0x10 ? 1 : 0); 351 if (asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, 352 embd_phy, 0, 0, NULL) < 0) { 353 debug("Select PHY #1 failed\n"); 354 return -1; 355 } 356 357 if (asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL) < 0) 358 return -1; 359 360 if (asix_sw_reset(dev, AX_SWRESET_CLEAR) < 0) 361 return -1; 362 363 if (embd_phy) { 364 if (asix_sw_reset(dev, AX_SWRESET_IPRL) < 0) 365 return -1; 366 } else { 367 if (asix_sw_reset(dev, AX_SWRESET_PRTE) < 0) 368 return -1; 369 } 370 371 rx_ctl = asix_read_rx_ctl(dev); 372 debug("RX_CTL is 0x%04x after software reset\n", rx_ctl); 373 if (asix_write_rx_ctl(dev, 0x0000) < 0) 374 return -1; 375 376 rx_ctl = asix_read_rx_ctl(dev); 377 debug("RX_CTL is 0x%04x setting to 0x0000\n", rx_ctl); 378 379 return 0; 380 } 381 382 /* 383 * Asix callbacks 384 */ 385 static int asix_init(struct eth_device *eth, bd_t *bd) 386 { 387 struct ueth_data *dev = (struct ueth_data *)eth->priv; 388 int timeout = 0; 389 #define TIMEOUT_RESOLUTION 50 /* ms */ 390 int link_detected; 391 392 debug("** %s()\n", __func__); 393 394 /* Get the MAC address */ 395 if (asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 396 0, 0, ETH_ALEN, buf) < 0) { 397 debug("Failed to read MAC address.\n"); 398 goto out_err; 399 } 400 memcpy(eth->enetaddr, buf, ETH_ALEN); 401 debug("MAC %02x:%02x:%02x:%02x:%02x:%02x\n", 402 eth->enetaddr[0], eth->enetaddr[1], 403 eth->enetaddr[2], eth->enetaddr[3], 404 eth->enetaddr[4], eth->enetaddr[5]); 405 406 dev->phy_id = asix_get_phy_addr(dev); 407 if (dev->phy_id < 0) 408 debug("Failed to read phy id\n"); 409 410 if (asix_sw_reset(dev, AX_SWRESET_PRL) < 0) 411 goto out_err; 412 413 if (asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL) < 0) 414 goto out_err; 415 416 asix_mdio_write(dev, dev->phy_id, MII_BMCR, BMCR_RESET); 417 asix_mdio_write(dev, dev->phy_id, MII_ADVERTISE, 418 ADVERTISE_ALL | ADVERTISE_CSMA); 419 mii_nway_restart(dev); 420 421 if (asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT) < 0) 422 goto out_err; 423 424 if (asix_write_cmd(dev, AX_CMD_WRITE_IPG0, 425 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT, 426 AX88772_IPG2_DEFAULT, 0, NULL) < 0) { 427 debug("Write IPG,IPG1,IPG2 failed\n"); 428 goto out_err; 429 } 430 431 if (asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL) < 0) 432 goto out_err; 433 434 do { 435 link_detected = asix_mdio_read(dev, dev->phy_id, MII_BMSR) & 436 BMSR_LSTATUS; 437 if (!link_detected) { 438 if (timeout == 0) 439 printf("Waiting for Ethernet connection... "); 440 udelay(TIMEOUT_RESOLUTION * 1000); 441 timeout += TIMEOUT_RESOLUTION; 442 } 443 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT); 444 if (link_detected) { 445 if (timeout != 0) 446 printf("done.\n"); 447 } else { 448 printf("unable to connect.\n"); 449 goto out_err; 450 } 451 452 return 0; 453 out_err: 454 return -1; 455 } 456 457 static int asix_send(struct eth_device *eth, void *packet, int length) 458 { 459 struct ueth_data *dev = (struct ueth_data *)eth->priv; 460 int err; 461 u32 packet_len; 462 int actual_len; 463 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg, 464 PKTSIZE + sizeof(packet_len)); 465 466 debug("** %s(), len %d\n", __func__, length); 467 468 packet_len = (((length) ^ 0x0000ffff) << 16) + (length); 469 cpu_to_le32s(&packet_len); 470 471 memcpy(msg, &packet_len, sizeof(packet_len)); 472 memcpy(msg + sizeof(packet_len), (void *)packet, length); 473 if (length & 1) 474 length++; 475 476 err = usb_bulk_msg(dev->pusb_dev, 477 usb_sndbulkpipe(dev->pusb_dev, dev->ep_out), 478 (void *)msg, 479 length + sizeof(packet_len), 480 &actual_len, 481 USB_BULK_SEND_TIMEOUT); 482 debug("Tx: len = %u, actual = %u, err = %d\n", 483 length + sizeof(packet_len), actual_len, err); 484 485 return err; 486 } 487 488 static int asix_recv(struct eth_device *eth) 489 { 490 struct ueth_data *dev = (struct ueth_data *)eth->priv; 491 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, AX_RX_URB_SIZE); 492 unsigned char *buf_ptr; 493 int err; 494 int actual_len; 495 u32 packet_len; 496 497 debug("** %s()\n", __func__); 498 499 err = usb_bulk_msg(dev->pusb_dev, 500 usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in), 501 (void *)recv_buf, 502 AX_RX_URB_SIZE, 503 &actual_len, 504 USB_BULK_RECV_TIMEOUT); 505 debug("Rx: len = %u, actual = %u, err = %d\n", AX_RX_URB_SIZE, 506 actual_len, err); 507 if (err != 0) { 508 debug("Rx: failed to receive\n"); 509 return -1; 510 } 511 if (actual_len > AX_RX_URB_SIZE) { 512 debug("Rx: received too many bytes %d\n", actual_len); 513 return -1; 514 } 515 516 buf_ptr = recv_buf; 517 while (actual_len > 0) { 518 /* 519 * 1st 4 bytes contain the length of the actual data as two 520 * complementary 16-bit words. Extract the length of the data. 521 */ 522 if (actual_len < sizeof(packet_len)) { 523 debug("Rx: incomplete packet length\n"); 524 return -1; 525 } 526 memcpy(&packet_len, buf_ptr, sizeof(packet_len)); 527 le32_to_cpus(&packet_len); 528 if (((packet_len >> 16) ^ 0xffff) != (packet_len & 0xffff)) { 529 debug("Rx: malformed packet length: %#x (%#x:%#x)\n", 530 packet_len, (packet_len >> 16) ^ 0xffff, 531 packet_len & 0xffff); 532 return -1; 533 } 534 packet_len = packet_len & 0xffff; 535 if (packet_len > actual_len - sizeof(packet_len)) { 536 debug("Rx: too large packet: %d\n", packet_len); 537 return -1; 538 } 539 540 /* Notify net stack */ 541 NetReceive(buf_ptr + sizeof(packet_len), packet_len); 542 543 /* Adjust for next iteration. Packets are padded to 16-bits */ 544 if (packet_len & 1) 545 packet_len++; 546 actual_len -= sizeof(packet_len) + packet_len; 547 buf_ptr += sizeof(packet_len) + packet_len; 548 } 549 550 return err; 551 } 552 553 static void asix_halt(struct eth_device *eth) 554 { 555 debug("** %s()\n", __func__); 556 } 557 558 /* 559 * Asix probing functions 560 */ 561 void asix_eth_before_probe(void) 562 { 563 curr_eth_dev = 0; 564 } 565 566 struct asix_dongle { 567 unsigned short vendor; 568 unsigned short product; 569 int flags; 570 }; 571 572 static const struct asix_dongle const asix_dongles[] = { 573 { 0x05ac, 0x1402, FLAG_TYPE_AX88772 }, /* Apple USB Ethernet Adapter */ 574 { 0x07d1, 0x3c05, FLAG_TYPE_AX88772 }, /* D-Link DUB-E100 H/W Ver B1 */ 575 /* Cables-to-Go USB Ethernet Adapter */ 576 { 0x0b95, 0x772a, FLAG_TYPE_AX88772 }, 577 { 0x0b95, 0x7720, FLAG_TYPE_AX88772 }, /* Trendnet TU2-ET100 V3.0R */ 578 { 0x0b95, 0x1720, FLAG_TYPE_AX88172 }, /* SMC */ 579 { 0x0db0, 0xa877, FLAG_TYPE_AX88772 }, /* MSI - ASIX 88772a */ 580 { 0x13b1, 0x0018, FLAG_TYPE_AX88172 }, /* Linksys 200M v2.1 */ 581 { 0x1557, 0x7720, FLAG_TYPE_AX88772 }, /* 0Q0 cable ethernet */ 582 /* DLink DUB-E100 H/W Ver B1 Alternate */ 583 { 0x2001, 0x3c05, FLAG_TYPE_AX88772 }, 584 { 0x0000, 0x0000, FLAG_NONE } /* END - Do not remove */ 585 }; 586 587 /* Probe to see if a new device is actually an asix device */ 588 int asix_eth_probe(struct usb_device *dev, unsigned int ifnum, 589 struct ueth_data *ss) 590 { 591 struct usb_interface *iface; 592 struct usb_interface_descriptor *iface_desc; 593 int i; 594 595 /* let's examine the device now */ 596 iface = &dev->config.if_desc[ifnum]; 597 iface_desc = &dev->config.if_desc[ifnum].desc; 598 599 for (i = 0; asix_dongles[i].vendor != 0; i++) { 600 if (dev->descriptor.idVendor == asix_dongles[i].vendor && 601 dev->descriptor.idProduct == asix_dongles[i].product) 602 /* Found a supported dongle */ 603 break; 604 } 605 606 if (asix_dongles[i].vendor == 0) 607 return 0; 608 609 memset(ss, 0, sizeof(struct ueth_data)); 610 611 /* At this point, we know we've got a live one */ 612 debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n", 613 dev->descriptor.idVendor, dev->descriptor.idProduct); 614 615 /* Initialize the ueth_data structure with some useful info */ 616 ss->ifnum = ifnum; 617 ss->pusb_dev = dev; 618 ss->subclass = iface_desc->bInterfaceSubClass; 619 ss->protocol = iface_desc->bInterfaceProtocol; 620 621 /* alloc driver private */ 622 ss->dev_priv = calloc(1, sizeof(struct asix_private)); 623 if (!ss->dev_priv) 624 return 0; 625 626 ((struct asix_private *)ss->dev_priv)->flags = asix_dongles[i].flags; 627 628 /* 629 * We are expecting a minimum of 3 endpoints - in, out (bulk), and 630 * int. We will ignore any others. 631 */ 632 for (i = 0; i < iface_desc->bNumEndpoints; i++) { 633 /* is it an BULK endpoint? */ 634 if ((iface->ep_desc[i].bmAttributes & 635 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) { 636 if (iface->ep_desc[i].bEndpointAddress & USB_DIR_IN) 637 ss->ep_in = iface->ep_desc[i].bEndpointAddress & 638 USB_ENDPOINT_NUMBER_MASK; 639 else 640 ss->ep_out = 641 iface->ep_desc[i].bEndpointAddress & 642 USB_ENDPOINT_NUMBER_MASK; 643 } 644 645 /* is it an interrupt endpoint? */ 646 if ((iface->ep_desc[i].bmAttributes & 647 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) { 648 ss->ep_int = iface->ep_desc[i].bEndpointAddress & 649 USB_ENDPOINT_NUMBER_MASK; 650 ss->irqinterval = iface->ep_desc[i].bInterval; 651 } 652 } 653 debug("Endpoints In %d Out %d Int %d\n", 654 ss->ep_in, ss->ep_out, ss->ep_int); 655 656 /* Do some basic sanity checks, and bail if we find a problem */ 657 if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) || 658 !ss->ep_in || !ss->ep_out || !ss->ep_int) { 659 debug("Problems with device\n"); 660 return 0; 661 } 662 dev->privptr = (void *)ss; 663 return 1; 664 } 665 666 int asix_eth_get_info(struct usb_device *dev, struct ueth_data *ss, 667 struct eth_device *eth) 668 { 669 struct asix_private *priv = (struct asix_private *)ss->dev_priv; 670 671 if (!eth) { 672 debug("%s: missing parameter.\n", __func__); 673 return 0; 674 } 675 sprintf(eth->name, "%s%d", ASIX_BASE_NAME, curr_eth_dev++); 676 eth->init = asix_init; 677 eth->send = asix_send; 678 eth->recv = asix_recv; 679 eth->halt = asix_halt; 680 if (!(priv->flags & FLAG_TYPE_AX88172)) 681 eth->write_hwaddr = asix_write_hwaddr; 682 eth->priv = ss; 683 684 if (asix_basic_reset(ss)) 685 return 0; 686 687 return 1; 688 } 689