1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * See file CREDITS for list of people who contributed to this 4 * project. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * MA 02111-1307 USA 20 */ 21 22 #include <common.h> 23 #include <usb.h> 24 #include <linux/mii.h> 25 #include "usb_ether.h" 26 #include <malloc.h> 27 28 29 /* ASIX AX8817X based USB 2.0 Ethernet Devices */ 30 31 #define AX_CMD_SET_SW_MII 0x06 32 #define AX_CMD_READ_MII_REG 0x07 33 #define AX_CMD_WRITE_MII_REG 0x08 34 #define AX_CMD_SET_HW_MII 0x0a 35 #define AX_CMD_READ_EEPROM 0x0b 36 #define AX_CMD_READ_RX_CTL 0x0f 37 #define AX_CMD_WRITE_RX_CTL 0x10 38 #define AX_CMD_WRITE_IPG0 0x12 39 #define AX_CMD_READ_NODE_ID 0x13 40 #define AX_CMD_WRITE_NODE_ID 0x14 41 #define AX_CMD_READ_PHY_ID 0x19 42 #define AX_CMD_WRITE_MEDIUM_MODE 0x1b 43 #define AX_CMD_WRITE_GPIOS 0x1f 44 #define AX_CMD_SW_RESET 0x20 45 #define AX_CMD_SW_PHY_SELECT 0x22 46 47 #define AX_SWRESET_CLEAR 0x00 48 #define AX_SWRESET_PRTE 0x04 49 #define AX_SWRESET_PRL 0x08 50 #define AX_SWRESET_IPRL 0x20 51 #define AX_SWRESET_IPPD 0x40 52 53 #define AX88772_IPG0_DEFAULT 0x15 54 #define AX88772_IPG1_DEFAULT 0x0c 55 #define AX88772_IPG2_DEFAULT 0x12 56 57 /* AX88772 & AX88178 Medium Mode Register */ 58 #define AX_MEDIUM_PF 0x0080 59 #define AX_MEDIUM_JFE 0x0040 60 #define AX_MEDIUM_TFC 0x0020 61 #define AX_MEDIUM_RFC 0x0010 62 #define AX_MEDIUM_ENCK 0x0008 63 #define AX_MEDIUM_AC 0x0004 64 #define AX_MEDIUM_FD 0x0002 65 #define AX_MEDIUM_GM 0x0001 66 #define AX_MEDIUM_SM 0x1000 67 #define AX_MEDIUM_SBP 0x0800 68 #define AX_MEDIUM_PS 0x0200 69 #define AX_MEDIUM_RE 0x0100 70 71 #define AX88178_MEDIUM_DEFAULT \ 72 (AX_MEDIUM_PS | AX_MEDIUM_FD | AX_MEDIUM_AC | \ 73 AX_MEDIUM_RFC | AX_MEDIUM_TFC | AX_MEDIUM_JFE | \ 74 AX_MEDIUM_RE) 75 76 #define AX88772_MEDIUM_DEFAULT \ 77 (AX_MEDIUM_FD | AX_MEDIUM_RFC | \ 78 AX_MEDIUM_TFC | AX_MEDIUM_PS | \ 79 AX_MEDIUM_AC | AX_MEDIUM_RE) 80 81 /* AX88772 & AX88178 RX_CTL values */ 82 #define AX_RX_CTL_SO 0x0080 83 #define AX_RX_CTL_AB 0x0008 84 85 #define AX_DEFAULT_RX_CTL \ 86 (AX_RX_CTL_SO | AX_RX_CTL_AB) 87 88 /* GPIO 2 toggles */ 89 #define AX_GPIO_GPO2EN 0x10 /* GPIO2 Output enable */ 90 #define AX_GPIO_GPO_2 0x20 /* GPIO2 Output value */ 91 #define AX_GPIO_RSE 0x80 /* Reload serial EEPROM */ 92 93 /* local defines */ 94 #define ASIX_BASE_NAME "asx" 95 #define USB_CTRL_SET_TIMEOUT 5000 96 #define USB_CTRL_GET_TIMEOUT 5000 97 #define USB_BULK_SEND_TIMEOUT 5000 98 #define USB_BULK_RECV_TIMEOUT 5000 99 100 #define AX_RX_URB_SIZE 2048 101 #define PHY_CONNECT_TIMEOUT 5000 102 103 /* asix_flags defines */ 104 #define FLAG_NONE 0 105 #define FLAG_TYPE_AX88172 (1U << 0) 106 #define FLAG_TYPE_AX88772 (1U << 1) 107 #define FLAG_EEPROM_MAC (1U << 2) /* initial mac address in eeprom */ 108 109 /* local vars */ 110 static int curr_eth_dev; /* index for name of next device detected */ 111 112 /* driver private */ 113 struct asix_private { 114 int flags; 115 }; 116 117 /* 118 * Asix infrastructure commands 119 */ 120 static int asix_write_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index, 121 u16 size, void *data) 122 { 123 int len; 124 125 debug("asix_write_cmd() cmd=0x%02x value=0x%04x index=0x%04x " 126 "size=%d\n", cmd, value, index, size); 127 128 len = usb_control_msg( 129 dev->pusb_dev, 130 usb_sndctrlpipe(dev->pusb_dev, 0), 131 cmd, 132 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 133 value, 134 index, 135 data, 136 size, 137 USB_CTRL_SET_TIMEOUT); 138 139 return len == size ? 0 : -1; 140 } 141 142 static int asix_read_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index, 143 u16 size, void *data) 144 { 145 int len; 146 147 debug("asix_read_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n", 148 cmd, value, index, size); 149 150 len = usb_control_msg( 151 dev->pusb_dev, 152 usb_rcvctrlpipe(dev->pusb_dev, 0), 153 cmd, 154 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 155 value, 156 index, 157 data, 158 size, 159 USB_CTRL_GET_TIMEOUT); 160 return len == size ? 0 : -1; 161 } 162 163 static inline int asix_set_sw_mii(struct ueth_data *dev) 164 { 165 int ret; 166 167 ret = asix_write_cmd(dev, AX_CMD_SET_SW_MII, 0x0000, 0, 0, NULL); 168 if (ret < 0) 169 debug("Failed to enable software MII access\n"); 170 return ret; 171 } 172 173 static inline int asix_set_hw_mii(struct ueth_data *dev) 174 { 175 int ret; 176 177 ret = asix_write_cmd(dev, AX_CMD_SET_HW_MII, 0x0000, 0, 0, NULL); 178 if (ret < 0) 179 debug("Failed to enable hardware MII access\n"); 180 return ret; 181 } 182 183 static int asix_mdio_read(struct ueth_data *dev, int phy_id, int loc) 184 { 185 ALLOC_CACHE_ALIGN_BUFFER(__le16, res, 1); 186 187 asix_set_sw_mii(dev); 188 asix_read_cmd(dev, AX_CMD_READ_MII_REG, phy_id, (__u16)loc, 2, res); 189 asix_set_hw_mii(dev); 190 191 debug("asix_mdio_read() phy_id=0x%02x, loc=0x%02x, returns=0x%04x\n", 192 phy_id, loc, le16_to_cpu(*res)); 193 194 return le16_to_cpu(*res); 195 } 196 197 static void 198 asix_mdio_write(struct ueth_data *dev, int phy_id, int loc, int val) 199 { 200 ALLOC_CACHE_ALIGN_BUFFER(__le16, res, 1); 201 *res = cpu_to_le16(val); 202 203 debug("asix_mdio_write() phy_id=0x%02x, loc=0x%02x, val=0x%04x\n", 204 phy_id, loc, val); 205 asix_set_sw_mii(dev); 206 asix_write_cmd(dev, AX_CMD_WRITE_MII_REG, phy_id, (__u16)loc, 2, res); 207 asix_set_hw_mii(dev); 208 } 209 210 /* 211 * Asix "high level" commands 212 */ 213 static int asix_sw_reset(struct ueth_data *dev, u8 flags) 214 { 215 int ret; 216 217 ret = asix_write_cmd(dev, AX_CMD_SW_RESET, flags, 0, 0, NULL); 218 if (ret < 0) 219 debug("Failed to send software reset: %02x\n", ret); 220 else 221 udelay(150 * 1000); 222 223 return ret; 224 } 225 226 static inline int asix_get_phy_addr(struct ueth_data *dev) 227 { 228 ALLOC_CACHE_ALIGN_BUFFER(u8, buf, 2); 229 230 int ret = asix_read_cmd(dev, AX_CMD_READ_PHY_ID, 0, 0, 2, buf); 231 232 debug("asix_get_phy_addr()\n"); 233 234 if (ret < 0) { 235 debug("Error reading PHYID register: %02x\n", ret); 236 goto out; 237 } 238 debug("asix_get_phy_addr() returning 0x%02x%02x\n", buf[0], buf[1]); 239 ret = buf[1]; 240 241 out: 242 return ret; 243 } 244 245 static int asix_write_medium_mode(struct ueth_data *dev, u16 mode) 246 { 247 int ret; 248 249 debug("asix_write_medium_mode() - mode = 0x%04x\n", mode); 250 ret = asix_write_cmd(dev, AX_CMD_WRITE_MEDIUM_MODE, mode, 251 0, 0, NULL); 252 if (ret < 0) { 253 debug("Failed to write Medium Mode mode to 0x%04x: %02x\n", 254 mode, ret); 255 } 256 return ret; 257 } 258 259 static u16 asix_read_rx_ctl(struct ueth_data *dev) 260 { 261 ALLOC_CACHE_ALIGN_BUFFER(__le16, v, 1); 262 263 int ret = asix_read_cmd(dev, AX_CMD_READ_RX_CTL, 0, 0, 2, v); 264 265 if (ret < 0) 266 debug("Error reading RX_CTL register: %02x\n", ret); 267 else 268 ret = le16_to_cpu(*v); 269 return ret; 270 } 271 272 static int asix_write_rx_ctl(struct ueth_data *dev, u16 mode) 273 { 274 int ret; 275 276 debug("asix_write_rx_ctl() - mode = 0x%04x\n", mode); 277 ret = asix_write_cmd(dev, AX_CMD_WRITE_RX_CTL, mode, 0, 0, NULL); 278 if (ret < 0) { 279 debug("Failed to write RX_CTL mode to 0x%04x: %02x\n", 280 mode, ret); 281 } 282 return ret; 283 } 284 285 static int asix_write_gpio(struct ueth_data *dev, u16 value, int sleep) 286 { 287 int ret; 288 289 debug("asix_write_gpio() - value = 0x%04x\n", value); 290 ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS, value, 0, 0, NULL); 291 if (ret < 0) { 292 debug("Failed to write GPIO value 0x%04x: %02x\n", 293 value, ret); 294 } 295 if (sleep) 296 udelay(sleep * 1000); 297 298 return ret; 299 } 300 301 static int asix_write_hwaddr(struct eth_device *eth) 302 { 303 struct ueth_data *dev = (struct ueth_data *)eth->priv; 304 int ret; 305 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, ETH_ALEN); 306 307 memcpy(buf, eth->enetaddr, ETH_ALEN); 308 309 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN, buf); 310 if (ret < 0) 311 debug("Failed to set MAC address: %02x\n", ret); 312 313 return ret; 314 } 315 316 /* 317 * mii commands 318 */ 319 320 /* 321 * mii_nway_restart - restart NWay (autonegotiation) for this interface 322 * 323 * Returns 0 on success, negative on error. 324 */ 325 static int mii_nway_restart(struct ueth_data *dev) 326 { 327 int bmcr; 328 int r = -1; 329 330 /* if autoneg is off, it's an error */ 331 bmcr = asix_mdio_read(dev, dev->phy_id, MII_BMCR); 332 333 if (bmcr & BMCR_ANENABLE) { 334 bmcr |= BMCR_ANRESTART; 335 asix_mdio_write(dev, dev->phy_id, MII_BMCR, bmcr); 336 r = 0; 337 } 338 339 return r; 340 } 341 342 static int asix_read_mac(struct eth_device *eth) 343 { 344 struct ueth_data *dev = (struct ueth_data *)eth->priv; 345 struct asix_private *priv = (struct asix_private *)dev->dev_priv; 346 int i; 347 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, ETH_ALEN); 348 349 if (priv->flags & FLAG_EEPROM_MAC) { 350 for (i = 0; i < (ETH_ALEN >> 1); i++) { 351 if (asix_read_cmd(dev, AX_CMD_READ_EEPROM, 352 0x04 + i, 0, 2, buf) < 0) { 353 debug("Failed to read SROM address 04h.\n"); 354 return -1; 355 } 356 memcpy((eth->enetaddr + i * 2), buf, 2); 357 } 358 } else { 359 if (asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf) 360 < 0) { 361 debug("Failed to read MAC address.\n"); 362 return -1; 363 } 364 memcpy(eth->enetaddr, buf, ETH_ALEN); 365 } 366 367 return 0; 368 } 369 370 static int asix_basic_reset(struct ueth_data *dev) 371 { 372 int embd_phy; 373 u16 rx_ctl; 374 375 if (asix_write_gpio(dev, 376 AX_GPIO_RSE | AX_GPIO_GPO_2 | AX_GPIO_GPO2EN, 5) < 0) 377 return -1; 378 379 /* 0x10 is the phy id of the embedded 10/100 ethernet phy */ 380 embd_phy = ((asix_get_phy_addr(dev) & 0x1f) == 0x10 ? 1 : 0); 381 if (asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, 382 embd_phy, 0, 0, NULL) < 0) { 383 debug("Select PHY #1 failed\n"); 384 return -1; 385 } 386 387 if (asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL) < 0) 388 return -1; 389 390 if (asix_sw_reset(dev, AX_SWRESET_CLEAR) < 0) 391 return -1; 392 393 if (embd_phy) { 394 if (asix_sw_reset(dev, AX_SWRESET_IPRL) < 0) 395 return -1; 396 } else { 397 if (asix_sw_reset(dev, AX_SWRESET_PRTE) < 0) 398 return -1; 399 } 400 401 rx_ctl = asix_read_rx_ctl(dev); 402 debug("RX_CTL is 0x%04x after software reset\n", rx_ctl); 403 if (asix_write_rx_ctl(dev, 0x0000) < 0) 404 return -1; 405 406 rx_ctl = asix_read_rx_ctl(dev); 407 debug("RX_CTL is 0x%04x setting to 0x0000\n", rx_ctl); 408 409 return 0; 410 } 411 412 /* 413 * Asix callbacks 414 */ 415 static int asix_init(struct eth_device *eth, bd_t *bd) 416 { 417 struct ueth_data *dev = (struct ueth_data *)eth->priv; 418 int timeout = 0; 419 #define TIMEOUT_RESOLUTION 50 /* ms */ 420 int link_detected; 421 422 debug("** %s()\n", __func__); 423 424 dev->phy_id = asix_get_phy_addr(dev); 425 if (dev->phy_id < 0) 426 debug("Failed to read phy id\n"); 427 428 if (asix_sw_reset(dev, AX_SWRESET_PRL) < 0) 429 goto out_err; 430 431 if (asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL) < 0) 432 goto out_err; 433 434 asix_mdio_write(dev, dev->phy_id, MII_BMCR, BMCR_RESET); 435 asix_mdio_write(dev, dev->phy_id, MII_ADVERTISE, 436 ADVERTISE_ALL | ADVERTISE_CSMA); 437 mii_nway_restart(dev); 438 439 if (asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT) < 0) 440 goto out_err; 441 442 if (asix_write_cmd(dev, AX_CMD_WRITE_IPG0, 443 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT, 444 AX88772_IPG2_DEFAULT, 0, NULL) < 0) { 445 debug("Write IPG,IPG1,IPG2 failed\n"); 446 goto out_err; 447 } 448 449 if (asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL) < 0) 450 goto out_err; 451 452 do { 453 link_detected = asix_mdio_read(dev, dev->phy_id, MII_BMSR) & 454 BMSR_LSTATUS; 455 if (!link_detected) { 456 if (timeout == 0) 457 printf("Waiting for Ethernet connection... "); 458 udelay(TIMEOUT_RESOLUTION * 1000); 459 timeout += TIMEOUT_RESOLUTION; 460 } 461 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT); 462 if (link_detected) { 463 if (timeout != 0) 464 printf("done.\n"); 465 } else { 466 printf("unable to connect.\n"); 467 goto out_err; 468 } 469 470 return 0; 471 out_err: 472 return -1; 473 } 474 475 static int asix_send(struct eth_device *eth, void *packet, int length) 476 { 477 struct ueth_data *dev = (struct ueth_data *)eth->priv; 478 int err; 479 u32 packet_len; 480 int actual_len; 481 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg, 482 PKTSIZE + sizeof(packet_len)); 483 484 debug("** %s(), len %d\n", __func__, length); 485 486 packet_len = (((length) ^ 0x0000ffff) << 16) + (length); 487 cpu_to_le32s(&packet_len); 488 489 memcpy(msg, &packet_len, sizeof(packet_len)); 490 memcpy(msg + sizeof(packet_len), (void *)packet, length); 491 if (length & 1) 492 length++; 493 494 err = usb_bulk_msg(dev->pusb_dev, 495 usb_sndbulkpipe(dev->pusb_dev, dev->ep_out), 496 (void *)msg, 497 length + sizeof(packet_len), 498 &actual_len, 499 USB_BULK_SEND_TIMEOUT); 500 debug("Tx: len = %u, actual = %u, err = %d\n", 501 length + sizeof(packet_len), actual_len, err); 502 503 return err; 504 } 505 506 static int asix_recv(struct eth_device *eth) 507 { 508 struct ueth_data *dev = (struct ueth_data *)eth->priv; 509 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, AX_RX_URB_SIZE); 510 unsigned char *buf_ptr; 511 int err; 512 int actual_len; 513 u32 packet_len; 514 515 debug("** %s()\n", __func__); 516 517 err = usb_bulk_msg(dev->pusb_dev, 518 usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in), 519 (void *)recv_buf, 520 AX_RX_URB_SIZE, 521 &actual_len, 522 USB_BULK_RECV_TIMEOUT); 523 debug("Rx: len = %u, actual = %u, err = %d\n", AX_RX_URB_SIZE, 524 actual_len, err); 525 if (err != 0) { 526 debug("Rx: failed to receive\n"); 527 return -1; 528 } 529 if (actual_len > AX_RX_URB_SIZE) { 530 debug("Rx: received too many bytes %d\n", actual_len); 531 return -1; 532 } 533 534 buf_ptr = recv_buf; 535 while (actual_len > 0) { 536 /* 537 * 1st 4 bytes contain the length of the actual data as two 538 * complementary 16-bit words. Extract the length of the data. 539 */ 540 if (actual_len < sizeof(packet_len)) { 541 debug("Rx: incomplete packet length\n"); 542 return -1; 543 } 544 memcpy(&packet_len, buf_ptr, sizeof(packet_len)); 545 le32_to_cpus(&packet_len); 546 if (((packet_len >> 16) ^ 0xffff) != (packet_len & 0xffff)) { 547 debug("Rx: malformed packet length: %#x (%#x:%#x)\n", 548 packet_len, (packet_len >> 16) ^ 0xffff, 549 packet_len & 0xffff); 550 return -1; 551 } 552 packet_len = packet_len & 0xffff; 553 if (packet_len > actual_len - sizeof(packet_len)) { 554 debug("Rx: too large packet: %d\n", packet_len); 555 return -1; 556 } 557 558 /* Notify net stack */ 559 NetReceive(buf_ptr + sizeof(packet_len), packet_len); 560 561 /* Adjust for next iteration. Packets are padded to 16-bits */ 562 if (packet_len & 1) 563 packet_len++; 564 actual_len -= sizeof(packet_len) + packet_len; 565 buf_ptr += sizeof(packet_len) + packet_len; 566 } 567 568 return err; 569 } 570 571 static void asix_halt(struct eth_device *eth) 572 { 573 debug("** %s()\n", __func__); 574 } 575 576 /* 577 * Asix probing functions 578 */ 579 void asix_eth_before_probe(void) 580 { 581 curr_eth_dev = 0; 582 } 583 584 struct asix_dongle { 585 unsigned short vendor; 586 unsigned short product; 587 int flags; 588 }; 589 590 static const struct asix_dongle const asix_dongles[] = { 591 { 0x05ac, 0x1402, FLAG_TYPE_AX88772 }, /* Apple USB Ethernet Adapter */ 592 { 0x07d1, 0x3c05, FLAG_TYPE_AX88772 }, /* D-Link DUB-E100 H/W Ver B1 */ 593 /* Cables-to-Go USB Ethernet Adapter */ 594 { 0x0b95, 0x772a, FLAG_TYPE_AX88772 }, 595 { 0x0b95, 0x7720, FLAG_TYPE_AX88772 }, /* Trendnet TU2-ET100 V3.0R */ 596 { 0x0b95, 0x1720, FLAG_TYPE_AX88172 }, /* SMC */ 597 { 0x0db0, 0xa877, FLAG_TYPE_AX88772 }, /* MSI - ASIX 88772a */ 598 { 0x13b1, 0x0018, FLAG_TYPE_AX88172 }, /* Linksys 200M v2.1 */ 599 { 0x1557, 0x7720, FLAG_TYPE_AX88772 }, /* 0Q0 cable ethernet */ 600 /* DLink DUB-E100 H/W Ver B1 Alternate */ 601 { 0x2001, 0x3c05, FLAG_TYPE_AX88772 }, 602 { 0x0000, 0x0000, FLAG_NONE } /* END - Do not remove */ 603 }; 604 605 /* Probe to see if a new device is actually an asix device */ 606 int asix_eth_probe(struct usb_device *dev, unsigned int ifnum, 607 struct ueth_data *ss) 608 { 609 struct usb_interface *iface; 610 struct usb_interface_descriptor *iface_desc; 611 int i; 612 613 /* let's examine the device now */ 614 iface = &dev->config.if_desc[ifnum]; 615 iface_desc = &dev->config.if_desc[ifnum].desc; 616 617 for (i = 0; asix_dongles[i].vendor != 0; i++) { 618 if (dev->descriptor.idVendor == asix_dongles[i].vendor && 619 dev->descriptor.idProduct == asix_dongles[i].product) 620 /* Found a supported dongle */ 621 break; 622 } 623 624 if (asix_dongles[i].vendor == 0) 625 return 0; 626 627 memset(ss, 0, sizeof(struct ueth_data)); 628 629 /* At this point, we know we've got a live one */ 630 debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n", 631 dev->descriptor.idVendor, dev->descriptor.idProduct); 632 633 /* Initialize the ueth_data structure with some useful info */ 634 ss->ifnum = ifnum; 635 ss->pusb_dev = dev; 636 ss->subclass = iface_desc->bInterfaceSubClass; 637 ss->protocol = iface_desc->bInterfaceProtocol; 638 639 /* alloc driver private */ 640 ss->dev_priv = calloc(1, sizeof(struct asix_private)); 641 if (!ss->dev_priv) 642 return 0; 643 644 ((struct asix_private *)ss->dev_priv)->flags = asix_dongles[i].flags; 645 646 /* 647 * We are expecting a minimum of 3 endpoints - in, out (bulk), and 648 * int. We will ignore any others. 649 */ 650 for (i = 0; i < iface_desc->bNumEndpoints; i++) { 651 /* is it an BULK endpoint? */ 652 if ((iface->ep_desc[i].bmAttributes & 653 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) { 654 if (iface->ep_desc[i].bEndpointAddress & USB_DIR_IN) 655 ss->ep_in = iface->ep_desc[i].bEndpointAddress & 656 USB_ENDPOINT_NUMBER_MASK; 657 else 658 ss->ep_out = 659 iface->ep_desc[i].bEndpointAddress & 660 USB_ENDPOINT_NUMBER_MASK; 661 } 662 663 /* is it an interrupt endpoint? */ 664 if ((iface->ep_desc[i].bmAttributes & 665 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) { 666 ss->ep_int = iface->ep_desc[i].bEndpointAddress & 667 USB_ENDPOINT_NUMBER_MASK; 668 ss->irqinterval = iface->ep_desc[i].bInterval; 669 } 670 } 671 debug("Endpoints In %d Out %d Int %d\n", 672 ss->ep_in, ss->ep_out, ss->ep_int); 673 674 /* Do some basic sanity checks, and bail if we find a problem */ 675 if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) || 676 !ss->ep_in || !ss->ep_out || !ss->ep_int) { 677 debug("Problems with device\n"); 678 return 0; 679 } 680 dev->privptr = (void *)ss; 681 return 1; 682 } 683 684 int asix_eth_get_info(struct usb_device *dev, struct ueth_data *ss, 685 struct eth_device *eth) 686 { 687 struct asix_private *priv = (struct asix_private *)ss->dev_priv; 688 689 if (!eth) { 690 debug("%s: missing parameter.\n", __func__); 691 return 0; 692 } 693 sprintf(eth->name, "%s%d", ASIX_BASE_NAME, curr_eth_dev++); 694 eth->init = asix_init; 695 eth->send = asix_send; 696 eth->recv = asix_recv; 697 eth->halt = asix_halt; 698 if (!(priv->flags & FLAG_TYPE_AX88172)) 699 eth->write_hwaddr = asix_write_hwaddr; 700 eth->priv = ss; 701 702 if (asix_basic_reset(ss)) 703 return 0; 704 705 /* Get the MAC address */ 706 if (asix_read_mac(eth)) 707 return 0; 708 debug("MAC %pM\n", eth->enetaddr); 709 710 return 1; 711 } 712