1 /** 2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling 3 * 4 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/ep0.c) and ported 10 * to uboot. 11 * 12 * commit c00552ebaf : Merge 3.18-rc7 into usb-next 13 * 14 * SPDX-License-Identifier: GPL-2.0 15 */ 16 17 #include <linux/kernel.h> 18 #include <linux/list.h> 19 20 #include <linux/usb/ch9.h> 21 #include <linux/usb/gadget.h> 22 #include <linux/usb/composite.h> 23 24 #include "core.h" 25 #include "gadget.h" 26 #include "io.h" 27 28 #include "linux-compat.h" 29 30 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep); 31 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, 32 struct dwc3_ep *dep, struct dwc3_request *req); 33 34 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state) 35 { 36 switch (state) { 37 case EP0_UNCONNECTED: 38 return "Unconnected"; 39 case EP0_SETUP_PHASE: 40 return "Setup Phase"; 41 case EP0_DATA_PHASE: 42 return "Data Phase"; 43 case EP0_STATUS_PHASE: 44 return "Status Phase"; 45 default: 46 return "UNKNOWN"; 47 } 48 } 49 50 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma, 51 u32 len, u32 type) 52 { 53 struct dwc3_gadget_ep_cmd_params params; 54 struct dwc3_trb *trb; 55 struct dwc3_ep *dep; 56 57 int ret; 58 59 dep = dwc->eps[epnum]; 60 if (dep->flags & DWC3_EP_BUSY) { 61 dev_vdbg(dwc->dev, "%s still busy", dep->name); 62 return 0; 63 } 64 65 trb = dwc->ep0_trb; 66 67 trb->bpl = lower_32_bits(buf_dma); 68 trb->bph = upper_32_bits(buf_dma); 69 trb->size = len; 70 trb->ctrl = type; 71 72 trb->ctrl |= (DWC3_TRB_CTRL_HWO 73 | DWC3_TRB_CTRL_LST 74 | DWC3_TRB_CTRL_IOC 75 | DWC3_TRB_CTRL_ISP_IMI); 76 77 memset(¶ms, 0, sizeof(params)); 78 params.param0 = upper_32_bits(dwc->ep0_trb_addr); 79 params.param1 = lower_32_bits(dwc->ep0_trb_addr); 80 81 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 82 DWC3_DEPCMD_STARTTRANSFER, ¶ms); 83 if (ret < 0) { 84 dev_dbg(dwc->dev, "%s STARTTRANSFER failed", dep->name); 85 return ret; 86 } 87 88 dep->flags |= DWC3_EP_BUSY; 89 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc, 90 dep->number); 91 92 dwc->ep0_next_event = DWC3_EP0_COMPLETE; 93 94 return 0; 95 } 96 97 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep, 98 struct dwc3_request *req) 99 { 100 struct dwc3 *dwc = dep->dwc; 101 102 req->request.actual = 0; 103 req->request.status = -EINPROGRESS; 104 req->epnum = dep->number; 105 106 list_add_tail(&req->list, &dep->request_list); 107 108 /* 109 * Gadget driver might not be quick enough to queue a request 110 * before we get a Transfer Not Ready event on this endpoint. 111 * 112 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that 113 * flag is set, it's telling us that as soon as Gadget queues the 114 * required request, we should kick the transfer here because the 115 * IRQ we were waiting for is long gone. 116 */ 117 if (dep->flags & DWC3_EP_PENDING_REQUEST) { 118 unsigned direction; 119 120 direction = !!(dep->flags & DWC3_EP0_DIR_IN); 121 122 if (dwc->ep0state != EP0_DATA_PHASE) { 123 dev_WARN(dwc->dev, "Unexpected pending request\n"); 124 return 0; 125 } 126 127 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req); 128 129 dep->flags &= ~(DWC3_EP_PENDING_REQUEST | 130 DWC3_EP0_DIR_IN); 131 132 return 0; 133 } 134 135 /* 136 * In case gadget driver asked us to delay the STATUS phase, 137 * handle it here. 138 */ 139 if (dwc->delayed_status) { 140 unsigned direction; 141 142 direction = !dwc->ep0_expect_in; 143 dwc->delayed_status = false; 144 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED); 145 146 if (dwc->ep0state == EP0_STATUS_PHASE) 147 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]); 148 else 149 dev_dbg(dwc->dev, "too early for delayed status"); 150 151 return 0; 152 } 153 154 /* 155 * Unfortunately we have uncovered a limitation wrt the Data Phase. 156 * 157 * Section 9.4 says we can wait for the XferNotReady(DATA) event to 158 * come before issueing Start Transfer command, but if we do, we will 159 * miss situations where the host starts another SETUP phase instead of 160 * the DATA phase. Such cases happen at least on TD.7.6 of the Link 161 * Layer Compliance Suite. 162 * 163 * The problem surfaces due to the fact that in case of back-to-back 164 * SETUP packets there will be no XferNotReady(DATA) generated and we 165 * will be stuck waiting for XferNotReady(DATA) forever. 166 * 167 * By looking at tables 9-13 and 9-14 of the Databook, we can see that 168 * it tells us to start Data Phase right away. It also mentions that if 169 * we receive a SETUP phase instead of the DATA phase, core will issue 170 * XferComplete for the DATA phase, before actually initiating it in 171 * the wire, with the TRB's status set to "SETUP_PENDING". Such status 172 * can only be used to print some debugging logs, as the core expects 173 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB, 174 * just so it completes right away, without transferring anything and, 175 * only then, we can go back to the SETUP phase. 176 * 177 * Because of this scenario, SNPS decided to change the programming 178 * model of control transfers and support on-demand transfers only for 179 * the STATUS phase. To fix the issue we have now, we will always wait 180 * for gadget driver to queue the DATA phase's struct usb_request, then 181 * start it right away. 182 * 183 * If we're actually in a 2-stage transfer, we will wait for 184 * XferNotReady(STATUS). 185 */ 186 if (dwc->three_stage_setup) { 187 unsigned direction; 188 189 direction = dwc->ep0_expect_in; 190 dwc->ep0state = EP0_DATA_PHASE; 191 192 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req); 193 194 dep->flags &= ~DWC3_EP0_DIR_IN; 195 } 196 197 return 0; 198 } 199 200 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request, 201 gfp_t gfp_flags) 202 { 203 struct dwc3_request *req = to_dwc3_request(request); 204 struct dwc3_ep *dep = to_dwc3_ep(ep); 205 struct dwc3 *dwc = dep->dwc; 206 207 unsigned long flags; 208 209 int ret; 210 211 spin_lock_irqsave(&dwc->lock, flags); 212 if (!dep->endpoint.desc) { 213 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s", 214 request, dep->name); 215 ret = -ESHUTDOWN; 216 goto out; 217 } 218 219 /* we share one TRB for ep0/1 */ 220 if (!list_empty(&dep->request_list)) { 221 ret = -EBUSY; 222 goto out; 223 } 224 225 dev_vdbg(dwc->dev, "queueing request %p to %s length %d state '%s'", 226 request, dep->name, request->length, 227 dwc3_ep0_state_string(dwc->ep0state)); 228 229 ret = __dwc3_gadget_ep0_queue(dep, req); 230 231 out: 232 spin_unlock_irqrestore(&dwc->lock, flags); 233 234 return ret; 235 } 236 237 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc) 238 { 239 struct dwc3_ep *dep; 240 241 /* reinitialize physical ep1 */ 242 dep = dwc->eps[1]; 243 dep->flags = DWC3_EP_ENABLED; 244 245 /* stall is always issued on EP0 */ 246 dep = dwc->eps[0]; 247 __dwc3_gadget_ep_set_halt(dep, 1, false); 248 dep->flags = DWC3_EP_ENABLED; 249 dwc->delayed_status = false; 250 251 if (!list_empty(&dep->request_list)) { 252 struct dwc3_request *req; 253 254 req = next_request(&dep->request_list); 255 dwc3_gadget_giveback(dep, req, -ECONNRESET); 256 } 257 258 dwc->ep0state = EP0_SETUP_PHASE; 259 dwc3_ep0_out_start(dwc); 260 } 261 262 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value) 263 { 264 struct dwc3_ep *dep = to_dwc3_ep(ep); 265 struct dwc3 *dwc = dep->dwc; 266 267 dwc3_ep0_stall_and_restart(dwc); 268 269 return 0; 270 } 271 272 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value) 273 { 274 unsigned long flags; 275 int ret; 276 277 spin_lock_irqsave(&dwc->lock, flags); 278 ret = __dwc3_gadget_ep0_set_halt(ep, value); 279 spin_unlock_irqrestore(&dwc->lock, flags); 280 281 return ret; 282 } 283 284 void dwc3_ep0_out_start(struct dwc3 *dwc) 285 { 286 int ret; 287 288 ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8, 289 DWC3_TRBCTL_CONTROL_SETUP); 290 WARN_ON(ret < 0); 291 } 292 293 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le) 294 { 295 struct dwc3_ep *dep; 296 u32 windex = le16_to_cpu(wIndex_le); 297 u32 epnum; 298 299 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1; 300 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) 301 epnum |= 1; 302 303 dep = dwc->eps[epnum]; 304 if (dep->flags & DWC3_EP_ENABLED) 305 return dep; 306 307 return NULL; 308 } 309 310 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req) 311 { 312 } 313 /* 314 * ch 9.4.5 315 */ 316 static int dwc3_ep0_handle_status(struct dwc3 *dwc, 317 struct usb_ctrlrequest *ctrl) 318 { 319 struct dwc3_ep *dep; 320 u32 recip; 321 u32 reg; 322 u16 usb_status = 0; 323 __le16 *response_pkt; 324 325 recip = ctrl->bRequestType & USB_RECIP_MASK; 326 switch (recip) { 327 case USB_RECIP_DEVICE: 328 /* 329 * LTM will be set once we know how to set this in HW. 330 */ 331 usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED; 332 333 if (dwc->speed == DWC3_DSTS_SUPERSPEED) { 334 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 335 if (reg & DWC3_DCTL_INITU1ENA) 336 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED; 337 if (reg & DWC3_DCTL_INITU2ENA) 338 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED; 339 } 340 341 break; 342 343 case USB_RECIP_INTERFACE: 344 /* 345 * Function Remote Wake Capable D0 346 * Function Remote Wakeup D1 347 */ 348 break; 349 350 case USB_RECIP_ENDPOINT: 351 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex); 352 if (!dep) 353 return -EINVAL; 354 355 if (dep->flags & DWC3_EP_STALL) 356 usb_status = 1 << USB_ENDPOINT_HALT; 357 break; 358 default: 359 return -EINVAL; 360 } 361 362 response_pkt = (__le16 *) dwc->setup_buf; 363 *response_pkt = cpu_to_le16(usb_status); 364 365 dep = dwc->eps[0]; 366 dwc->ep0_usb_req.dep = dep; 367 dwc->ep0_usb_req.request.length = sizeof(*response_pkt); 368 dwc->ep0_usb_req.request.buf = dwc->setup_buf; 369 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl; 370 371 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); 372 } 373 374 static int dwc3_ep0_handle_feature(struct dwc3 *dwc, 375 struct usb_ctrlrequest *ctrl, int set) 376 { 377 struct dwc3_ep *dep; 378 u32 recip; 379 u32 wValue; 380 u32 wIndex; 381 u32 reg; 382 int ret; 383 enum usb_device_state state; 384 385 wValue = le16_to_cpu(ctrl->wValue); 386 wIndex = le16_to_cpu(ctrl->wIndex); 387 recip = ctrl->bRequestType & USB_RECIP_MASK; 388 state = dwc->gadget.state; 389 390 switch (recip) { 391 case USB_RECIP_DEVICE: 392 393 switch (wValue) { 394 case USB_DEVICE_REMOTE_WAKEUP: 395 break; 396 /* 397 * 9.4.1 says only only for SS, in AddressState only for 398 * default control pipe 399 */ 400 case USB_DEVICE_U1_ENABLE: 401 if (state != USB_STATE_CONFIGURED) 402 return -EINVAL; 403 if (dwc->speed != DWC3_DSTS_SUPERSPEED) 404 return -EINVAL; 405 406 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 407 if (set) 408 reg |= DWC3_DCTL_INITU1ENA; 409 else 410 reg &= ~DWC3_DCTL_INITU1ENA; 411 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 412 break; 413 414 case USB_DEVICE_U2_ENABLE: 415 if (state != USB_STATE_CONFIGURED) 416 return -EINVAL; 417 if (dwc->speed != DWC3_DSTS_SUPERSPEED) 418 return -EINVAL; 419 420 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 421 if (set) 422 reg |= DWC3_DCTL_INITU2ENA; 423 else 424 reg &= ~DWC3_DCTL_INITU2ENA; 425 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 426 break; 427 428 case USB_DEVICE_LTM_ENABLE: 429 return -EINVAL; 430 431 case USB_DEVICE_TEST_MODE: 432 if ((wIndex & 0xff) != 0) 433 return -EINVAL; 434 if (!set) 435 return -EINVAL; 436 437 dwc->test_mode_nr = wIndex >> 8; 438 dwc->test_mode = true; 439 break; 440 default: 441 return -EINVAL; 442 } 443 break; 444 445 case USB_RECIP_INTERFACE: 446 switch (wValue) { 447 case USB_INTRF_FUNC_SUSPEND: 448 if (wIndex & USB_INTRF_FUNC_SUSPEND_LP) 449 /* XXX enable Low power suspend */ 450 ; 451 if (wIndex & USB_INTRF_FUNC_SUSPEND_RW) 452 /* XXX enable remote wakeup */ 453 ; 454 break; 455 default: 456 return -EINVAL; 457 } 458 break; 459 460 case USB_RECIP_ENDPOINT: 461 switch (wValue) { 462 case USB_ENDPOINT_HALT: 463 dep = dwc3_wIndex_to_dep(dwc, wIndex); 464 if (!dep) 465 return -EINVAL; 466 if (set == 0 && (dep->flags & DWC3_EP_WEDGE)) 467 break; 468 ret = __dwc3_gadget_ep_set_halt(dep, set, true); 469 if (ret) 470 return -EINVAL; 471 break; 472 default: 473 return -EINVAL; 474 } 475 break; 476 477 default: 478 return -EINVAL; 479 } 480 481 return 0; 482 } 483 484 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 485 { 486 enum usb_device_state state = dwc->gadget.state; 487 u32 addr; 488 u32 reg; 489 490 addr = le16_to_cpu(ctrl->wValue); 491 if (addr > 127) { 492 dev_dbg(dwc->dev, "invalid device address %d", addr); 493 return -EINVAL; 494 } 495 496 if (state == USB_STATE_CONFIGURED) { 497 dev_dbg(dwc->dev, "trying to set address when configured"); 498 return -EINVAL; 499 } 500 501 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 502 reg &= ~(DWC3_DCFG_DEVADDR_MASK); 503 reg |= DWC3_DCFG_DEVADDR(addr); 504 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 505 506 if (addr) 507 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS); 508 else 509 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT); 510 511 return 0; 512 } 513 514 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 515 { 516 int ret; 517 518 spin_unlock(&dwc->lock); 519 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl); 520 spin_lock(&dwc->lock); 521 return ret; 522 } 523 524 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 525 { 526 enum usb_device_state state = dwc->gadget.state; 527 u32 cfg; 528 int ret; 529 u32 reg; 530 531 dwc->start_config_issued = false; 532 cfg = le16_to_cpu(ctrl->wValue); 533 534 switch (state) { 535 case USB_STATE_DEFAULT: 536 return -EINVAL; 537 538 case USB_STATE_ADDRESS: 539 ret = dwc3_ep0_delegate_req(dwc, ctrl); 540 /* if the cfg matches and the cfg is non zero */ 541 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) { 542 543 /* 544 * only change state if set_config has already 545 * been processed. If gadget driver returns 546 * USB_GADGET_DELAYED_STATUS, we will wait 547 * to change the state on the next usb_ep_queue() 548 */ 549 if (ret == 0) 550 usb_gadget_set_state(&dwc->gadget, 551 USB_STATE_CONFIGURED); 552 553 /* 554 * Enable transition to U1/U2 state when 555 * nothing is pending from application. 556 */ 557 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 558 reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA); 559 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 560 561 dwc->resize_fifos = true; 562 dev_dbg(dwc->dev, "resize FIFOs flag SET"); 563 } 564 break; 565 566 case USB_STATE_CONFIGURED: 567 ret = dwc3_ep0_delegate_req(dwc, ctrl); 568 if (!cfg && !ret) 569 usb_gadget_set_state(&dwc->gadget, 570 USB_STATE_ADDRESS); 571 break; 572 default: 573 ret = -EINVAL; 574 } 575 return ret; 576 } 577 578 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req) 579 { 580 struct dwc3_ep *dep = to_dwc3_ep(ep); 581 struct dwc3 *dwc = dep->dwc; 582 583 u32 param = 0; 584 u32 reg; 585 586 struct timing { 587 u8 u1sel; 588 u8 u1pel; 589 u16 u2sel; 590 u16 u2pel; 591 } __packed timing; 592 593 int ret; 594 595 memcpy(&timing, req->buf, sizeof(timing)); 596 597 dwc->u1sel = timing.u1sel; 598 dwc->u1pel = timing.u1pel; 599 dwc->u2sel = le16_to_cpu(timing.u2sel); 600 dwc->u2pel = le16_to_cpu(timing.u2pel); 601 602 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 603 if (reg & DWC3_DCTL_INITU2ENA) 604 param = dwc->u2pel; 605 if (reg & DWC3_DCTL_INITU1ENA) 606 param = dwc->u1pel; 607 608 /* 609 * According to Synopsys Databook, if parameter is 610 * greater than 125, a value of zero should be 611 * programmed in the register. 612 */ 613 if (param > 125) 614 param = 0; 615 616 /* now that we have the time, issue DGCMD Set Sel */ 617 ret = dwc3_send_gadget_generic_command(dwc, 618 DWC3_DGCMD_SET_PERIODIC_PAR, param); 619 WARN_ON(ret < 0); 620 } 621 622 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 623 { 624 struct dwc3_ep *dep; 625 enum usb_device_state state = dwc->gadget.state; 626 u16 wLength; 627 628 if (state == USB_STATE_DEFAULT) 629 return -EINVAL; 630 631 wLength = le16_to_cpu(ctrl->wLength); 632 633 if (wLength != 6) { 634 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n", 635 wLength); 636 return -EINVAL; 637 } 638 639 /* 640 * To handle Set SEL we need to receive 6 bytes from Host. So let's 641 * queue a usb_request for 6 bytes. 642 * 643 * Remember, though, this controller can't handle non-wMaxPacketSize 644 * aligned transfers on the OUT direction, so we queue a request for 645 * wMaxPacketSize instead. 646 */ 647 dep = dwc->eps[0]; 648 dwc->ep0_usb_req.dep = dep; 649 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket; 650 dwc->ep0_usb_req.request.buf = dwc->setup_buf; 651 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl; 652 653 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); 654 } 655 656 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 657 { 658 u16 wLength; 659 u16 wValue; 660 u16 wIndex; 661 662 wValue = le16_to_cpu(ctrl->wValue); 663 wLength = le16_to_cpu(ctrl->wLength); 664 wIndex = le16_to_cpu(ctrl->wIndex); 665 666 if (wIndex || wLength) 667 return -EINVAL; 668 669 /* 670 * REVISIT It's unclear from Databook what to do with this 671 * value. For now, just cache it. 672 */ 673 dwc->isoch_delay = wValue; 674 675 return 0; 676 } 677 678 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 679 { 680 int ret; 681 682 switch (ctrl->bRequest) { 683 case USB_REQ_GET_STATUS: 684 dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS"); 685 ret = dwc3_ep0_handle_status(dwc, ctrl); 686 break; 687 case USB_REQ_CLEAR_FEATURE: 688 dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE"); 689 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0); 690 break; 691 case USB_REQ_SET_FEATURE: 692 dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE"); 693 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1); 694 break; 695 case USB_REQ_SET_ADDRESS: 696 dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS"); 697 ret = dwc3_ep0_set_address(dwc, ctrl); 698 break; 699 case USB_REQ_SET_CONFIGURATION: 700 dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION"); 701 ret = dwc3_ep0_set_config(dwc, ctrl); 702 break; 703 case USB_REQ_SET_SEL: 704 dev_vdbg(dwc->dev, "USB_REQ_SET_SEL"); 705 ret = dwc3_ep0_set_sel(dwc, ctrl); 706 break; 707 case USB_REQ_SET_ISOCH_DELAY: 708 dev_vdbg(dwc->dev, "USB_REQ_SET_ISOCH_DELAY"); 709 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl); 710 break; 711 default: 712 dev_vdbg(dwc->dev, "Forwarding to gadget driver"); 713 ret = dwc3_ep0_delegate_req(dwc, ctrl); 714 break; 715 } 716 717 return ret; 718 } 719 720 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc, 721 const struct dwc3_event_depevt *event) 722 { 723 struct usb_ctrlrequest *ctrl = dwc->ctrl_req; 724 int ret = -EINVAL; 725 u32 len; 726 727 if (!dwc->gadget_driver) 728 goto out; 729 730 len = le16_to_cpu(ctrl->wLength); 731 if (!len) { 732 dwc->three_stage_setup = false; 733 dwc->ep0_expect_in = false; 734 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; 735 } else { 736 dwc->three_stage_setup = true; 737 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN); 738 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA; 739 } 740 741 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) 742 ret = dwc3_ep0_std_request(dwc, ctrl); 743 else 744 ret = dwc3_ep0_delegate_req(dwc, ctrl); 745 746 if (ret == USB_GADGET_DELAYED_STATUS) 747 dwc->delayed_status = true; 748 749 out: 750 if (ret < 0) 751 dwc3_ep0_stall_and_restart(dwc); 752 } 753 754 static void dwc3_ep0_complete_data(struct dwc3 *dwc, 755 const struct dwc3_event_depevt *event) 756 { 757 struct dwc3_request *r = NULL; 758 struct usb_request *ur; 759 struct dwc3_trb *trb; 760 struct dwc3_ep *ep0; 761 u32 transferred; 762 u32 status; 763 u32 length; 764 u8 epnum; 765 766 epnum = event->endpoint_number; 767 ep0 = dwc->eps[0]; 768 769 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; 770 771 trb = dwc->ep0_trb; 772 773 r = next_request(&ep0->request_list); 774 if (!r) 775 return; 776 777 status = DWC3_TRB_SIZE_TRBSTS(trb->size); 778 if (status == DWC3_TRBSTS_SETUP_PENDING) { 779 dev_dbg(dwc->dev, "Setup Pending received"); 780 781 if (r) 782 dwc3_gadget_giveback(ep0, r, -ECONNRESET); 783 784 return; 785 } 786 787 ur = &r->request; 788 789 length = trb->size & DWC3_TRB_SIZE_MASK; 790 791 if (dwc->ep0_bounced) { 792 unsigned transfer_size = ur->length; 793 unsigned maxp = ep0->endpoint.maxpacket; 794 795 transfer_size += (maxp - (transfer_size % maxp)); 796 transferred = min_t(u32, ur->length, 797 transfer_size - length); 798 memcpy(ur->buf, dwc->ep0_bounce, transferred); 799 } else { 800 transferred = ur->length - length; 801 } 802 803 ur->actual += transferred; 804 805 if ((epnum & 1) && ur->actual < ur->length) { 806 /* for some reason we did not get everything out */ 807 808 dwc3_ep0_stall_and_restart(dwc); 809 } else { 810 dwc3_gadget_giveback(ep0, r, 0); 811 812 if (IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) && 813 ur->length && ur->zero) { 814 int ret; 815 816 dwc->ep0_next_event = DWC3_EP0_COMPLETE; 817 818 ret = dwc3_ep0_start_trans(dwc, epnum, 819 dwc->ctrl_req_addr, 0, 820 DWC3_TRBCTL_CONTROL_DATA); 821 WARN_ON(ret < 0); 822 } 823 } 824 } 825 826 static void dwc3_ep0_complete_status(struct dwc3 *dwc, 827 const struct dwc3_event_depevt *event) 828 { 829 struct dwc3_request *r; 830 struct dwc3_ep *dep; 831 struct dwc3_trb *trb; 832 u32 status; 833 834 dep = dwc->eps[0]; 835 trb = dwc->ep0_trb; 836 837 if (!list_empty(&dep->request_list)) { 838 r = next_request(&dep->request_list); 839 840 dwc3_gadget_giveback(dep, r, 0); 841 } 842 843 if (dwc->test_mode) { 844 int ret; 845 846 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr); 847 if (ret < 0) { 848 dev_dbg(dwc->dev, "Invalid Test #%d", 849 dwc->test_mode_nr); 850 dwc3_ep0_stall_and_restart(dwc); 851 return; 852 } 853 } 854 855 status = DWC3_TRB_SIZE_TRBSTS(trb->size); 856 if (status == DWC3_TRBSTS_SETUP_PENDING) 857 dev_dbg(dwc->dev, "Setup Pending received"); 858 859 dwc->ep0state = EP0_SETUP_PHASE; 860 dwc3_ep0_out_start(dwc); 861 } 862 863 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc, 864 const struct dwc3_event_depevt *event) 865 { 866 struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; 867 868 dep->flags &= ~DWC3_EP_BUSY; 869 dep->resource_index = 0; 870 dwc->setup_packet_pending = false; 871 872 switch (dwc->ep0state) { 873 case EP0_SETUP_PHASE: 874 dev_vdbg(dwc->dev, "Setup Phase"); 875 dwc3_ep0_inspect_setup(dwc, event); 876 break; 877 878 case EP0_DATA_PHASE: 879 dev_vdbg(dwc->dev, "Data Phase"); 880 dwc3_ep0_complete_data(dwc, event); 881 break; 882 883 case EP0_STATUS_PHASE: 884 dev_vdbg(dwc->dev, "Status Phase"); 885 dwc3_ep0_complete_status(dwc, event); 886 break; 887 default: 888 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state); 889 } 890 } 891 892 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, 893 struct dwc3_ep *dep, struct dwc3_request *req) 894 { 895 int ret; 896 897 req->direction = !!dep->number; 898 899 if (req->request.length == 0) { 900 ret = dwc3_ep0_start_trans(dwc, dep->number, 901 dwc->ctrl_req_addr, 0, 902 DWC3_TRBCTL_CONTROL_DATA); 903 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) 904 && (dep->number == 0)) { 905 u32 transfer_size; 906 u32 maxpacket; 907 908 ret = usb_gadget_map_request(&dwc->gadget, &req->request, 909 dep->number); 910 if (ret) { 911 dev_dbg(dwc->dev, "failed to map request\n"); 912 return; 913 } 914 915 WARN_ON(req->request.length > DWC3_EP0_BOUNCE_SIZE); 916 917 maxpacket = dep->endpoint.maxpacket; 918 transfer_size = roundup(req->request.length, maxpacket); 919 920 dwc->ep0_bounced = true; 921 922 /* 923 * REVISIT in case request length is bigger than 924 * DWC3_EP0_BOUNCE_SIZE we will need two chained 925 * TRBs to handle the transfer. 926 */ 927 ret = dwc3_ep0_start_trans(dwc, dep->number, 928 dwc->ep0_bounce_addr, transfer_size, 929 DWC3_TRBCTL_CONTROL_DATA); 930 } else { 931 ret = usb_gadget_map_request(&dwc->gadget, &req->request, 932 dep->number); 933 if (ret) { 934 dev_dbg(dwc->dev, "failed to map request\n"); 935 return; 936 } 937 938 ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma, 939 req->request.length, DWC3_TRBCTL_CONTROL_DATA); 940 } 941 942 WARN_ON(ret < 0); 943 } 944 945 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep) 946 { 947 struct dwc3 *dwc = dep->dwc; 948 u32 type; 949 950 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3 951 : DWC3_TRBCTL_CONTROL_STATUS2; 952 953 return dwc3_ep0_start_trans(dwc, dep->number, 954 dwc->ctrl_req_addr, 0, type); 955 } 956 957 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep) 958 { 959 if (dwc->resize_fifos) { 960 dev_dbg(dwc->dev, "Resizing FIFOs"); 961 dwc3_gadget_resize_tx_fifos(dwc); 962 dwc->resize_fifos = 0; 963 } 964 965 WARN_ON(dwc3_ep0_start_control_status(dep)); 966 } 967 968 static void dwc3_ep0_do_control_status(struct dwc3 *dwc, 969 const struct dwc3_event_depevt *event) 970 { 971 struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; 972 973 __dwc3_ep0_do_control_status(dwc, dep); 974 } 975 976 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep) 977 { 978 struct dwc3_gadget_ep_cmd_params params; 979 u32 cmd; 980 int ret; 981 982 if (!dep->resource_index) 983 return; 984 985 cmd = DWC3_DEPCMD_ENDTRANSFER; 986 cmd |= DWC3_DEPCMD_CMDIOC; 987 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); 988 memset(¶ms, 0, sizeof(params)); 989 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); 990 WARN_ON_ONCE(ret); 991 dep->resource_index = 0; 992 } 993 994 static void dwc3_ep0_xfernotready(struct dwc3 *dwc, 995 const struct dwc3_event_depevt *event) 996 { 997 dwc->setup_packet_pending = true; 998 999 switch (event->status) { 1000 case DEPEVT_STATUS_CONTROL_DATA: 1001 dev_vdbg(dwc->dev, "Control Data"); 1002 1003 /* 1004 * We already have a DATA transfer in the controller's cache, 1005 * if we receive a XferNotReady(DATA) we will ignore it, unless 1006 * it's for the wrong direction. 1007 * 1008 * In that case, we must issue END_TRANSFER command to the Data 1009 * Phase we already have started and issue SetStall on the 1010 * control endpoint. 1011 */ 1012 if (dwc->ep0_expect_in != event->endpoint_number) { 1013 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in]; 1014 1015 dev_vdbg(dwc->dev, "Wrong direction for Data phase"); 1016 dwc3_ep0_end_control_data(dwc, dep); 1017 dwc3_ep0_stall_and_restart(dwc); 1018 return; 1019 } 1020 1021 break; 1022 1023 case DEPEVT_STATUS_CONTROL_STATUS: 1024 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) 1025 return; 1026 1027 dev_vdbg(dwc->dev, "Control Status"); 1028 1029 dwc->ep0state = EP0_STATUS_PHASE; 1030 1031 if (dwc->delayed_status) { 1032 WARN_ON_ONCE(event->endpoint_number != 1); 1033 dev_vdbg(dwc->dev, "Delayed Status"); 1034 return; 1035 } 1036 1037 dwc3_ep0_do_control_status(dwc, event); 1038 } 1039 } 1040 1041 void dwc3_ep0_interrupt(struct dwc3 *dwc, 1042 const struct dwc3_event_depevt *event) 1043 { 1044 u8 epnum = event->endpoint_number; 1045 1046 dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'", 1047 dwc3_ep_event_string(event->endpoint_event), 1048 epnum >> 1, (epnum & 1) ? "in" : "out", 1049 dwc3_ep0_state_string(dwc->ep0state)); 1050 1051 switch (event->endpoint_event) { 1052 case DWC3_DEPEVT_XFERCOMPLETE: 1053 dwc3_ep0_xfer_complete(dwc, event); 1054 break; 1055 1056 case DWC3_DEPEVT_XFERNOTREADY: 1057 dwc3_ep0_xfernotready(dwc, event); 1058 break; 1059 1060 case DWC3_DEPEVT_XFERINPROGRESS: 1061 case DWC3_DEPEVT_RXTXFIFOEVT: 1062 case DWC3_DEPEVT_STREAMEVT: 1063 case DWC3_DEPEVT_EPCMDCMPLT: 1064 break; 1065 } 1066 } 1067