1 /** 2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling 3 * 4 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/ep0.c) and ported 10 * to uboot. 11 * 12 * commit c00552ebaf : Merge 3.18-rc7 into usb-next 13 * 14 * SPDX-License-Identifier: GPL-2.0 15 */ 16 17 #include <linux/kernel.h> 18 #include <linux/list.h> 19 20 #include <linux/usb/ch9.h> 21 #include <linux/usb/gadget.h> 22 #include <linux/usb/composite.h> 23 24 #include "core.h" 25 #include "gadget.h" 26 #include "io.h" 27 28 #include "linux-compat.h" 29 30 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep); 31 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, 32 struct dwc3_ep *dep, struct dwc3_request *req); 33 34 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state) 35 { 36 switch (state) { 37 case EP0_UNCONNECTED: 38 return "Unconnected"; 39 case EP0_SETUP_PHASE: 40 return "Setup Phase"; 41 case EP0_DATA_PHASE: 42 return "Data Phase"; 43 case EP0_STATUS_PHASE: 44 return "Status Phase"; 45 default: 46 return "UNKNOWN"; 47 } 48 } 49 50 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma, 51 u32 len, u32 type) 52 { 53 struct dwc3_gadget_ep_cmd_params params; 54 struct dwc3_trb *trb; 55 struct dwc3_ep *dep; 56 57 int ret; 58 59 dep = dwc->eps[epnum]; 60 if (dep->flags & DWC3_EP_BUSY) { 61 dev_vdbg(dwc->dev, "%s still busy", dep->name); 62 return 0; 63 } 64 65 trb = dwc->ep0_trb; 66 67 trb->bpl = lower_32_bits(buf_dma); 68 trb->bph = upper_32_bits(buf_dma); 69 trb->size = len; 70 trb->ctrl = type; 71 72 trb->ctrl |= (DWC3_TRB_CTRL_HWO 73 | DWC3_TRB_CTRL_LST 74 | DWC3_TRB_CTRL_IOC 75 | DWC3_TRB_CTRL_ISP_IMI); 76 77 dwc3_flush_cache((int)buf_dma, len); 78 dwc3_flush_cache((int)trb, sizeof(*trb)); 79 80 memset(¶ms, 0, sizeof(params)); 81 params.param0 = upper_32_bits(dwc->ep0_trb_addr); 82 params.param1 = lower_32_bits(dwc->ep0_trb_addr); 83 84 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 85 DWC3_DEPCMD_STARTTRANSFER, ¶ms); 86 if (ret < 0) { 87 dev_dbg(dwc->dev, "%s STARTTRANSFER failed", dep->name); 88 return ret; 89 } 90 91 dep->flags |= DWC3_EP_BUSY; 92 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc, 93 dep->number); 94 95 dwc->ep0_next_event = DWC3_EP0_COMPLETE; 96 97 return 0; 98 } 99 100 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep, 101 struct dwc3_request *req) 102 { 103 struct dwc3 *dwc = dep->dwc; 104 105 req->request.actual = 0; 106 req->request.status = -EINPROGRESS; 107 req->epnum = dep->number; 108 109 list_add_tail(&req->list, &dep->request_list); 110 111 /* 112 * Gadget driver might not be quick enough to queue a request 113 * before we get a Transfer Not Ready event on this endpoint. 114 * 115 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that 116 * flag is set, it's telling us that as soon as Gadget queues the 117 * required request, we should kick the transfer here because the 118 * IRQ we were waiting for is long gone. 119 */ 120 if (dep->flags & DWC3_EP_PENDING_REQUEST) { 121 unsigned direction; 122 123 direction = !!(dep->flags & DWC3_EP0_DIR_IN); 124 125 if (dwc->ep0state != EP0_DATA_PHASE) { 126 dev_WARN(dwc->dev, "Unexpected pending request\n"); 127 return 0; 128 } 129 130 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req); 131 132 dep->flags &= ~(DWC3_EP_PENDING_REQUEST | 133 DWC3_EP0_DIR_IN); 134 135 return 0; 136 } 137 138 /* 139 * In case gadget driver asked us to delay the STATUS phase, 140 * handle it here. 141 */ 142 if (dwc->delayed_status) { 143 unsigned direction; 144 145 direction = !dwc->ep0_expect_in; 146 dwc->delayed_status = false; 147 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED); 148 149 if (dwc->ep0state == EP0_STATUS_PHASE) 150 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]); 151 else 152 dev_dbg(dwc->dev, "too early for delayed status"); 153 154 return 0; 155 } 156 157 /* 158 * Unfortunately we have uncovered a limitation wrt the Data Phase. 159 * 160 * Section 9.4 says we can wait for the XferNotReady(DATA) event to 161 * come before issueing Start Transfer command, but if we do, we will 162 * miss situations where the host starts another SETUP phase instead of 163 * the DATA phase. Such cases happen at least on TD.7.6 of the Link 164 * Layer Compliance Suite. 165 * 166 * The problem surfaces due to the fact that in case of back-to-back 167 * SETUP packets there will be no XferNotReady(DATA) generated and we 168 * will be stuck waiting for XferNotReady(DATA) forever. 169 * 170 * By looking at tables 9-13 and 9-14 of the Databook, we can see that 171 * it tells us to start Data Phase right away. It also mentions that if 172 * we receive a SETUP phase instead of the DATA phase, core will issue 173 * XferComplete for the DATA phase, before actually initiating it in 174 * the wire, with the TRB's status set to "SETUP_PENDING". Such status 175 * can only be used to print some debugging logs, as the core expects 176 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB, 177 * just so it completes right away, without transferring anything and, 178 * only then, we can go back to the SETUP phase. 179 * 180 * Because of this scenario, SNPS decided to change the programming 181 * model of control transfers and support on-demand transfers only for 182 * the STATUS phase. To fix the issue we have now, we will always wait 183 * for gadget driver to queue the DATA phase's struct usb_request, then 184 * start it right away. 185 * 186 * If we're actually in a 2-stage transfer, we will wait for 187 * XferNotReady(STATUS). 188 */ 189 if (dwc->three_stage_setup) { 190 unsigned direction; 191 192 direction = dwc->ep0_expect_in; 193 dwc->ep0state = EP0_DATA_PHASE; 194 195 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req); 196 197 dep->flags &= ~DWC3_EP0_DIR_IN; 198 } 199 200 return 0; 201 } 202 203 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request, 204 gfp_t gfp_flags) 205 { 206 struct dwc3_request *req = to_dwc3_request(request); 207 struct dwc3_ep *dep = to_dwc3_ep(ep); 208 struct dwc3 *dwc = dep->dwc; 209 210 unsigned long flags; 211 212 int ret; 213 214 spin_lock_irqsave(&dwc->lock, flags); 215 if (!dep->endpoint.desc) { 216 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s", 217 request, dep->name); 218 ret = -ESHUTDOWN; 219 goto out; 220 } 221 222 /* we share one TRB for ep0/1 */ 223 if (!list_empty(&dep->request_list)) { 224 ret = -EBUSY; 225 goto out; 226 } 227 228 dev_vdbg(dwc->dev, "queueing request %p to %s length %d state '%s'", 229 request, dep->name, request->length, 230 dwc3_ep0_state_string(dwc->ep0state)); 231 232 ret = __dwc3_gadget_ep0_queue(dep, req); 233 234 out: 235 spin_unlock_irqrestore(&dwc->lock, flags); 236 237 return ret; 238 } 239 240 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc) 241 { 242 struct dwc3_ep *dep; 243 244 /* reinitialize physical ep1 */ 245 dep = dwc->eps[1]; 246 dep->flags = DWC3_EP_ENABLED; 247 248 /* stall is always issued on EP0 */ 249 dep = dwc->eps[0]; 250 __dwc3_gadget_ep_set_halt(dep, 1, false); 251 dep->flags = DWC3_EP_ENABLED; 252 dwc->delayed_status = false; 253 254 if (!list_empty(&dep->request_list)) { 255 struct dwc3_request *req; 256 257 req = next_request(&dep->request_list); 258 dwc3_gadget_giveback(dep, req, -ECONNRESET); 259 } 260 261 dwc->ep0state = EP0_SETUP_PHASE; 262 dwc3_ep0_out_start(dwc); 263 } 264 265 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value) 266 { 267 struct dwc3_ep *dep = to_dwc3_ep(ep); 268 struct dwc3 *dwc = dep->dwc; 269 270 dwc3_ep0_stall_and_restart(dwc); 271 272 return 0; 273 } 274 275 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value) 276 { 277 unsigned long flags; 278 int ret; 279 280 spin_lock_irqsave(&dwc->lock, flags); 281 ret = __dwc3_gadget_ep0_set_halt(ep, value); 282 spin_unlock_irqrestore(&dwc->lock, flags); 283 284 return ret; 285 } 286 287 void dwc3_ep0_out_start(struct dwc3 *dwc) 288 { 289 int ret; 290 291 ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8, 292 DWC3_TRBCTL_CONTROL_SETUP); 293 WARN_ON(ret < 0); 294 } 295 296 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le) 297 { 298 struct dwc3_ep *dep; 299 u32 windex = le16_to_cpu(wIndex_le); 300 u32 epnum; 301 302 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1; 303 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) 304 epnum |= 1; 305 306 dep = dwc->eps[epnum]; 307 if (dep->flags & DWC3_EP_ENABLED) 308 return dep; 309 310 return NULL; 311 } 312 313 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req) 314 { 315 } 316 /* 317 * ch 9.4.5 318 */ 319 static int dwc3_ep0_handle_status(struct dwc3 *dwc, 320 struct usb_ctrlrequest *ctrl) 321 { 322 struct dwc3_ep *dep; 323 u32 recip; 324 u32 reg; 325 u16 usb_status = 0; 326 __le16 *response_pkt; 327 328 recip = ctrl->bRequestType & USB_RECIP_MASK; 329 switch (recip) { 330 case USB_RECIP_DEVICE: 331 /* 332 * LTM will be set once we know how to set this in HW. 333 */ 334 usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED; 335 336 if (dwc->speed == DWC3_DSTS_SUPERSPEED) { 337 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 338 if (reg & DWC3_DCTL_INITU1ENA) 339 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED; 340 if (reg & DWC3_DCTL_INITU2ENA) 341 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED; 342 } 343 344 break; 345 346 case USB_RECIP_INTERFACE: 347 /* 348 * Function Remote Wake Capable D0 349 * Function Remote Wakeup D1 350 */ 351 break; 352 353 case USB_RECIP_ENDPOINT: 354 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex); 355 if (!dep) 356 return -EINVAL; 357 358 if (dep->flags & DWC3_EP_STALL) 359 usb_status = 1 << USB_ENDPOINT_HALT; 360 break; 361 default: 362 return -EINVAL; 363 } 364 365 response_pkt = (__le16 *) dwc->setup_buf; 366 *response_pkt = cpu_to_le16(usb_status); 367 368 dep = dwc->eps[0]; 369 dwc->ep0_usb_req.dep = dep; 370 dwc->ep0_usb_req.request.length = sizeof(*response_pkt); 371 dwc->ep0_usb_req.request.buf = dwc->setup_buf; 372 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl; 373 374 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); 375 } 376 377 static int dwc3_ep0_handle_feature(struct dwc3 *dwc, 378 struct usb_ctrlrequest *ctrl, int set) 379 { 380 struct dwc3_ep *dep; 381 u32 recip; 382 u32 wValue; 383 u32 wIndex; 384 u32 reg; 385 int ret; 386 enum usb_device_state state; 387 388 wValue = le16_to_cpu(ctrl->wValue); 389 wIndex = le16_to_cpu(ctrl->wIndex); 390 recip = ctrl->bRequestType & USB_RECIP_MASK; 391 state = dwc->gadget.state; 392 393 switch (recip) { 394 case USB_RECIP_DEVICE: 395 396 switch (wValue) { 397 case USB_DEVICE_REMOTE_WAKEUP: 398 break; 399 /* 400 * 9.4.1 says only only for SS, in AddressState only for 401 * default control pipe 402 */ 403 case USB_DEVICE_U1_ENABLE: 404 if (state != USB_STATE_CONFIGURED) 405 return -EINVAL; 406 if (dwc->speed != DWC3_DSTS_SUPERSPEED) 407 return -EINVAL; 408 409 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 410 if (set) 411 reg |= DWC3_DCTL_INITU1ENA; 412 else 413 reg &= ~DWC3_DCTL_INITU1ENA; 414 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 415 break; 416 417 case USB_DEVICE_U2_ENABLE: 418 if (state != USB_STATE_CONFIGURED) 419 return -EINVAL; 420 if (dwc->speed != DWC3_DSTS_SUPERSPEED) 421 return -EINVAL; 422 423 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 424 if (set) 425 reg |= DWC3_DCTL_INITU2ENA; 426 else 427 reg &= ~DWC3_DCTL_INITU2ENA; 428 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 429 break; 430 431 case USB_DEVICE_LTM_ENABLE: 432 return -EINVAL; 433 434 case USB_DEVICE_TEST_MODE: 435 if ((wIndex & 0xff) != 0) 436 return -EINVAL; 437 if (!set) 438 return -EINVAL; 439 440 dwc->test_mode_nr = wIndex >> 8; 441 dwc->test_mode = true; 442 break; 443 default: 444 return -EINVAL; 445 } 446 break; 447 448 case USB_RECIP_INTERFACE: 449 switch (wValue) { 450 case USB_INTRF_FUNC_SUSPEND: 451 if (wIndex & USB_INTRF_FUNC_SUSPEND_LP) 452 /* XXX enable Low power suspend */ 453 ; 454 if (wIndex & USB_INTRF_FUNC_SUSPEND_RW) 455 /* XXX enable remote wakeup */ 456 ; 457 break; 458 default: 459 return -EINVAL; 460 } 461 break; 462 463 case USB_RECIP_ENDPOINT: 464 switch (wValue) { 465 case USB_ENDPOINT_HALT: 466 dep = dwc3_wIndex_to_dep(dwc, wIndex); 467 if (!dep) 468 return -EINVAL; 469 if (set == 0 && (dep->flags & DWC3_EP_WEDGE)) 470 break; 471 ret = __dwc3_gadget_ep_set_halt(dep, set, true); 472 if (ret) 473 return -EINVAL; 474 break; 475 default: 476 return -EINVAL; 477 } 478 break; 479 480 default: 481 return -EINVAL; 482 } 483 484 return 0; 485 } 486 487 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 488 { 489 enum usb_device_state state = dwc->gadget.state; 490 u32 addr; 491 u32 reg; 492 493 addr = le16_to_cpu(ctrl->wValue); 494 if (addr > 127) { 495 dev_dbg(dwc->dev, "invalid device address %d", addr); 496 return -EINVAL; 497 } 498 499 if (state == USB_STATE_CONFIGURED) { 500 dev_dbg(dwc->dev, "trying to set address when configured"); 501 return -EINVAL; 502 } 503 504 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 505 reg &= ~(DWC3_DCFG_DEVADDR_MASK); 506 reg |= DWC3_DCFG_DEVADDR(addr); 507 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 508 509 if (addr) 510 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS); 511 else 512 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT); 513 514 return 0; 515 } 516 517 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 518 { 519 int ret; 520 521 spin_unlock(&dwc->lock); 522 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl); 523 spin_lock(&dwc->lock); 524 return ret; 525 } 526 527 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 528 { 529 enum usb_device_state state = dwc->gadget.state; 530 u32 cfg; 531 int ret; 532 u32 reg; 533 534 dwc->start_config_issued = false; 535 cfg = le16_to_cpu(ctrl->wValue); 536 537 switch (state) { 538 case USB_STATE_DEFAULT: 539 return -EINVAL; 540 541 case USB_STATE_ADDRESS: 542 ret = dwc3_ep0_delegate_req(dwc, ctrl); 543 /* if the cfg matches and the cfg is non zero */ 544 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) { 545 546 /* 547 * only change state if set_config has already 548 * been processed. If gadget driver returns 549 * USB_GADGET_DELAYED_STATUS, we will wait 550 * to change the state on the next usb_ep_queue() 551 */ 552 if (ret == 0) 553 usb_gadget_set_state(&dwc->gadget, 554 USB_STATE_CONFIGURED); 555 556 /* 557 * Enable transition to U1/U2 state when 558 * nothing is pending from application. 559 */ 560 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 561 reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA); 562 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 563 564 dwc->resize_fifos = true; 565 dev_dbg(dwc->dev, "resize FIFOs flag SET"); 566 } 567 break; 568 569 case USB_STATE_CONFIGURED: 570 ret = dwc3_ep0_delegate_req(dwc, ctrl); 571 if (!cfg && !ret) 572 usb_gadget_set_state(&dwc->gadget, 573 USB_STATE_ADDRESS); 574 break; 575 default: 576 ret = -EINVAL; 577 } 578 return ret; 579 } 580 581 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req) 582 { 583 struct dwc3_ep *dep = to_dwc3_ep(ep); 584 struct dwc3 *dwc = dep->dwc; 585 586 u32 param = 0; 587 u32 reg; 588 589 struct timing { 590 u8 u1sel; 591 u8 u1pel; 592 u16 u2sel; 593 u16 u2pel; 594 } __packed timing; 595 596 int ret; 597 598 memcpy(&timing, req->buf, sizeof(timing)); 599 600 dwc->u1sel = timing.u1sel; 601 dwc->u1pel = timing.u1pel; 602 dwc->u2sel = le16_to_cpu(timing.u2sel); 603 dwc->u2pel = le16_to_cpu(timing.u2pel); 604 605 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 606 if (reg & DWC3_DCTL_INITU2ENA) 607 param = dwc->u2pel; 608 if (reg & DWC3_DCTL_INITU1ENA) 609 param = dwc->u1pel; 610 611 /* 612 * According to Synopsys Databook, if parameter is 613 * greater than 125, a value of zero should be 614 * programmed in the register. 615 */ 616 if (param > 125) 617 param = 0; 618 619 /* now that we have the time, issue DGCMD Set Sel */ 620 ret = dwc3_send_gadget_generic_command(dwc, 621 DWC3_DGCMD_SET_PERIODIC_PAR, param); 622 WARN_ON(ret < 0); 623 } 624 625 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 626 { 627 struct dwc3_ep *dep; 628 enum usb_device_state state = dwc->gadget.state; 629 u16 wLength; 630 631 if (state == USB_STATE_DEFAULT) 632 return -EINVAL; 633 634 wLength = le16_to_cpu(ctrl->wLength); 635 636 if (wLength != 6) { 637 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n", 638 wLength); 639 return -EINVAL; 640 } 641 642 /* 643 * To handle Set SEL we need to receive 6 bytes from Host. So let's 644 * queue a usb_request for 6 bytes. 645 * 646 * Remember, though, this controller can't handle non-wMaxPacketSize 647 * aligned transfers on the OUT direction, so we queue a request for 648 * wMaxPacketSize instead. 649 */ 650 dep = dwc->eps[0]; 651 dwc->ep0_usb_req.dep = dep; 652 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket; 653 dwc->ep0_usb_req.request.buf = dwc->setup_buf; 654 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl; 655 656 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); 657 } 658 659 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 660 { 661 u16 wLength; 662 u16 wValue; 663 u16 wIndex; 664 665 wValue = le16_to_cpu(ctrl->wValue); 666 wLength = le16_to_cpu(ctrl->wLength); 667 wIndex = le16_to_cpu(ctrl->wIndex); 668 669 if (wIndex || wLength) 670 return -EINVAL; 671 672 /* 673 * REVISIT It's unclear from Databook what to do with this 674 * value. For now, just cache it. 675 */ 676 dwc->isoch_delay = wValue; 677 678 return 0; 679 } 680 681 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 682 { 683 int ret; 684 685 switch (ctrl->bRequest) { 686 case USB_REQ_GET_STATUS: 687 dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS"); 688 ret = dwc3_ep0_handle_status(dwc, ctrl); 689 break; 690 case USB_REQ_CLEAR_FEATURE: 691 dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE"); 692 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0); 693 break; 694 case USB_REQ_SET_FEATURE: 695 dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE"); 696 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1); 697 break; 698 case USB_REQ_SET_ADDRESS: 699 dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS"); 700 ret = dwc3_ep0_set_address(dwc, ctrl); 701 break; 702 case USB_REQ_SET_CONFIGURATION: 703 dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION"); 704 ret = dwc3_ep0_set_config(dwc, ctrl); 705 break; 706 case USB_REQ_SET_SEL: 707 dev_vdbg(dwc->dev, "USB_REQ_SET_SEL"); 708 ret = dwc3_ep0_set_sel(dwc, ctrl); 709 break; 710 case USB_REQ_SET_ISOCH_DELAY: 711 dev_vdbg(dwc->dev, "USB_REQ_SET_ISOCH_DELAY"); 712 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl); 713 break; 714 default: 715 dev_vdbg(dwc->dev, "Forwarding to gadget driver"); 716 ret = dwc3_ep0_delegate_req(dwc, ctrl); 717 break; 718 } 719 720 return ret; 721 } 722 723 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc, 724 const struct dwc3_event_depevt *event) 725 { 726 struct usb_ctrlrequest *ctrl = dwc->ctrl_req; 727 int ret = -EINVAL; 728 u32 len; 729 730 if (!dwc->gadget_driver) 731 goto out; 732 733 len = le16_to_cpu(ctrl->wLength); 734 if (!len) { 735 dwc->three_stage_setup = false; 736 dwc->ep0_expect_in = false; 737 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; 738 } else { 739 dwc->three_stage_setup = true; 740 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN); 741 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA; 742 } 743 744 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) 745 ret = dwc3_ep0_std_request(dwc, ctrl); 746 else 747 ret = dwc3_ep0_delegate_req(dwc, ctrl); 748 749 if (ret == USB_GADGET_DELAYED_STATUS) 750 dwc->delayed_status = true; 751 752 out: 753 if (ret < 0) 754 dwc3_ep0_stall_and_restart(dwc); 755 } 756 757 static void dwc3_ep0_complete_data(struct dwc3 *dwc, 758 const struct dwc3_event_depevt *event) 759 { 760 struct dwc3_request *r = NULL; 761 struct usb_request *ur; 762 struct dwc3_trb *trb; 763 struct dwc3_ep *ep0; 764 unsigned transfer_size = 0; 765 unsigned maxp; 766 void *buf; 767 u32 transferred = 0; 768 u32 status; 769 u32 length; 770 u8 epnum; 771 772 epnum = event->endpoint_number; 773 ep0 = dwc->eps[0]; 774 775 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; 776 777 trb = dwc->ep0_trb; 778 779 r = next_request(&ep0->request_list); 780 if (!r) 781 return; 782 783 dwc3_flush_cache((int)trb, sizeof(*trb)); 784 785 status = DWC3_TRB_SIZE_TRBSTS(trb->size); 786 if (status == DWC3_TRBSTS_SETUP_PENDING) { 787 dev_dbg(dwc->dev, "Setup Pending received"); 788 789 if (r) 790 dwc3_gadget_giveback(ep0, r, -ECONNRESET); 791 792 return; 793 } 794 795 ur = &r->request; 796 buf = ur->buf; 797 798 length = trb->size & DWC3_TRB_SIZE_MASK; 799 800 maxp = ep0->endpoint.maxpacket; 801 802 if (dwc->ep0_bounced) { 803 transfer_size = roundup((ur->length - transfer_size), 804 maxp); 805 transferred = min_t(u32, ur->length - transferred, 806 transfer_size - length); 807 dwc3_flush_cache((int)dwc->ep0_bounce, DWC3_EP0_BOUNCE_SIZE); 808 memcpy(buf, dwc->ep0_bounce, transferred); 809 } else { 810 transferred = ur->length - length; 811 } 812 813 ur->actual += transferred; 814 815 if ((epnum & 1) && ur->actual < ur->length) { 816 /* for some reason we did not get everything out */ 817 818 dwc3_ep0_stall_and_restart(dwc); 819 } else { 820 dwc3_gadget_giveback(ep0, r, 0); 821 822 if (IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) && 823 ur->length && ur->zero) { 824 int ret; 825 826 dwc->ep0_next_event = DWC3_EP0_COMPLETE; 827 828 ret = dwc3_ep0_start_trans(dwc, epnum, 829 dwc->ctrl_req_addr, 0, 830 DWC3_TRBCTL_CONTROL_DATA); 831 WARN_ON(ret < 0); 832 } 833 } 834 } 835 836 static void dwc3_ep0_complete_status(struct dwc3 *dwc, 837 const struct dwc3_event_depevt *event) 838 { 839 struct dwc3_request *r; 840 struct dwc3_ep *dep; 841 struct dwc3_trb *trb; 842 u32 status; 843 844 dep = dwc->eps[0]; 845 trb = dwc->ep0_trb; 846 847 if (!list_empty(&dep->request_list)) { 848 r = next_request(&dep->request_list); 849 850 dwc3_gadget_giveback(dep, r, 0); 851 } 852 853 if (dwc->test_mode) { 854 int ret; 855 856 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr); 857 if (ret < 0) { 858 dev_dbg(dwc->dev, "Invalid Test #%d", 859 dwc->test_mode_nr); 860 dwc3_ep0_stall_and_restart(dwc); 861 return; 862 } 863 } 864 865 status = DWC3_TRB_SIZE_TRBSTS(trb->size); 866 if (status == DWC3_TRBSTS_SETUP_PENDING) 867 dev_dbg(dwc->dev, "Setup Pending received"); 868 869 dwc->ep0state = EP0_SETUP_PHASE; 870 dwc3_ep0_out_start(dwc); 871 } 872 873 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc, 874 const struct dwc3_event_depevt *event) 875 { 876 struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; 877 878 dep->flags &= ~DWC3_EP_BUSY; 879 dep->resource_index = 0; 880 dwc->setup_packet_pending = false; 881 882 switch (dwc->ep0state) { 883 case EP0_SETUP_PHASE: 884 dev_vdbg(dwc->dev, "Setup Phase"); 885 dwc3_ep0_inspect_setup(dwc, event); 886 break; 887 888 case EP0_DATA_PHASE: 889 dev_vdbg(dwc->dev, "Data Phase"); 890 dwc3_ep0_complete_data(dwc, event); 891 break; 892 893 case EP0_STATUS_PHASE: 894 dev_vdbg(dwc->dev, "Status Phase"); 895 dwc3_ep0_complete_status(dwc, event); 896 break; 897 default: 898 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state); 899 } 900 } 901 902 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, 903 struct dwc3_ep *dep, struct dwc3_request *req) 904 { 905 int ret; 906 907 req->direction = !!dep->number; 908 909 if (req->request.length == 0) { 910 ret = dwc3_ep0_start_trans(dwc, dep->number, 911 dwc->ctrl_req_addr, 0, 912 DWC3_TRBCTL_CONTROL_DATA); 913 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) 914 && (dep->number == 0)) { 915 u32 transfer_size; 916 u32 maxpacket; 917 918 ret = usb_gadget_map_request(&dwc->gadget, &req->request, 919 dep->number); 920 if (ret) { 921 dev_dbg(dwc->dev, "failed to map request\n"); 922 return; 923 } 924 925 WARN_ON(req->request.length > DWC3_EP0_BOUNCE_SIZE); 926 927 maxpacket = dep->endpoint.maxpacket; 928 transfer_size = roundup(req->request.length, maxpacket); 929 930 dwc->ep0_bounced = true; 931 932 /* 933 * REVISIT in case request length is bigger than 934 * DWC3_EP0_BOUNCE_SIZE we will need two chained 935 * TRBs to handle the transfer. 936 */ 937 ret = dwc3_ep0_start_trans(dwc, dep->number, 938 dwc->ep0_bounce_addr, transfer_size, 939 DWC3_TRBCTL_CONTROL_DATA); 940 } else { 941 ret = usb_gadget_map_request(&dwc->gadget, &req->request, 942 dep->number); 943 if (ret) { 944 dev_dbg(dwc->dev, "failed to map request\n"); 945 return; 946 } 947 948 ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma, 949 req->request.length, DWC3_TRBCTL_CONTROL_DATA); 950 } 951 952 WARN_ON(ret < 0); 953 } 954 955 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep) 956 { 957 struct dwc3 *dwc = dep->dwc; 958 u32 type; 959 960 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3 961 : DWC3_TRBCTL_CONTROL_STATUS2; 962 963 return dwc3_ep0_start_trans(dwc, dep->number, 964 dwc->ctrl_req_addr, 0, type); 965 } 966 967 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep) 968 { 969 if (dwc->resize_fifos) { 970 dev_dbg(dwc->dev, "Resizing FIFOs"); 971 dwc3_gadget_resize_tx_fifos(dwc); 972 dwc->resize_fifos = 0; 973 } 974 975 WARN_ON(dwc3_ep0_start_control_status(dep)); 976 } 977 978 static void dwc3_ep0_do_control_status(struct dwc3 *dwc, 979 const struct dwc3_event_depevt *event) 980 { 981 struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; 982 983 __dwc3_ep0_do_control_status(dwc, dep); 984 } 985 986 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep) 987 { 988 struct dwc3_gadget_ep_cmd_params params; 989 u32 cmd; 990 int ret; 991 992 if (!dep->resource_index) 993 return; 994 995 cmd = DWC3_DEPCMD_ENDTRANSFER; 996 cmd |= DWC3_DEPCMD_CMDIOC; 997 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); 998 memset(¶ms, 0, sizeof(params)); 999 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); 1000 WARN_ON_ONCE(ret); 1001 dep->resource_index = 0; 1002 } 1003 1004 static void dwc3_ep0_xfernotready(struct dwc3 *dwc, 1005 const struct dwc3_event_depevt *event) 1006 { 1007 dwc->setup_packet_pending = true; 1008 1009 switch (event->status) { 1010 case DEPEVT_STATUS_CONTROL_DATA: 1011 dev_vdbg(dwc->dev, "Control Data"); 1012 1013 /* 1014 * We already have a DATA transfer in the controller's cache, 1015 * if we receive a XferNotReady(DATA) we will ignore it, unless 1016 * it's for the wrong direction. 1017 * 1018 * In that case, we must issue END_TRANSFER command to the Data 1019 * Phase we already have started and issue SetStall on the 1020 * control endpoint. 1021 */ 1022 if (dwc->ep0_expect_in != event->endpoint_number) { 1023 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in]; 1024 1025 dev_vdbg(dwc->dev, "Wrong direction for Data phase"); 1026 dwc3_ep0_end_control_data(dwc, dep); 1027 dwc3_ep0_stall_and_restart(dwc); 1028 return; 1029 } 1030 1031 break; 1032 1033 case DEPEVT_STATUS_CONTROL_STATUS: 1034 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) 1035 return; 1036 1037 dev_vdbg(dwc->dev, "Control Status"); 1038 1039 dwc->ep0state = EP0_STATUS_PHASE; 1040 1041 if (dwc->delayed_status) { 1042 WARN_ON_ONCE(event->endpoint_number != 1); 1043 dev_vdbg(dwc->dev, "Delayed Status"); 1044 return; 1045 } 1046 1047 dwc3_ep0_do_control_status(dwc, event); 1048 } 1049 } 1050 1051 void dwc3_ep0_interrupt(struct dwc3 *dwc, 1052 const struct dwc3_event_depevt *event) 1053 { 1054 u8 epnum = event->endpoint_number; 1055 1056 dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'", 1057 dwc3_ep_event_string(event->endpoint_event), 1058 epnum >> 1, (epnum & 1) ? "in" : "out", 1059 dwc3_ep0_state_string(dwc->ep0state)); 1060 1061 switch (event->endpoint_event) { 1062 case DWC3_DEPEVT_XFERCOMPLETE: 1063 dwc3_ep0_xfer_complete(dwc, event); 1064 break; 1065 1066 case DWC3_DEPEVT_XFERNOTREADY: 1067 dwc3_ep0_xfernotready(dwc, event); 1068 break; 1069 1070 case DWC3_DEPEVT_XFERINPROGRESS: 1071 case DWC3_DEPEVT_RXTXFIFOEVT: 1072 case DWC3_DEPEVT_STREAMEVT: 1073 case DWC3_DEPEVT_EPCMDCMPLT: 1074 break; 1075 } 1076 } 1077