1 /** 2 * dwc3-omap.c - OMAP Specific Glue layer 3 * 4 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/dwc3-omap.c) and ported 10 * to uboot. 11 * 12 * commit 7ee2566ff5 : usb: dwc3: dwc3-omap: get rid of ->prepare()/->complete() 13 * 14 * SPDX-License-Identifier: GPL-2.0 15 */ 16 17 #include <common.h> 18 #include <malloc.h> 19 #include <asm/io.h> 20 #include <dm.h> 21 #include <dwc3-omap-uboot.h> 22 #include <linux/usb/dwc3-omap.h> 23 #include <linux/ioport.h> 24 25 #include <linux/usb/otg.h> 26 #include <linux/compat.h> 27 28 #include "linux-compat.h" 29 30 /* 31 * All these registers belong to OMAP's Wrapper around the 32 * DesignWare USB3 Core. 33 */ 34 35 #define USBOTGSS_REVISION 0x0000 36 #define USBOTGSS_SYSCONFIG 0x0010 37 #define USBOTGSS_IRQ_EOI 0x0020 38 #define USBOTGSS_EOI_OFFSET 0x0008 39 #define USBOTGSS_IRQSTATUS_RAW_0 0x0024 40 #define USBOTGSS_IRQSTATUS_0 0x0028 41 #define USBOTGSS_IRQENABLE_SET_0 0x002c 42 #define USBOTGSS_IRQENABLE_CLR_0 0x0030 43 #define USBOTGSS_IRQ0_OFFSET 0x0004 44 #define USBOTGSS_IRQSTATUS_RAW_1 0x0030 45 #define USBOTGSS_IRQSTATUS_1 0x0034 46 #define USBOTGSS_IRQENABLE_SET_1 0x0038 47 #define USBOTGSS_IRQENABLE_CLR_1 0x003c 48 #define USBOTGSS_IRQSTATUS_RAW_2 0x0040 49 #define USBOTGSS_IRQSTATUS_2 0x0044 50 #define USBOTGSS_IRQENABLE_SET_2 0x0048 51 #define USBOTGSS_IRQENABLE_CLR_2 0x004c 52 #define USBOTGSS_IRQSTATUS_RAW_3 0x0050 53 #define USBOTGSS_IRQSTATUS_3 0x0054 54 #define USBOTGSS_IRQENABLE_SET_3 0x0058 55 #define USBOTGSS_IRQENABLE_CLR_3 0x005c 56 #define USBOTGSS_IRQSTATUS_EOI_MISC 0x0030 57 #define USBOTGSS_IRQSTATUS_RAW_MISC 0x0034 58 #define USBOTGSS_IRQSTATUS_MISC 0x0038 59 #define USBOTGSS_IRQENABLE_SET_MISC 0x003c 60 #define USBOTGSS_IRQENABLE_CLR_MISC 0x0040 61 #define USBOTGSS_IRQMISC_OFFSET 0x03fc 62 #define USBOTGSS_UTMI_OTG_CTRL 0x0080 63 #define USBOTGSS_UTMI_OTG_STATUS 0x0084 64 #define USBOTGSS_UTMI_OTG_OFFSET 0x0480 65 #define USBOTGSS_TXFIFO_DEPTH 0x0508 66 #define USBOTGSS_RXFIFO_DEPTH 0x050c 67 #define USBOTGSS_MMRAM_OFFSET 0x0100 68 #define USBOTGSS_FLADJ 0x0104 69 #define USBOTGSS_DEBUG_CFG 0x0108 70 #define USBOTGSS_DEBUG_DATA 0x010c 71 #define USBOTGSS_DEV_EBC_EN 0x0110 72 #define USBOTGSS_DEBUG_OFFSET 0x0600 73 74 /* SYSCONFIG REGISTER */ 75 #define USBOTGSS_SYSCONFIG_DMADISABLE (1 << 16) 76 77 /* IRQ_EOI REGISTER */ 78 #define USBOTGSS_IRQ_EOI_LINE_NUMBER (1 << 0) 79 80 /* IRQS0 BITS */ 81 #define USBOTGSS_IRQO_COREIRQ_ST (1 << 0) 82 83 /* IRQMISC BITS */ 84 #define USBOTGSS_IRQMISC_DMADISABLECLR (1 << 17) 85 #define USBOTGSS_IRQMISC_OEVT (1 << 16) 86 #define USBOTGSS_IRQMISC_DRVVBUS_RISE (1 << 13) 87 #define USBOTGSS_IRQMISC_CHRGVBUS_RISE (1 << 12) 88 #define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE (1 << 11) 89 #define USBOTGSS_IRQMISC_IDPULLUP_RISE (1 << 8) 90 #define USBOTGSS_IRQMISC_DRVVBUS_FALL (1 << 5) 91 #define USBOTGSS_IRQMISC_CHRGVBUS_FALL (1 << 4) 92 #define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL (1 << 3) 93 #define USBOTGSS_IRQMISC_IDPULLUP_FALL (1 << 0) 94 95 #define USBOTGSS_INTERRUPTS (USBOTGSS_IRQMISC_OEVT | \ 96 USBOTGSS_IRQMISC_DRVVBUS_RISE | \ 97 USBOTGSS_IRQMISC_CHRGVBUS_RISE | \ 98 USBOTGSS_IRQMISC_DISCHRGVBUS_RISE | \ 99 USBOTGSS_IRQMISC_IDPULLUP_RISE | \ 100 USBOTGSS_IRQMISC_DRVVBUS_FALL | \ 101 USBOTGSS_IRQMISC_CHRGVBUS_FALL | \ 102 USBOTGSS_IRQMISC_DISCHRGVBUS_FALL | \ 103 USBOTGSS_IRQMISC_IDPULLUP_FALL) 104 105 /* UTMI_OTG_CTRL REGISTER */ 106 #define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS (1 << 5) 107 #define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS (1 << 4) 108 #define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS (1 << 3) 109 #define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP (1 << 0) 110 111 /* UTMI_OTG_STATUS REGISTER */ 112 #define USBOTGSS_UTMI_OTG_STATUS_SW_MODE (1 << 31) 113 #define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT (1 << 9) 114 #define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8) 115 #define USBOTGSS_UTMI_OTG_STATUS_IDDIG (1 << 4) 116 #define USBOTGSS_UTMI_OTG_STATUS_SESSEND (1 << 3) 117 #define USBOTGSS_UTMI_OTG_STATUS_SESSVALID (1 << 2) 118 #define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID (1 << 1) 119 120 struct dwc3_omap { 121 struct device *dev; 122 123 void __iomem *base; 124 125 u32 utmi_otg_status; 126 u32 utmi_otg_offset; 127 u32 irqmisc_offset; 128 u32 irq_eoi_offset; 129 u32 debug_offset; 130 u32 irq0_offset; 131 132 u32 dma_status:1; 133 struct list_head list; 134 u32 index; 135 }; 136 137 static LIST_HEAD(dwc3_omap_list); 138 139 static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset) 140 { 141 return readl(base + offset); 142 } 143 144 static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value) 145 { 146 writel(value, base + offset); 147 } 148 149 static u32 dwc3_omap_read_utmi_status(struct dwc3_omap *omap) 150 { 151 return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS + 152 omap->utmi_otg_offset); 153 } 154 155 static void dwc3_omap_write_utmi_status(struct dwc3_omap *omap, u32 value) 156 { 157 dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS + 158 omap->utmi_otg_offset, value); 159 160 } 161 162 static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap) 163 { 164 return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0 - 165 omap->irq0_offset); 166 } 167 168 static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value) 169 { 170 dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 - 171 omap->irq0_offset, value); 172 173 } 174 175 static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap) 176 { 177 return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_MISC + 178 omap->irqmisc_offset); 179 } 180 181 static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value) 182 { 183 dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC + 184 omap->irqmisc_offset, value); 185 186 } 187 188 static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value) 189 { 190 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC + 191 omap->irqmisc_offset, value); 192 193 } 194 195 static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value) 196 { 197 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 - 198 omap->irq0_offset, value); 199 } 200 201 static void dwc3_omap_write_irqmisc_clr(struct dwc3_omap *omap, u32 value) 202 { 203 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_MISC + 204 omap->irqmisc_offset, value); 205 } 206 207 static void dwc3_omap_write_irq0_clr(struct dwc3_omap *omap, u32 value) 208 { 209 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_0 - 210 omap->irq0_offset, value); 211 } 212 213 static void dwc3_omap_set_mailbox(struct dwc3_omap *omap, 214 enum omap_dwc3_vbus_id_status status) 215 { 216 u32 val; 217 218 switch (status) { 219 case OMAP_DWC3_ID_GROUND: 220 dev_dbg(omap->dev, "ID GND\n"); 221 222 val = dwc3_omap_read_utmi_status(omap); 223 val &= ~(USBOTGSS_UTMI_OTG_STATUS_IDDIG 224 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID 225 | USBOTGSS_UTMI_OTG_STATUS_SESSEND); 226 val |= USBOTGSS_UTMI_OTG_STATUS_SESSVALID 227 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT; 228 dwc3_omap_write_utmi_status(omap, val); 229 break; 230 231 case OMAP_DWC3_VBUS_VALID: 232 dev_dbg(omap->dev, "VBUS Connect\n"); 233 234 val = dwc3_omap_read_utmi_status(omap); 235 val &= ~USBOTGSS_UTMI_OTG_STATUS_SESSEND; 236 val |= USBOTGSS_UTMI_OTG_STATUS_IDDIG 237 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID 238 | USBOTGSS_UTMI_OTG_STATUS_SESSVALID 239 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT; 240 dwc3_omap_write_utmi_status(omap, val); 241 break; 242 243 case OMAP_DWC3_ID_FLOAT: 244 case OMAP_DWC3_VBUS_OFF: 245 dev_dbg(omap->dev, "VBUS Disconnect\n"); 246 247 val = dwc3_omap_read_utmi_status(omap); 248 val &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSVALID 249 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID 250 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT); 251 val |= USBOTGSS_UTMI_OTG_STATUS_SESSEND 252 | USBOTGSS_UTMI_OTG_STATUS_IDDIG; 253 dwc3_omap_write_utmi_status(omap, val); 254 break; 255 256 default: 257 dev_dbg(omap->dev, "invalid state\n"); 258 } 259 } 260 261 static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap) 262 { 263 struct dwc3_omap *omap = _omap; 264 u32 reg; 265 266 reg = dwc3_omap_read_irqmisc_status(omap); 267 268 if (reg & USBOTGSS_IRQMISC_DMADISABLECLR) { 269 dev_dbg(omap->dev, "DMA Disable was Cleared\n"); 270 omap->dma_status = false; 271 } 272 273 if (reg & USBOTGSS_IRQMISC_OEVT) 274 dev_dbg(omap->dev, "OTG Event\n"); 275 276 if (reg & USBOTGSS_IRQMISC_DRVVBUS_RISE) 277 dev_dbg(omap->dev, "DRVVBUS Rise\n"); 278 279 if (reg & USBOTGSS_IRQMISC_CHRGVBUS_RISE) 280 dev_dbg(omap->dev, "CHRGVBUS Rise\n"); 281 282 if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_RISE) 283 dev_dbg(omap->dev, "DISCHRGVBUS Rise\n"); 284 285 if (reg & USBOTGSS_IRQMISC_IDPULLUP_RISE) 286 dev_dbg(omap->dev, "IDPULLUP Rise\n"); 287 288 if (reg & USBOTGSS_IRQMISC_DRVVBUS_FALL) 289 dev_dbg(omap->dev, "DRVVBUS Fall\n"); 290 291 if (reg & USBOTGSS_IRQMISC_CHRGVBUS_FALL) 292 dev_dbg(omap->dev, "CHRGVBUS Fall\n"); 293 294 if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_FALL) 295 dev_dbg(omap->dev, "DISCHRGVBUS Fall\n"); 296 297 if (reg & USBOTGSS_IRQMISC_IDPULLUP_FALL) 298 dev_dbg(omap->dev, "IDPULLUP Fall\n"); 299 300 dwc3_omap_write_irqmisc_status(omap, reg); 301 302 reg = dwc3_omap_read_irq0_status(omap); 303 304 dwc3_omap_write_irq0_status(omap, reg); 305 306 return IRQ_HANDLED; 307 } 308 309 static void dwc3_omap_enable_irqs(struct dwc3_omap *omap) 310 { 311 /* enable all IRQs */ 312 dwc3_omap_write_irq0_set(omap, USBOTGSS_IRQO_COREIRQ_ST); 313 314 dwc3_omap_write_irqmisc_set(omap, USBOTGSS_INTERRUPTS); 315 } 316 317 static void dwc3_omap_disable_irqs(struct dwc3_omap *omap) 318 { 319 /* disable all IRQs */ 320 dwc3_omap_write_irq0_clr(omap, USBOTGSS_IRQO_COREIRQ_ST); 321 322 dwc3_omap_write_irqmisc_clr(omap, USBOTGSS_INTERRUPTS); 323 } 324 325 static void dwc3_omap_map_offset(struct dwc3_omap *omap) 326 { 327 /* 328 * Differentiate between OMAP5 and AM437x. 329 * 330 * For OMAP5(ES2.0) and AM437x wrapper revision is same, even 331 * though there are changes in wrapper register offsets. 332 * 333 * Using dt compatible to differentiate AM437x. 334 */ 335 #ifdef CONFIG_AM43XX 336 omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET; 337 omap->irq0_offset = USBOTGSS_IRQ0_OFFSET; 338 omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET; 339 omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET; 340 omap->debug_offset = USBOTGSS_DEBUG_OFFSET; 341 #endif 342 } 343 344 static void dwc3_omap_set_utmi_mode(struct dwc3_omap *omap, int utmi_mode) 345 { 346 u32 reg; 347 348 reg = dwc3_omap_read_utmi_status(omap); 349 350 switch (utmi_mode) { 351 case DWC3_OMAP_UTMI_MODE_SW: 352 reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE; 353 break; 354 case DWC3_OMAP_UTMI_MODE_HW: 355 reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE; 356 break; 357 default: 358 dev_dbg(omap->dev, "UNKNOWN utmi mode %d\n", utmi_mode); 359 } 360 361 dwc3_omap_write_utmi_status(omap, reg); 362 } 363 364 /** 365 * dwc3_omap_uboot_init - dwc3 omap uboot initialization code 366 * @dev: struct dwc3_omap_device containing initialization data 367 * 368 * Entry point for dwc3 omap driver (equivalent to dwc3_omap_probe in linux 369 * kernel driver). Pointer to dwc3_omap_device should be passed containing 370 * base address and other initialization data. Returns '0' on success and 371 * a negative value on failure. 372 * 373 * Generally called from board_usb_init() implemented in board file. 374 */ 375 int dwc3_omap_uboot_init(struct dwc3_omap_device *omap_dev) 376 { 377 u32 reg; 378 struct device *dev = NULL; 379 struct dwc3_omap *omap; 380 381 omap = devm_kzalloc((struct udevice *)dev, sizeof(*omap), GFP_KERNEL); 382 if (!omap) 383 return -ENOMEM; 384 385 omap->base = omap_dev->base; 386 omap->index = omap_dev->index; 387 388 dwc3_omap_map_offset(omap); 389 dwc3_omap_set_utmi_mode(omap, omap_dev->utmi_mode); 390 391 /* check the DMA Status */ 392 reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG); 393 omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE); 394 395 dwc3_omap_set_mailbox(omap, omap_dev->vbus_id_status); 396 397 dwc3_omap_enable_irqs(omap); 398 list_add_tail(&omap->list, &dwc3_omap_list); 399 400 return 0; 401 } 402 403 /** 404 * dwc3_omap_uboot_exit - dwc3 omap uboot cleanup code 405 * @index: index of this controller 406 * 407 * Performs cleanup of memory allocated in dwc3_omap_uboot_init 408 * (equivalent to dwc3_omap_remove in linux). index of _this_ controller 409 * should be passed and should match with the index passed in 410 * dwc3_omap_device during init. 411 * 412 * Generally called from board file. 413 */ 414 void dwc3_omap_uboot_exit(int index) 415 { 416 struct dwc3_omap *omap = NULL; 417 418 list_for_each_entry(omap, &dwc3_omap_list, list) { 419 if (omap->index != index) 420 continue; 421 422 dwc3_omap_disable_irqs(omap); 423 list_del(&omap->list); 424 kfree(omap); 425 break; 426 } 427 } 428 429 /** 430 * dwc3_omap_uboot_interrupt_status - check the status of interrupt 431 * @index: index of this controller 432 * 433 * Checks the status of interrupts and returns true if an interrupt 434 * is detected or false otherwise. 435 * 436 * Generally called from board file. 437 */ 438 int dwc3_omap_uboot_interrupt_status(int index) 439 { 440 struct dwc3_omap *omap = NULL; 441 442 list_for_each_entry(omap, &dwc3_omap_list, list) 443 if (omap->index == index) 444 return dwc3_omap_interrupt(-1, omap); 445 446 return 0; 447 } 448 449 MODULE_ALIAS("platform:omap-dwc3"); 450 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 451 MODULE_LICENSE("GPL v2"); 452 MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer"); 453