1 /** 2 * core.h - DesignWare USB3 DRD Core Header 3 * 4 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.h) and ported 10 * to uboot. 11 * 12 * commit 460d098cb6 : usb: dwc3: make HIRD threshold configurable 13 * 14 * SPDX-License-Identifier: GPL-2.0 15 * 16 */ 17 18 #ifndef __DRIVERS_USB_DWC3_CORE_H 19 #define __DRIVERS_USB_DWC3_CORE_H 20 21 #include <linux/ioport.h> 22 23 #include <linux/usb/ch9.h> 24 #include <linux/usb/otg.h> 25 26 #define DWC3_MSG_MAX 500 27 28 /* Global constants */ 29 #define DWC3_EP0_BOUNCE_SIZE 512 30 #define DWC3_ENDPOINTS_NUM 32 31 #define DWC3_XHCI_RESOURCES_NUM 2 32 33 #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */ 34 #define DWC3_EVENT_SIZE 4 /* bytes */ 35 #define DWC3_EVENT_MAX_NUM 64 /* 2 events/endpoint */ 36 #define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM) 37 #define DWC3_EVENT_TYPE_MASK 0xfe 38 39 #define DWC3_EVENT_TYPE_DEV 0 40 #define DWC3_EVENT_TYPE_CARKIT 3 41 #define DWC3_EVENT_TYPE_I2C 4 42 43 #define DWC3_DEVICE_EVENT_DISCONNECT 0 44 #define DWC3_DEVICE_EVENT_RESET 1 45 #define DWC3_DEVICE_EVENT_CONNECT_DONE 2 46 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 47 #define DWC3_DEVICE_EVENT_WAKEUP 4 48 #define DWC3_DEVICE_EVENT_HIBER_REQ 5 49 #define DWC3_DEVICE_EVENT_EOPF 6 50 #define DWC3_DEVICE_EVENT_SOF 7 51 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 52 #define DWC3_DEVICE_EVENT_CMD_CMPL 10 53 #define DWC3_DEVICE_EVENT_OVERFLOW 11 54 55 #define DWC3_GEVNTCOUNT_MASK 0xfffc 56 #define DWC3_GSNPSID_MASK 0xffff0000 57 #define DWC3_GSNPSREV_MASK 0xffff 58 59 /* DWC3 registers memory space boundries */ 60 #define DWC3_XHCI_REGS_START 0x0 61 #define DWC3_XHCI_REGS_END 0x7fff 62 #define DWC3_GLOBALS_REGS_START 0xc100 63 #define DWC3_GLOBALS_REGS_END 0xc6ff 64 #define DWC3_DEVICE_REGS_START 0xc700 65 #define DWC3_DEVICE_REGS_END 0xcbff 66 #define DWC3_OTG_REGS_START 0xcc00 67 #define DWC3_OTG_REGS_END 0xccff 68 69 /* Global Registers */ 70 #define DWC3_GSBUSCFG0 0xc100 71 #define DWC3_GSBUSCFG1 0xc104 72 #define DWC3_GTXTHRCFG 0xc108 73 #define DWC3_GRXTHRCFG 0xc10c 74 #define DWC3_GCTL 0xc110 75 #define DWC3_GEVTEN 0xc114 76 #define DWC3_GSTS 0xc118 77 #define DWC3_GUCTL1 0xc11c 78 #define DWC3_GSNPSID 0xc120 79 #define DWC3_GGPIO 0xc124 80 #define DWC3_GUID 0xc128 81 #define DWC3_GUCTL 0xc12c 82 #define DWC3_GBUSERRADDR0 0xc130 83 #define DWC3_GBUSERRADDR1 0xc134 84 #define DWC3_GPRTBIMAP0 0xc138 85 #define DWC3_GPRTBIMAP1 0xc13c 86 #define DWC3_GHWPARAMS0 0xc140 87 #define DWC3_GHWPARAMS1 0xc144 88 #define DWC3_GHWPARAMS2 0xc148 89 #define DWC3_GHWPARAMS3 0xc14c 90 #define DWC3_GHWPARAMS4 0xc150 91 #define DWC3_GHWPARAMS5 0xc154 92 #define DWC3_GHWPARAMS6 0xc158 93 #define DWC3_GHWPARAMS7 0xc15c 94 #define DWC3_GDBGFIFOSPACE 0xc160 95 #define DWC3_GDBGLTSSM 0xc164 96 #define DWC3_GPRTBIMAP_HS0 0xc180 97 #define DWC3_GPRTBIMAP_HS1 0xc184 98 #define DWC3_GPRTBIMAP_FS0 0xc188 99 #define DWC3_GPRTBIMAP_FS1 0xc18c 100 101 #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04)) 102 #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04)) 103 104 #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04)) 105 106 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04)) 107 108 #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04)) 109 #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04)) 110 111 #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10)) 112 #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10)) 113 #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10)) 114 #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10)) 115 116 #define DWC3_GHWPARAMS8 0xc600 117 118 /* Device Registers */ 119 #define DWC3_DCFG 0xc700 120 #define DWC3_DCTL 0xc704 121 #define DWC3_DEVTEN 0xc708 122 #define DWC3_DSTS 0xc70c 123 #define DWC3_DGCMDPAR 0xc710 124 #define DWC3_DGCMD 0xc714 125 #define DWC3_DALEPENA 0xc720 126 #define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10)) 127 #define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10)) 128 #define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10)) 129 #define DWC3_DEPCMD(n) (0xc80c + (n * 0x10)) 130 131 /* OTG Registers */ 132 #define DWC3_OCFG 0xcc00 133 #define DWC3_OCTL 0xcc04 134 #define DWC3_OEVT 0xcc08 135 #define DWC3_OEVTEN 0xcc0C 136 #define DWC3_OSTS 0xcc10 137 138 /* Bit fields */ 139 140 /* Global Configuration Register */ 141 #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) 142 #define DWC3_GCTL_U2RSTECN (1 << 16) 143 #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) 144 #define DWC3_GCTL_CLK_BUS (0) 145 #define DWC3_GCTL_CLK_PIPE (1) 146 #define DWC3_GCTL_CLK_PIPEHALF (2) 147 #define DWC3_GCTL_CLK_MASK (3) 148 149 #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) 150 #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) 151 #define DWC3_GCTL_PRTCAP_HOST 1 152 #define DWC3_GCTL_PRTCAP_DEVICE 2 153 #define DWC3_GCTL_PRTCAP_OTG 3 154 155 #define DWC3_GCTL_CORESOFTRESET (1 << 11) 156 #define DWC3_GCTL_SOFITPSYNC (1 << 10) 157 #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) 158 #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) 159 #define DWC3_GCTL_DISSCRAMBLE (1 << 3) 160 #define DWC3_GCTL_U2EXIT_LFPS (1 << 2) 161 #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1) 162 #define DWC3_GCTL_DSBLCLKGTNG (1 << 0) 163 164 /* Global USB2 PHY Configuration Register */ 165 #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) 166 #define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8) 167 #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) 168 #define DWC3_GUSB2PHYCFG_PHYIF_8BIT (0 << 3) 169 #define DWC3_GUSB2PHYCFG_PHYIF_16BIT (1 << 3) 170 #define DWC3_GUSB2PHYCFG_USBTRDTIM_SHIFT (10) 171 #define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK (0xf << \ 172 DWC3_GUSB2PHYCFG_USBTRDTIM_SHIFT) 173 #define DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT (0x5 << \ 174 DWC3_GUSB2PHYCFG_USBTRDTIM_SHIFT) 175 #define DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT (0x9 << \ 176 DWC3_GUSB2PHYCFG_USBTRDTIM_SHIFT) 177 178 /* Global USB3 PIPE Control Register */ 179 #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) 180 #define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29) 181 #define DWC3_GUSB3PIPECTL_REQP1P2P3 (1 << 24) 182 #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19) 183 #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7) 184 #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1) 185 #define DWC3_GUSB3PIPECTL_DEPOCHANGE (1 << 18) 186 #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) 187 #define DWC3_GUSB3PIPECTL_LFPSFILT (1 << 9) 188 #define DWC3_GUSB3PIPECTL_RX_DETOPOLL (1 << 8) 189 #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3) 190 #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1) 191 192 /* Global TX Fifo Size Register */ 193 #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) 194 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) 195 196 /* Global Event Size Registers */ 197 #define DWC3_GEVNTSIZ_INTMASK (1 << 31) 198 #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff) 199 200 /* Global HWPARAMS1 Register */ 201 #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) 202 #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 203 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 204 #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2 205 #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24) 206 #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3) 207 208 /* Global HWPARAMS3 Register */ 209 #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3) 210 #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0 211 #define DWC3_GHWPARAMS3_SSPHY_IFC_ENA 1 212 #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2) 213 #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0 214 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1 215 #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2 216 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3 217 #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4) 218 #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0 219 #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1 220 221 /* Global HWPARAMS4 Register */ 222 #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13) 223 #define DWC3_MAX_HIBER_SCRATCHBUFS 15 224 225 /* Global HWPARAMS6 Register */ 226 #define DWC3_GHWPARAMS6_EN_FPGA (1 << 7) 227 228 /* Device Configuration Register */ 229 #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) 230 #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) 231 232 #define DWC3_DCFG_SPEED_MASK (7 << 0) 233 #define DWC3_DCFG_SUPERSPEED (4 << 0) 234 #define DWC3_DCFG_HIGHSPEED (0 << 0) 235 #define DWC3_DCFG_FULLSPEED2 (1 << 0) 236 #define DWC3_DCFG_LOWSPEED (2 << 0) 237 #define DWC3_DCFG_FULLSPEED1 (3 << 0) 238 239 #define DWC3_DCFG_LPM_CAP (1 << 22) 240 241 /* Device Control Register */ 242 #define DWC3_DCTL_RUN_STOP (1 << 31) 243 #define DWC3_DCTL_CSFTRST (1 << 30) 244 #define DWC3_DCTL_LSFTRST (1 << 29) 245 246 #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) 247 #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24) 248 249 #define DWC3_DCTL_APPL1RES (1 << 23) 250 251 /* These apply for core versions 1.87a and earlier */ 252 #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) 253 #define DWC3_DCTL_TRGTULST(n) ((n) << 17) 254 #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2)) 255 #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3)) 256 #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4)) 257 #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5)) 258 #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) 259 260 /* These apply for core versions 1.94a and later */ 261 #define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf) 262 #define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20) 263 264 #define DWC3_DCTL_KEEP_CONNECT (1 << 19) 265 #define DWC3_DCTL_L1_HIBER_EN (1 << 18) 266 #define DWC3_DCTL_CRS (1 << 17) 267 #define DWC3_DCTL_CSS (1 << 16) 268 269 #define DWC3_DCTL_INITU2ENA (1 << 12) 270 #define DWC3_DCTL_ACCEPTU2ENA (1 << 11) 271 #define DWC3_DCTL_INITU1ENA (1 << 10) 272 #define DWC3_DCTL_ACCEPTU1ENA (1 << 9) 273 #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) 274 275 #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) 276 #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) 277 278 #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) 279 #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) 280 #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) 281 #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) 282 #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) 283 #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) 284 #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) 285 286 /* Device Event Enable Register */ 287 #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12) 288 #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11) 289 #define DWC3_DEVTEN_CMDCMPLTEN (1 << 10) 290 #define DWC3_DEVTEN_ERRTICERREN (1 << 9) 291 #define DWC3_DEVTEN_SOFEN (1 << 7) 292 #define DWC3_DEVTEN_EOPFEN (1 << 6) 293 #define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5) 294 #define DWC3_DEVTEN_WKUPEVTEN (1 << 4) 295 #define DWC3_DEVTEN_ULSTCNGEN (1 << 3) 296 #define DWC3_DEVTEN_CONNECTDONEEN (1 << 2) 297 #define DWC3_DEVTEN_USBRSTEN (1 << 1) 298 #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0) 299 300 /* Device Status Register */ 301 #define DWC3_DSTS_DCNRD (1 << 29) 302 303 /* This applies for core versions 1.87a and earlier */ 304 #define DWC3_DSTS_PWRUPREQ (1 << 24) 305 306 /* These apply for core versions 1.94a and later */ 307 #define DWC3_DSTS_RSS (1 << 25) 308 #define DWC3_DSTS_SSS (1 << 24) 309 310 #define DWC3_DSTS_COREIDLE (1 << 23) 311 #define DWC3_DSTS_DEVCTRLHLT (1 << 22) 312 313 #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) 314 #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) 315 316 #define DWC3_DSTS_RXFIFOEMPTY (1 << 17) 317 318 #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3) 319 #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) 320 321 #define DWC3_DSTS_CONNECTSPD (7 << 0) 322 323 #define DWC3_DSTS_SUPERSPEED (4 << 0) 324 #define DWC3_DSTS_HIGHSPEED (0 << 0) 325 #define DWC3_DSTS_FULLSPEED2 (1 << 0) 326 #define DWC3_DSTS_LOWSPEED (2 << 0) 327 #define DWC3_DSTS_FULLSPEED1 (3 << 0) 328 329 /* Device Generic Command Register */ 330 #define DWC3_DGCMD_SET_LMP 0x01 331 #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 332 #define DWC3_DGCMD_XMIT_FUNCTION 0x03 333 334 /* These apply for core versions 1.94a and later */ 335 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04 336 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05 337 338 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 339 #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a 340 #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c 341 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 342 343 #define DWC3_DGCMD_STATUS(n) (((n) >> 15) & 1) 344 #define DWC3_DGCMD_CMDACT (1 << 10) 345 #define DWC3_DGCMD_CMDIOC (1 << 8) 346 347 /* Device Generic Command Parameter Register */ 348 #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0) 349 #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0) 350 #define DWC3_DGCMDPAR_RX_FIFO (0 << 5) 351 #define DWC3_DGCMDPAR_TX_FIFO (1 << 5) 352 #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0) 353 #define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0) 354 355 /* Device Endpoint Command Register */ 356 #define DWC3_DEPCMD_PARAM_SHIFT 16 357 #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT) 358 #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) 359 #define DWC3_DEPCMD_STATUS(x) (((x) >> 15) & 1) 360 #define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11) 361 #define DWC3_DEPCMD_CMDACT (1 << 10) 362 #define DWC3_DEPCMD_CMDIOC (1 << 8) 363 364 #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) 365 #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) 366 #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) 367 #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) 368 #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) 369 #define DWC3_DEPCMD_SETSTALL (0x04 << 0) 370 /* This applies for core versions 1.90a and earlier */ 371 #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) 372 /* This applies for core versions 1.94a and later */ 373 #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0) 374 #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) 375 #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) 376 377 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ 378 #define DWC3_DALEPENA_EP(n) (1 << n) 379 380 #define DWC3_DEPCMD_TYPE_CONTROL 0 381 #define DWC3_DEPCMD_TYPE_ISOC 1 382 #define DWC3_DEPCMD_TYPE_BULK 2 383 #define DWC3_DEPCMD_TYPE_INTR 3 384 385 /* Structures */ 386 387 struct dwc3_trb; 388 389 /** 390 * struct dwc3_event_buffer - Software event buffer representation 391 * @buf: _THE_ buffer 392 * @length: size of this buffer 393 * @lpos: event offset 394 * @count: cache of last read event count register 395 * @flags: flags related to this event buffer 396 * @dma: dma_addr_t 397 * @dwc: pointer to DWC controller 398 */ 399 struct dwc3_event_buffer { 400 void *buf; 401 unsigned length; 402 unsigned int lpos; 403 unsigned int count; 404 unsigned int flags; 405 406 #define DWC3_EVENT_PENDING (1UL << 0) 407 408 dma_addr_t dma; 409 410 struct dwc3 *dwc; 411 }; 412 413 #define DWC3_EP_FLAG_STALLED (1 << 0) 414 #define DWC3_EP_FLAG_WEDGED (1 << 1) 415 416 #define DWC3_EP_DIRECTION_TX true 417 #define DWC3_EP_DIRECTION_RX false 418 419 #define DWC3_TRB_NUM 32 420 #define DWC3_TRB_MASK (DWC3_TRB_NUM - 1) 421 422 /** 423 * struct dwc3_ep - device side endpoint representation 424 * @endpoint: usb endpoint 425 * @request_list: list of requests for this endpoint 426 * @req_queued: list of requests on this ep which have TRBs setup 427 * @trb_pool: array of transaction buffers 428 * @trb_pool_dma: dma address of @trb_pool 429 * @free_slot: next slot which is going to be used 430 * @busy_slot: first slot which is owned by HW 431 * @desc: usb_endpoint_descriptor pointer 432 * @dwc: pointer to DWC controller 433 * @saved_state: ep state saved during hibernation 434 * @flags: endpoint flags (wedged, stalled, ...) 435 * @current_trb: index of current used trb 436 * @number: endpoint number (1 - 15) 437 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK 438 * @resource_index: Resource transfer index 439 * @interval: the interval on which the ISOC transfer is started 440 * @name: a human readable name e.g. ep1out-bulk 441 * @direction: true for TX, false for RX 442 * @stream_capable: true when streams are enabled 443 */ 444 struct dwc3_ep { 445 struct usb_ep endpoint; 446 struct list_head request_list; 447 struct list_head req_queued; 448 449 struct dwc3_trb *trb_pool; 450 dma_addr_t trb_pool_dma; 451 u32 free_slot; 452 u32 busy_slot; 453 const struct usb_ss_ep_comp_descriptor *comp_desc; 454 struct dwc3 *dwc; 455 456 u32 saved_state; 457 unsigned flags; 458 #define DWC3_EP_ENABLED (1 << 0) 459 #define DWC3_EP_STALL (1 << 1) 460 #define DWC3_EP_WEDGE (1 << 2) 461 #define DWC3_EP_BUSY (1 << 4) 462 #define DWC3_EP_PENDING_REQUEST (1 << 5) 463 #define DWC3_EP_MISSED_ISOC (1 << 6) 464 465 /* This last one is specific to EP0 */ 466 #define DWC3_EP0_DIR_IN (1 << 31) 467 468 unsigned current_trb; 469 470 u8 number; 471 u8 type; 472 u8 resource_index; 473 u32 interval; 474 475 char name[20]; 476 477 unsigned direction:1; 478 unsigned stream_capable:1; 479 }; 480 481 enum dwc3_phy { 482 DWC3_PHY_UNKNOWN = 0, 483 DWC3_PHY_USB3, 484 DWC3_PHY_USB2, 485 }; 486 487 enum dwc3_ep0_next { 488 DWC3_EP0_UNKNOWN = 0, 489 DWC3_EP0_COMPLETE, 490 DWC3_EP0_NRDY_DATA, 491 DWC3_EP0_NRDY_STATUS, 492 }; 493 494 enum dwc3_ep0_state { 495 EP0_UNCONNECTED = 0, 496 EP0_SETUP_PHASE, 497 EP0_DATA_PHASE, 498 EP0_STATUS_PHASE, 499 }; 500 501 enum dwc3_link_state { 502 /* In SuperSpeed */ 503 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ 504 DWC3_LINK_STATE_U1 = 0x01, 505 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ 506 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ 507 DWC3_LINK_STATE_SS_DIS = 0x04, 508 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ 509 DWC3_LINK_STATE_SS_INACT = 0x06, 510 DWC3_LINK_STATE_POLL = 0x07, 511 DWC3_LINK_STATE_RECOV = 0x08, 512 DWC3_LINK_STATE_HRESET = 0x09, 513 DWC3_LINK_STATE_CMPLY = 0x0a, 514 DWC3_LINK_STATE_LPBK = 0x0b, 515 DWC3_LINK_STATE_RESET = 0x0e, 516 DWC3_LINK_STATE_RESUME = 0x0f, 517 DWC3_LINK_STATE_MASK = 0x0f, 518 }; 519 520 /* TRB Length, PCM and Status */ 521 #define DWC3_TRB_SIZE_MASK (0x00ffffff) 522 #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK) 523 #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24) 524 #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28) 525 526 #define DWC3_TRBSTS_OK 0 527 #define DWC3_TRBSTS_MISSED_ISOC 1 528 #define DWC3_TRBSTS_SETUP_PENDING 2 529 #define DWC3_TRB_STS_XFER_IN_PROG 4 530 531 /* TRB Control */ 532 #define DWC3_TRB_CTRL_HWO (1 << 0) 533 #define DWC3_TRB_CTRL_LST (1 << 1) 534 #define DWC3_TRB_CTRL_CHN (1 << 2) 535 #define DWC3_TRB_CTRL_CSP (1 << 3) 536 #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) 537 #define DWC3_TRB_CTRL_ISP_IMI (1 << 10) 538 #define DWC3_TRB_CTRL_IOC (1 << 11) 539 #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) 540 541 #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1) 542 #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2) 543 #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3) 544 #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4) 545 #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5) 546 #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6) 547 #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7) 548 #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8) 549 550 /** 551 * struct dwc3_trb - transfer request block (hw format) 552 * @bpl: DW0-3 553 * @bph: DW4-7 554 * @size: DW8-B 555 * @trl: DWC-F 556 */ 557 struct dwc3_trb { 558 u32 bpl; 559 u32 bph; 560 u32 size; 561 u32 ctrl; 562 } __packed; 563 564 /** 565 * dwc3_hwparams - copy of HWPARAMS registers 566 * @hwparams0 - GHWPARAMS0 567 * @hwparams1 - GHWPARAMS1 568 * @hwparams2 - GHWPARAMS2 569 * @hwparams3 - GHWPARAMS3 570 * @hwparams4 - GHWPARAMS4 571 * @hwparams5 - GHWPARAMS5 572 * @hwparams6 - GHWPARAMS6 573 * @hwparams7 - GHWPARAMS7 574 * @hwparams8 - GHWPARAMS8 575 */ 576 struct dwc3_hwparams { 577 u32 hwparams0; 578 u32 hwparams1; 579 u32 hwparams2; 580 u32 hwparams3; 581 u32 hwparams4; 582 u32 hwparams5; 583 u32 hwparams6; 584 u32 hwparams7; 585 u32 hwparams8; 586 }; 587 588 /* HWPARAMS0 */ 589 #define DWC3_MODE(n) ((n) & 0x7) 590 591 #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8) 592 593 /* HWPARAMS1 */ 594 #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) 595 596 /* HWPARAMS3 */ 597 #define DWC3_NUM_IN_EPS_MASK (0x1f << 18) 598 #define DWC3_NUM_EPS_MASK (0x3f << 12) 599 #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \ 600 (DWC3_NUM_EPS_MASK)) >> 12) 601 #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \ 602 (DWC3_NUM_IN_EPS_MASK)) >> 18) 603 604 /* HWPARAMS7 */ 605 #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff) 606 607 struct dwc3_request { 608 struct usb_request request; 609 struct list_head list; 610 struct dwc3_ep *dep; 611 u32 start_slot; 612 613 u8 epnum; 614 struct dwc3_trb *trb; 615 dma_addr_t trb_dma; 616 617 unsigned direction:1; 618 unsigned mapped:1; 619 unsigned queued:1; 620 }; 621 622 /* 623 * struct dwc3_scratchpad_array - hibernation scratchpad array 624 * (format defined by hw) 625 */ 626 struct dwc3_scratchpad_array { 627 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS]; 628 }; 629 630 /** 631 * struct dwc3 - representation of our controller 632 * @ctrl_req: usb control request which is used for ep0 633 * @ep0_trb: trb which is used for the ctrl_req 634 * @ep0_bounce: bounce buffer for ep0 635 * @setup_buf: used while precessing STD USB requests 636 * @ctrl_req_addr: dma address of ctrl_req 637 * @ep0_trb: dma address of ep0_trb 638 * @ep0_usb_req: dummy req used while handling STD USB requests 639 * @ep0_bounce_addr: dma address of ep0_bounce 640 * @scratch_addr: dma address of scratchbuf 641 * @lock: for synchronizing 642 * @dev: pointer to our struct device 643 * @xhci: pointer to our xHCI child 644 * @event_buffer_list: a list of event buffers 645 * @gadget: device side representation of the peripheral controller 646 * @gadget_driver: pointer to the gadget driver 647 * @regs: base address for our registers 648 * @regs_size: address space size 649 * @nr_scratch: number of scratch buffers 650 * @num_event_buffers: calculated number of event buffers 651 * @u1u2: only used on revisions <1.83a for workaround 652 * @maximum_speed: maximum speed requested (mainly for testing purposes) 653 * @revision: revision register contents 654 * @dr_mode: requested mode of operation 655 * @dcfg: saved contents of DCFG register 656 * @gctl: saved contents of GCTL register 657 * @isoch_delay: wValue from Set Isochronous Delay request; 658 * @u2sel: parameter from Set SEL request. 659 * @u2pel: parameter from Set SEL request. 660 * @u1sel: parameter from Set SEL request. 661 * @u1pel: parameter from Set SEL request. 662 * @num_out_eps: number of out endpoints 663 * @num_in_eps: number of in endpoints 664 * @ep0_next_event: hold the next expected event 665 * @ep0state: state of endpoint zero 666 * @link_state: link state 667 * @speed: device speed (super, high, full, low) 668 * @mem: points to start of memory which is used for this struct. 669 * @hwparams: copy of hwparams registers 670 * @root: debugfs root folder pointer 671 * @regset: debugfs pointer to regdump file 672 * @test_mode: true when we're entering a USB test mode 673 * @test_mode_nr: test feature selector 674 * @lpm_nyet_threshold: LPM NYET response threshold 675 * @hird_threshold: HIRD threshold 676 * @delayed_status: true when gadget driver asks for delayed status 677 * @ep0_bounced: true when we used bounce buffer 678 * @ep0_expect_in: true when we expect a DATA IN transfer 679 * @has_hibernation: true when dwc3 was configured with Hibernation 680 * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that 681 * there's now way for software to detect this in runtime. 682 * @is_utmi_l1_suspend: the core asserts output signal 683 * 0 - utmi_sleep_n 684 * 1 - utmi_l1_suspend_n 685 * @is_selfpowered: true when we are selfpowered 686 * @is_fpga: true when we are using the FPGA board 687 * @needs_fifo_resize: not all users might want fifo resizing, flag it 688 * @pullups_connected: true when Run/Stop bit is set 689 * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes. 690 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround 691 * @start_config_issued: true when StartConfig command has been issued 692 * @three_stage_setup: set if we perform a three phase setup 693 * @disable_scramble_quirk: set if we enable the disable scramble quirk 694 * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk 695 * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk 696 * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk 697 * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk 698 * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk 699 * @lfps_filter_quirk: set if we enable LFPS filter quirk 700 * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk 701 * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy 702 * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy 703 * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk 704 * @tx_de_emphasis: Tx de-emphasis value 705 * 0 - -6dB de-emphasis 706 * 1 - -3.5dB de-emphasis 707 * 2 - No de-emphasis 708 * 3 - Reserved 709 * @index: index of _this_ controller 710 * @list: to maintain the list of dwc3 controllers 711 */ 712 struct dwc3 { 713 struct usb_ctrlrequest *ctrl_req; 714 struct dwc3_trb *ep0_trb; 715 void *ep0_bounce; 716 void *scratchbuf; 717 u8 *setup_buf; 718 dma_addr_t ctrl_req_addr; 719 dma_addr_t ep0_trb_addr; 720 dma_addr_t ep0_bounce_addr; 721 dma_addr_t scratch_addr; 722 struct dwc3_request ep0_usb_req; 723 724 /* device lock */ 725 spinlock_t lock; 726 727 #if defined(__UBOOT__) && defined(CONFIG_DM_USB) 728 struct udevice *dev; 729 #else 730 struct device *dev; 731 #endif 732 733 struct platform_device *xhci; 734 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM]; 735 736 struct dwc3_event_buffer **ev_buffs; 737 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; 738 739 struct usb_gadget gadget; 740 struct usb_gadget_driver *gadget_driver; 741 742 void __iomem *regs; 743 size_t regs_size; 744 745 enum usb_dr_mode dr_mode; 746 747 /* used for suspend/resume */ 748 u32 dcfg; 749 u32 gctl; 750 751 u32 nr_scratch; 752 u32 num_event_buffers; 753 u32 u1u2; 754 u32 maximum_speed; 755 u32 revision; 756 757 #define DWC3_REVISION_173A 0x5533173a 758 #define DWC3_REVISION_175A 0x5533175a 759 #define DWC3_REVISION_180A 0x5533180a 760 #define DWC3_REVISION_183A 0x5533183a 761 #define DWC3_REVISION_185A 0x5533185a 762 #define DWC3_REVISION_187A 0x5533187a 763 #define DWC3_REVISION_188A 0x5533188a 764 #define DWC3_REVISION_190A 0x5533190a 765 #define DWC3_REVISION_194A 0x5533194a 766 #define DWC3_REVISION_200A 0x5533200a 767 #define DWC3_REVISION_202A 0x5533202a 768 #define DWC3_REVISION_210A 0x5533210a 769 #define DWC3_REVISION_220A 0x5533220a 770 #define DWC3_REVISION_230A 0x5533230a 771 #define DWC3_REVISION_240A 0x5533240a 772 #define DWC3_REVISION_250A 0x5533250a 773 #define DWC3_REVISION_260A 0x5533260a 774 #define DWC3_REVISION_270A 0x5533270a 775 #define DWC3_REVISION_280A 0x5533280a 776 777 enum dwc3_ep0_next ep0_next_event; 778 enum dwc3_ep0_state ep0state; 779 enum dwc3_link_state link_state; 780 781 u16 isoch_delay; 782 u16 u2sel; 783 u16 u2pel; 784 u8 u1sel; 785 u8 u1pel; 786 787 u8 speed; 788 789 u8 num_out_eps; 790 u8 num_in_eps; 791 792 void *mem; 793 794 struct dwc3_hwparams hwparams; 795 struct dentry *root; 796 struct debugfs_regset32 *regset; 797 798 u8 test_mode; 799 u8 test_mode_nr; 800 u8 lpm_nyet_threshold; 801 u8 hird_threshold; 802 803 unsigned delayed_status:1; 804 unsigned ep0_bounced:1; 805 unsigned ep0_expect_in:1; 806 unsigned has_hibernation:1; 807 unsigned has_lpm_erratum:1; 808 unsigned is_utmi_l1_suspend:1; 809 unsigned is_selfpowered:1; 810 unsigned is_fpga:1; 811 unsigned needs_fifo_resize:1; 812 unsigned pullups_connected:1; 813 unsigned resize_fifos:1; 814 unsigned setup_packet_pending:1; 815 unsigned start_config_issued:1; 816 unsigned three_stage_setup:1; 817 818 unsigned disable_scramble_quirk:1; 819 unsigned u2exit_lfps_quirk:1; 820 unsigned u2ss_inp3_quirk:1; 821 unsigned req_p1p2p3_quirk:1; 822 unsigned del_p1p2p3_quirk:1; 823 unsigned del_phy_power_chg_quirk:1; 824 unsigned lfps_filter_quirk:1; 825 unsigned rx_detect_poll_quirk:1; 826 unsigned dis_u3_susphy_quirk:1; 827 unsigned dis_u2_susphy_quirk:1; 828 829 unsigned tx_de_emphasis_quirk:1; 830 unsigned tx_de_emphasis:2; 831 unsigned usb2_phyif_utmi_width:5; 832 int index; 833 struct list_head list; 834 }; 835 836 /* -------------------------------------------------------------------------- */ 837 838 /* -------------------------------------------------------------------------- */ 839 840 struct dwc3_event_type { 841 u32 is_devspec:1; 842 u32 type:7; 843 u32 reserved8_31:24; 844 } __packed; 845 846 #define DWC3_DEPEVT_XFERCOMPLETE 0x01 847 #define DWC3_DEPEVT_XFERINPROGRESS 0x02 848 #define DWC3_DEPEVT_XFERNOTREADY 0x03 849 #define DWC3_DEPEVT_RXTXFIFOEVT 0x04 850 #define DWC3_DEPEVT_STREAMEVT 0x06 851 #define DWC3_DEPEVT_EPCMDCMPLT 0x07 852 853 /** 854 * dwc3_ep_event_string - returns event name 855 * @event: then event code 856 */ 857 static inline const char *dwc3_ep_event_string(u8 event) 858 { 859 switch (event) { 860 case DWC3_DEPEVT_XFERCOMPLETE: 861 return "Transfer Complete"; 862 case DWC3_DEPEVT_XFERINPROGRESS: 863 return "Transfer In-Progress"; 864 case DWC3_DEPEVT_XFERNOTREADY: 865 return "Transfer Not Ready"; 866 case DWC3_DEPEVT_RXTXFIFOEVT: 867 return "FIFO"; 868 case DWC3_DEPEVT_STREAMEVT: 869 return "Stream"; 870 case DWC3_DEPEVT_EPCMDCMPLT: 871 return "Endpoint Command Complete"; 872 } 873 874 return "UNKNOWN"; 875 } 876 877 /** 878 * struct dwc3_event_depvt - Device Endpoint Events 879 * @one_bit: indicates this is an endpoint event (not used) 880 * @endpoint_number: number of the endpoint 881 * @endpoint_event: The event we have: 882 * 0x00 - Reserved 883 * 0x01 - XferComplete 884 * 0x02 - XferInProgress 885 * 0x03 - XferNotReady 886 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) 887 * 0x05 - Reserved 888 * 0x06 - StreamEvt 889 * 0x07 - EPCmdCmplt 890 * @reserved11_10: Reserved, don't use. 891 * @status: Indicates the status of the event. Refer to databook for 892 * more information. 893 * @parameters: Parameters of the current event. Refer to databook for 894 * more information. 895 */ 896 struct dwc3_event_depevt { 897 u32 one_bit:1; 898 u32 endpoint_number:5; 899 u32 endpoint_event:4; 900 u32 reserved11_10:2; 901 u32 status:4; 902 903 /* Within XferNotReady */ 904 #define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3) 905 906 /* Within XferComplete */ 907 #define DEPEVT_STATUS_BUSERR (1 << 0) 908 #define DEPEVT_STATUS_SHORT (1 << 1) 909 #define DEPEVT_STATUS_IOC (1 << 2) 910 #define DEPEVT_STATUS_LST (1 << 3) 911 912 /* Stream event only */ 913 #define DEPEVT_STREAMEVT_FOUND 1 914 #define DEPEVT_STREAMEVT_NOTFOUND 2 915 916 /* Control-only Status */ 917 #define DEPEVT_STATUS_CONTROL_DATA 1 918 #define DEPEVT_STATUS_CONTROL_STATUS 2 919 920 u32 parameters:16; 921 } __packed; 922 923 /** 924 * struct dwc3_event_devt - Device Events 925 * @one_bit: indicates this is a non-endpoint event (not used) 926 * @device_event: indicates it's a device event. Should read as 0x00 927 * @type: indicates the type of device event. 928 * 0 - DisconnEvt 929 * 1 - USBRst 930 * 2 - ConnectDone 931 * 3 - ULStChng 932 * 4 - WkUpEvt 933 * 5 - Reserved 934 * 6 - EOPF 935 * 7 - SOF 936 * 8 - Reserved 937 * 9 - ErrticErr 938 * 10 - CmdCmplt 939 * 11 - EvntOverflow 940 * 12 - VndrDevTstRcved 941 * @reserved15_12: Reserved, not used 942 * @event_info: Information about this event 943 * @reserved31_25: Reserved, not used 944 */ 945 struct dwc3_event_devt { 946 u32 one_bit:1; 947 u32 device_event:7; 948 u32 type:4; 949 u32 reserved15_12:4; 950 u32 event_info:9; 951 u32 reserved31_25:7; 952 } __packed; 953 954 /** 955 * struct dwc3_event_gevt - Other Core Events 956 * @one_bit: indicates this is a non-endpoint event (not used) 957 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. 958 * @phy_port_number: self-explanatory 959 * @reserved31_12: Reserved, not used. 960 */ 961 struct dwc3_event_gevt { 962 u32 one_bit:1; 963 u32 device_event:7; 964 u32 phy_port_number:4; 965 u32 reserved31_12:20; 966 } __packed; 967 968 /** 969 * union dwc3_event - representation of Event Buffer contents 970 * @raw: raw 32-bit event 971 * @type: the type of the event 972 * @depevt: Device Endpoint Event 973 * @devt: Device Event 974 * @gevt: Global Event 975 */ 976 union dwc3_event { 977 u32 raw; 978 struct dwc3_event_type type; 979 struct dwc3_event_depevt depevt; 980 struct dwc3_event_devt devt; 981 struct dwc3_event_gevt gevt; 982 }; 983 984 /** 985 * struct dwc3_gadget_ep_cmd_params - representation of endpoint command 986 * parameters 987 * @param2: third parameter 988 * @param1: second parameter 989 * @param0: first parameter 990 */ 991 struct dwc3_gadget_ep_cmd_params { 992 u32 param2; 993 u32 param1; 994 u32 param0; 995 }; 996 997 /* 998 * DWC3 Features to be used as Driver Data 999 */ 1000 1001 #define DWC3_HAS_PERIPHERAL BIT(0) 1002 #define DWC3_HAS_XHCI BIT(1) 1003 #define DWC3_HAS_OTG BIT(3) 1004 1005 /* prototypes */ 1006 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc); 1007 int dwc3_init(struct dwc3 *dwc); 1008 void dwc3_remove(struct dwc3 *dwc); 1009 1010 #ifdef CONFIG_USB_DWC3_HOST 1011 int dwc3_host_init(struct dwc3 *dwc); 1012 void dwc3_host_exit(struct dwc3 *dwc); 1013 #else 1014 static inline int dwc3_host_init(struct dwc3 *dwc) 1015 { return 0; } 1016 static inline void dwc3_host_exit(struct dwc3 *dwc) 1017 { } 1018 #endif 1019 1020 #ifdef CONFIG_USB_DWC3_GADGET 1021 int dwc3_gadget_init(struct dwc3 *dwc); 1022 void dwc3_gadget_exit(struct dwc3 *dwc); 1023 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode); 1024 int dwc3_gadget_get_link_state(struct dwc3 *dwc); 1025 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state); 1026 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, 1027 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params); 1028 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param); 1029 #else 1030 static inline int dwc3_gadget_init(struct dwc3 *dwc) 1031 { return 0; } 1032 static inline void dwc3_gadget_exit(struct dwc3 *dwc) 1033 { } 1034 static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) 1035 { return 0; } 1036 static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc) 1037 { return 0; } 1038 static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc, 1039 enum dwc3_link_state state) 1040 { return 0; } 1041 1042 static inline int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, 1043 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params) 1044 { return 0; } 1045 static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc, 1046 int cmd, u32 param) 1047 { return 0; } 1048 #endif 1049 1050 #endif /* __DRIVERS_USB_DWC3_CORE_H */ 1051