1 /** 2 * core.h - DesignWare USB3 DRD Core Header 3 * 4 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.h) and ported 10 * to uboot. 11 * 12 * commit 460d098cb6 : usb: dwc3: make HIRD threshold configurable 13 * 14 * SPDX-License-Identifier: GPL-2.0 15 * 16 */ 17 18 #ifndef __DRIVERS_USB_DWC3_CORE_H 19 #define __DRIVERS_USB_DWC3_CORE_H 20 21 #include <linux/ioport.h> 22 23 #include <linux/usb/ch9.h> 24 #include <linux/usb/otg.h> 25 26 #define DWC3_MSG_MAX 500 27 28 /* Global constants */ 29 #define DWC3_EP0_BOUNCE_SIZE 512 30 #define DWC3_ENDPOINTS_NUM 32 31 #define DWC3_XHCI_RESOURCES_NUM 2 32 33 #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */ 34 #define DWC3_EVENT_SIZE 4 /* bytes */ 35 #define DWC3_EVENT_MAX_NUM 64 /* 2 events/endpoint */ 36 #define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM) 37 #define DWC3_EVENT_TYPE_MASK 0xfe 38 39 #define DWC3_EVENT_TYPE_DEV 0 40 #define DWC3_EVENT_TYPE_CARKIT 3 41 #define DWC3_EVENT_TYPE_I2C 4 42 43 #define DWC3_DEVICE_EVENT_DISCONNECT 0 44 #define DWC3_DEVICE_EVENT_RESET 1 45 #define DWC3_DEVICE_EVENT_CONNECT_DONE 2 46 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 47 #define DWC3_DEVICE_EVENT_WAKEUP 4 48 #define DWC3_DEVICE_EVENT_HIBER_REQ 5 49 #define DWC3_DEVICE_EVENT_EOPF 6 50 #define DWC3_DEVICE_EVENT_SOF 7 51 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 52 #define DWC3_DEVICE_EVENT_CMD_CMPL 10 53 #define DWC3_DEVICE_EVENT_OVERFLOW 11 54 55 #define DWC3_GEVNTCOUNT_MASK 0xfffc 56 #define DWC3_GSNPSID_MASK 0xffff0000 57 #define DWC3_GSNPSREV_MASK 0xffff 58 59 /* DWC3 registers memory space boundries */ 60 #define DWC3_XHCI_REGS_START 0x0 61 #define DWC3_XHCI_REGS_END 0x7fff 62 #define DWC3_GLOBALS_REGS_START 0xc100 63 #define DWC3_GLOBALS_REGS_END 0xc6ff 64 #define DWC3_DEVICE_REGS_START 0xc700 65 #define DWC3_DEVICE_REGS_END 0xcbff 66 #define DWC3_OTG_REGS_START 0xcc00 67 #define DWC3_OTG_REGS_END 0xccff 68 69 /* Global Registers */ 70 #define DWC3_GSBUSCFG0 0xc100 71 #define DWC3_GSBUSCFG1 0xc104 72 #define DWC3_GTXTHRCFG 0xc108 73 #define DWC3_GRXTHRCFG 0xc10c 74 #define DWC3_GCTL 0xc110 75 #define DWC3_GEVTEN 0xc114 76 #define DWC3_GSTS 0xc118 77 #define DWC3_GUCTL1 0xc11c 78 #define DWC3_GSNPSID 0xc120 79 #define DWC3_GGPIO 0xc124 80 #define DWC3_GUID 0xc128 81 #define DWC3_GUCTL 0xc12c 82 #define DWC3_GBUSERRADDR0 0xc130 83 #define DWC3_GBUSERRADDR1 0xc134 84 #define DWC3_GPRTBIMAP0 0xc138 85 #define DWC3_GPRTBIMAP1 0xc13c 86 #define DWC3_GHWPARAMS0 0xc140 87 #define DWC3_GHWPARAMS1 0xc144 88 #define DWC3_GHWPARAMS2 0xc148 89 #define DWC3_GHWPARAMS3 0xc14c 90 #define DWC3_GHWPARAMS4 0xc150 91 #define DWC3_GHWPARAMS5 0xc154 92 #define DWC3_GHWPARAMS6 0xc158 93 #define DWC3_GHWPARAMS7 0xc15c 94 #define DWC3_GDBGFIFOSPACE 0xc160 95 #define DWC3_GDBGLTSSM 0xc164 96 #define DWC3_GPRTBIMAP_HS0 0xc180 97 #define DWC3_GPRTBIMAP_HS1 0xc184 98 #define DWC3_GPRTBIMAP_FS0 0xc188 99 #define DWC3_GPRTBIMAP_FS1 0xc18c 100 101 #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04)) 102 #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04)) 103 104 #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04)) 105 106 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04)) 107 108 #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04)) 109 #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04)) 110 111 #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10)) 112 #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10)) 113 #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10)) 114 #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10)) 115 116 #define DWC3_GHWPARAMS8 0xc600 117 118 /* Device Registers */ 119 #define DWC3_DCFG 0xc700 120 #define DWC3_DCTL 0xc704 121 #define DWC3_DEVTEN 0xc708 122 #define DWC3_DSTS 0xc70c 123 #define DWC3_DGCMDPAR 0xc710 124 #define DWC3_DGCMD 0xc714 125 #define DWC3_DALEPENA 0xc720 126 #define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10)) 127 #define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10)) 128 #define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10)) 129 #define DWC3_DEPCMD(n) (0xc80c + (n * 0x10)) 130 131 /* OTG Registers */ 132 #define DWC3_OCFG 0xcc00 133 #define DWC3_OCTL 0xcc04 134 #define DWC3_OEVT 0xcc08 135 #define DWC3_OEVTEN 0xcc0C 136 #define DWC3_OSTS 0xcc10 137 138 /* Bit fields */ 139 140 /* Global Configuration Register */ 141 #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) 142 #define DWC3_GCTL_U2RSTECN (1 << 16) 143 #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) 144 #define DWC3_GCTL_CLK_BUS (0) 145 #define DWC3_GCTL_CLK_PIPE (1) 146 #define DWC3_GCTL_CLK_PIPEHALF (2) 147 #define DWC3_GCTL_CLK_MASK (3) 148 149 #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) 150 #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) 151 #define DWC3_GCTL_PRTCAP_HOST 1 152 #define DWC3_GCTL_PRTCAP_DEVICE 2 153 #define DWC3_GCTL_PRTCAP_OTG 3 154 155 #define DWC3_GCTL_CORESOFTRESET (1 << 11) 156 #define DWC3_GCTL_SOFITPSYNC (1 << 10) 157 #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) 158 #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) 159 #define DWC3_GCTL_DISSCRAMBLE (1 << 3) 160 #define DWC3_GCTL_U2EXIT_LFPS (1 << 2) 161 #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1) 162 #define DWC3_GCTL_DSBLCLKGTNG (1 << 0) 163 164 /* Global USB2 PHY Configuration Register */ 165 #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) 166 #define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8) 167 #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) 168 #define DWC3_GUSB2PHYCFG_PHYIF_8BIT (0 << 3) 169 #define DWC3_GUSB2PHYCFG_PHYIF_16BIT (1 << 3) 170 #define DWC3_GUSB2PHYCFG_PHYIF(n) ((n) << 3) 171 #define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1) 172 #define DWC3_GUSB2PHYCFG_USBTRDTIM(n) ((n) << 10) 173 #define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf) 174 #define USBTRDTIM_UTMI_8_BIT 9 175 #define USBTRDTIM_UTMI_16_BIT 5 176 #define UTMI_PHYIF_16_BIT 1 177 #define UTMI_PHYIF_8_BIT 0 178 179 /* Global USB3 PIPE Control Register */ 180 #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) 181 #define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29) 182 #define DWC3_GUSB3PIPECTL_REQP1P2P3 (1 << 24) 183 #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19) 184 #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7) 185 #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1) 186 #define DWC3_GUSB3PIPECTL_DEPOCHANGE (1 << 18) 187 #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) 188 #define DWC3_GUSB3PIPECTL_LFPSFILT (1 << 9) 189 #define DWC3_GUSB3PIPECTL_RX_DETOPOLL (1 << 8) 190 #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3) 191 #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1) 192 193 /* Global TX Fifo Size Register */ 194 #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) 195 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) 196 197 /* Global Event Size Registers */ 198 #define DWC3_GEVNTSIZ_INTMASK (1 << 31) 199 #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff) 200 201 /* Global HWPARAMS1 Register */ 202 #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) 203 #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 204 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 205 #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2 206 #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24) 207 #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3) 208 209 /* Global HWPARAMS3 Register */ 210 #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3) 211 #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0 212 #define DWC3_GHWPARAMS3_SSPHY_IFC_ENA 1 213 #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2) 214 #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0 215 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1 216 #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2 217 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3 218 #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4) 219 #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0 220 #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1 221 222 /* Global HWPARAMS4 Register */ 223 #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13) 224 #define DWC3_MAX_HIBER_SCRATCHBUFS 15 225 226 /* Global HWPARAMS6 Register */ 227 #define DWC3_GHWPARAMS6_EN_FPGA (1 << 7) 228 229 /* Device Configuration Register */ 230 #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) 231 #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) 232 233 #define DWC3_DCFG_SPEED_MASK (7 << 0) 234 #define DWC3_DCFG_SUPERSPEED (4 << 0) 235 #define DWC3_DCFG_HIGHSPEED (0 << 0) 236 #define DWC3_DCFG_FULLSPEED2 (1 << 0) 237 #define DWC3_DCFG_LOWSPEED (2 << 0) 238 #define DWC3_DCFG_FULLSPEED1 (3 << 0) 239 240 #define DWC3_DCFG_LPM_CAP (1 << 22) 241 242 /* Device Control Register */ 243 #define DWC3_DCTL_RUN_STOP (1 << 31) 244 #define DWC3_DCTL_CSFTRST (1 << 30) 245 #define DWC3_DCTL_LSFTRST (1 << 29) 246 247 #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) 248 #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24) 249 250 #define DWC3_DCTL_APPL1RES (1 << 23) 251 252 /* These apply for core versions 1.87a and earlier */ 253 #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) 254 #define DWC3_DCTL_TRGTULST(n) ((n) << 17) 255 #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2)) 256 #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3)) 257 #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4)) 258 #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5)) 259 #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) 260 261 /* These apply for core versions 1.94a and later */ 262 #define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf) 263 #define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20) 264 265 #define DWC3_DCTL_KEEP_CONNECT (1 << 19) 266 #define DWC3_DCTL_L1_HIBER_EN (1 << 18) 267 #define DWC3_DCTL_CRS (1 << 17) 268 #define DWC3_DCTL_CSS (1 << 16) 269 270 #define DWC3_DCTL_INITU2ENA (1 << 12) 271 #define DWC3_DCTL_ACCEPTU2ENA (1 << 11) 272 #define DWC3_DCTL_INITU1ENA (1 << 10) 273 #define DWC3_DCTL_ACCEPTU1ENA (1 << 9) 274 #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) 275 276 #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) 277 #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) 278 279 #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) 280 #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) 281 #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) 282 #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) 283 #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) 284 #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) 285 #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) 286 287 /* Device Event Enable Register */ 288 #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12) 289 #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11) 290 #define DWC3_DEVTEN_CMDCMPLTEN (1 << 10) 291 #define DWC3_DEVTEN_ERRTICERREN (1 << 9) 292 #define DWC3_DEVTEN_SOFEN (1 << 7) 293 #define DWC3_DEVTEN_EOPFEN (1 << 6) 294 #define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5) 295 #define DWC3_DEVTEN_WKUPEVTEN (1 << 4) 296 #define DWC3_DEVTEN_ULSTCNGEN (1 << 3) 297 #define DWC3_DEVTEN_CONNECTDONEEN (1 << 2) 298 #define DWC3_DEVTEN_USBRSTEN (1 << 1) 299 #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0) 300 301 /* Device Status Register */ 302 #define DWC3_DSTS_DCNRD (1 << 29) 303 304 /* This applies for core versions 1.87a and earlier */ 305 #define DWC3_DSTS_PWRUPREQ (1 << 24) 306 307 /* These apply for core versions 1.94a and later */ 308 #define DWC3_DSTS_RSS (1 << 25) 309 #define DWC3_DSTS_SSS (1 << 24) 310 311 #define DWC3_DSTS_COREIDLE (1 << 23) 312 #define DWC3_DSTS_DEVCTRLHLT (1 << 22) 313 314 #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) 315 #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) 316 317 #define DWC3_DSTS_RXFIFOEMPTY (1 << 17) 318 319 #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3) 320 #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) 321 322 #define DWC3_DSTS_CONNECTSPD (7 << 0) 323 324 #define DWC3_DSTS_SUPERSPEED (4 << 0) 325 #define DWC3_DSTS_HIGHSPEED (0 << 0) 326 #define DWC3_DSTS_FULLSPEED2 (1 << 0) 327 #define DWC3_DSTS_LOWSPEED (2 << 0) 328 #define DWC3_DSTS_FULLSPEED1 (3 << 0) 329 330 /* Device Generic Command Register */ 331 #define DWC3_DGCMD_SET_LMP 0x01 332 #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 333 #define DWC3_DGCMD_XMIT_FUNCTION 0x03 334 335 /* These apply for core versions 1.94a and later */ 336 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04 337 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05 338 339 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 340 #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a 341 #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c 342 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 343 344 #define DWC3_DGCMD_STATUS(n) (((n) >> 15) & 1) 345 #define DWC3_DGCMD_CMDACT (1 << 10) 346 #define DWC3_DGCMD_CMDIOC (1 << 8) 347 348 /* Device Generic Command Parameter Register */ 349 #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0) 350 #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0) 351 #define DWC3_DGCMDPAR_RX_FIFO (0 << 5) 352 #define DWC3_DGCMDPAR_TX_FIFO (1 << 5) 353 #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0) 354 #define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0) 355 356 /* Device Endpoint Command Register */ 357 #define DWC3_DEPCMD_PARAM_SHIFT 16 358 #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT) 359 #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) 360 #define DWC3_DEPCMD_STATUS(x) (((x) >> 15) & 1) 361 #define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11) 362 #define DWC3_DEPCMD_CMDACT (1 << 10) 363 #define DWC3_DEPCMD_CMDIOC (1 << 8) 364 365 #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) 366 #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) 367 #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) 368 #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) 369 #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) 370 #define DWC3_DEPCMD_SETSTALL (0x04 << 0) 371 /* This applies for core versions 1.90a and earlier */ 372 #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) 373 /* This applies for core versions 1.94a and later */ 374 #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0) 375 #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) 376 #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) 377 378 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ 379 #define DWC3_DALEPENA_EP(n) (1 << n) 380 381 #define DWC3_DEPCMD_TYPE_CONTROL 0 382 #define DWC3_DEPCMD_TYPE_ISOC 1 383 #define DWC3_DEPCMD_TYPE_BULK 2 384 #define DWC3_DEPCMD_TYPE_INTR 3 385 386 /* Structures */ 387 388 struct dwc3_trb; 389 390 /** 391 * struct dwc3_event_buffer - Software event buffer representation 392 * @buf: _THE_ buffer 393 * @length: size of this buffer 394 * @lpos: event offset 395 * @count: cache of last read event count register 396 * @flags: flags related to this event buffer 397 * @dma: dma_addr_t 398 * @dwc: pointer to DWC controller 399 */ 400 struct dwc3_event_buffer { 401 void *buf; 402 unsigned length; 403 unsigned int lpos; 404 unsigned int count; 405 unsigned int flags; 406 407 #define DWC3_EVENT_PENDING (1UL << 0) 408 409 dma_addr_t dma; 410 411 struct dwc3 *dwc; 412 }; 413 414 #define DWC3_EP_FLAG_STALLED (1 << 0) 415 #define DWC3_EP_FLAG_WEDGED (1 << 1) 416 417 #define DWC3_EP_DIRECTION_TX true 418 #define DWC3_EP_DIRECTION_RX false 419 420 #define DWC3_TRB_NUM 32 421 #define DWC3_TRB_MASK (DWC3_TRB_NUM - 1) 422 423 /** 424 * struct dwc3_ep - device side endpoint representation 425 * @endpoint: usb endpoint 426 * @request_list: list of requests for this endpoint 427 * @req_queued: list of requests on this ep which have TRBs setup 428 * @trb_pool: array of transaction buffers 429 * @trb_pool_dma: dma address of @trb_pool 430 * @free_slot: next slot which is going to be used 431 * @busy_slot: first slot which is owned by HW 432 * @desc: usb_endpoint_descriptor pointer 433 * @dwc: pointer to DWC controller 434 * @saved_state: ep state saved during hibernation 435 * @flags: endpoint flags (wedged, stalled, ...) 436 * @current_trb: index of current used trb 437 * @number: endpoint number (1 - 15) 438 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK 439 * @resource_index: Resource transfer index 440 * @interval: the interval on which the ISOC transfer is started 441 * @name: a human readable name e.g. ep1out-bulk 442 * @direction: true for TX, false for RX 443 * @stream_capable: true when streams are enabled 444 */ 445 struct dwc3_ep { 446 struct usb_ep endpoint; 447 struct list_head request_list; 448 struct list_head req_queued; 449 450 struct dwc3_trb *trb_pool; 451 dma_addr_t trb_pool_dma; 452 u32 free_slot; 453 u32 busy_slot; 454 const struct usb_ss_ep_comp_descriptor *comp_desc; 455 struct dwc3 *dwc; 456 457 u32 saved_state; 458 unsigned flags; 459 #define DWC3_EP_ENABLED (1 << 0) 460 #define DWC3_EP_STALL (1 << 1) 461 #define DWC3_EP_WEDGE (1 << 2) 462 #define DWC3_EP_BUSY (1 << 4) 463 #define DWC3_EP_PENDING_REQUEST (1 << 5) 464 #define DWC3_EP_MISSED_ISOC (1 << 6) 465 466 /* This last one is specific to EP0 */ 467 #define DWC3_EP0_DIR_IN (1 << 31) 468 469 unsigned current_trb; 470 471 u8 number; 472 u8 type; 473 u8 resource_index; 474 u32 interval; 475 476 char name[20]; 477 478 unsigned direction:1; 479 unsigned stream_capable:1; 480 }; 481 482 enum dwc3_phy { 483 DWC3_PHY_UNKNOWN = 0, 484 DWC3_PHY_USB3, 485 DWC3_PHY_USB2, 486 }; 487 488 enum dwc3_ep0_next { 489 DWC3_EP0_UNKNOWN = 0, 490 DWC3_EP0_COMPLETE, 491 DWC3_EP0_NRDY_DATA, 492 DWC3_EP0_NRDY_STATUS, 493 }; 494 495 enum dwc3_ep0_state { 496 EP0_UNCONNECTED = 0, 497 EP0_SETUP_PHASE, 498 EP0_DATA_PHASE, 499 EP0_STATUS_PHASE, 500 }; 501 502 enum dwc3_link_state { 503 /* In SuperSpeed */ 504 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ 505 DWC3_LINK_STATE_U1 = 0x01, 506 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ 507 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ 508 DWC3_LINK_STATE_SS_DIS = 0x04, 509 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ 510 DWC3_LINK_STATE_SS_INACT = 0x06, 511 DWC3_LINK_STATE_POLL = 0x07, 512 DWC3_LINK_STATE_RECOV = 0x08, 513 DWC3_LINK_STATE_HRESET = 0x09, 514 DWC3_LINK_STATE_CMPLY = 0x0a, 515 DWC3_LINK_STATE_LPBK = 0x0b, 516 DWC3_LINK_STATE_RESET = 0x0e, 517 DWC3_LINK_STATE_RESUME = 0x0f, 518 DWC3_LINK_STATE_MASK = 0x0f, 519 }; 520 521 /* TRB Length, PCM and Status */ 522 #define DWC3_TRB_SIZE_MASK (0x00ffffff) 523 #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK) 524 #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24) 525 #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28) 526 527 #define DWC3_TRBSTS_OK 0 528 #define DWC3_TRBSTS_MISSED_ISOC 1 529 #define DWC3_TRBSTS_SETUP_PENDING 2 530 #define DWC3_TRB_STS_XFER_IN_PROG 4 531 532 /* TRB Control */ 533 #define DWC3_TRB_CTRL_HWO (1 << 0) 534 #define DWC3_TRB_CTRL_LST (1 << 1) 535 #define DWC3_TRB_CTRL_CHN (1 << 2) 536 #define DWC3_TRB_CTRL_CSP (1 << 3) 537 #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) 538 #define DWC3_TRB_CTRL_ISP_IMI (1 << 10) 539 #define DWC3_TRB_CTRL_IOC (1 << 11) 540 #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) 541 542 #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1) 543 #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2) 544 #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3) 545 #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4) 546 #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5) 547 #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6) 548 #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7) 549 #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8) 550 551 /** 552 * struct dwc3_trb - transfer request block (hw format) 553 * @bpl: DW0-3 554 * @bph: DW4-7 555 * @size: DW8-B 556 * @trl: DWC-F 557 */ 558 struct dwc3_trb { 559 u32 bpl; 560 u32 bph; 561 u32 size; 562 u32 ctrl; 563 } __packed; 564 565 /** 566 * dwc3_hwparams - copy of HWPARAMS registers 567 * @hwparams0 - GHWPARAMS0 568 * @hwparams1 - GHWPARAMS1 569 * @hwparams2 - GHWPARAMS2 570 * @hwparams3 - GHWPARAMS3 571 * @hwparams4 - GHWPARAMS4 572 * @hwparams5 - GHWPARAMS5 573 * @hwparams6 - GHWPARAMS6 574 * @hwparams7 - GHWPARAMS7 575 * @hwparams8 - GHWPARAMS8 576 */ 577 struct dwc3_hwparams { 578 u32 hwparams0; 579 u32 hwparams1; 580 u32 hwparams2; 581 u32 hwparams3; 582 u32 hwparams4; 583 u32 hwparams5; 584 u32 hwparams6; 585 u32 hwparams7; 586 u32 hwparams8; 587 }; 588 589 /* HWPARAMS0 */ 590 #define DWC3_MODE(n) ((n) & 0x7) 591 592 #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8) 593 594 /* HWPARAMS1 */ 595 #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) 596 597 /* HWPARAMS3 */ 598 #define DWC3_NUM_IN_EPS_MASK (0x1f << 18) 599 #define DWC3_NUM_EPS_MASK (0x3f << 12) 600 #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \ 601 (DWC3_NUM_EPS_MASK)) >> 12) 602 #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \ 603 (DWC3_NUM_IN_EPS_MASK)) >> 18) 604 605 /* HWPARAMS7 */ 606 #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff) 607 608 struct dwc3_request { 609 struct usb_request request; 610 struct list_head list; 611 struct dwc3_ep *dep; 612 u32 start_slot; 613 614 u8 epnum; 615 struct dwc3_trb *trb; 616 dma_addr_t trb_dma; 617 618 unsigned direction:1; 619 unsigned mapped:1; 620 unsigned queued:1; 621 }; 622 623 /* 624 * struct dwc3_scratchpad_array - hibernation scratchpad array 625 * (format defined by hw) 626 */ 627 struct dwc3_scratchpad_array { 628 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS]; 629 }; 630 631 /** 632 * struct dwc3 - representation of our controller 633 * @ctrl_req: usb control request which is used for ep0 634 * @ep0_trb: trb which is used for the ctrl_req 635 * @ep0_bounce: bounce buffer for ep0 636 * @setup_buf: used while precessing STD USB requests 637 * @ctrl_req_addr: dma address of ctrl_req 638 * @ep0_trb: dma address of ep0_trb 639 * @ep0_usb_req: dummy req used while handling STD USB requests 640 * @ep0_bounce_addr: dma address of ep0_bounce 641 * @scratch_addr: dma address of scratchbuf 642 * @lock: for synchronizing 643 * @dev: pointer to our struct device 644 * @xhci: pointer to our xHCI child 645 * @event_buffer_list: a list of event buffers 646 * @gadget: device side representation of the peripheral controller 647 * @gadget_driver: pointer to the gadget driver 648 * @regs: base address for our registers 649 * @regs_size: address space size 650 * @nr_scratch: number of scratch buffers 651 * @num_event_buffers: calculated number of event buffers 652 * @u1u2: only used on revisions <1.83a for workaround 653 * @maximum_speed: maximum speed requested (mainly for testing purposes) 654 * @revision: revision register contents 655 * @dr_mode: requested mode of operation 656 * @dcfg: saved contents of DCFG register 657 * @gctl: saved contents of GCTL register 658 * @isoch_delay: wValue from Set Isochronous Delay request; 659 * @u2sel: parameter from Set SEL request. 660 * @u2pel: parameter from Set SEL request. 661 * @u1sel: parameter from Set SEL request. 662 * @u1pel: parameter from Set SEL request. 663 * @num_out_eps: number of out endpoints 664 * @num_in_eps: number of in endpoints 665 * @ep0_next_event: hold the next expected event 666 * @ep0state: state of endpoint zero 667 * @link_state: link state 668 * @speed: device speed (super, high, full, low) 669 * @mem: points to start of memory which is used for this struct. 670 * @hwparams: copy of hwparams registers 671 * @root: debugfs root folder pointer 672 * @regset: debugfs pointer to regdump file 673 * @test_mode: true when we're entering a USB test mode 674 * @test_mode_nr: test feature selector 675 * @lpm_nyet_threshold: LPM NYET response threshold 676 * @hird_threshold: HIRD threshold 677 * @delayed_status: true when gadget driver asks for delayed status 678 * @ep0_bounced: true when we used bounce buffer 679 * @ep0_expect_in: true when we expect a DATA IN transfer 680 * @has_hibernation: true when dwc3 was configured with Hibernation 681 * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that 682 * there's now way for software to detect this in runtime. 683 * @is_utmi_l1_suspend: the core asserts output signal 684 * 0 - utmi_sleep_n 685 * 1 - utmi_l1_suspend_n 686 * @is_selfpowered: true when we are selfpowered 687 * @is_fpga: true when we are using the FPGA board 688 * @needs_fifo_resize: not all users might want fifo resizing, flag it 689 * @pullups_connected: true when Run/Stop bit is set 690 * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes. 691 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround 692 * @start_config_issued: true when StartConfig command has been issued 693 * @three_stage_setup: set if we perform a three phase setup 694 * @disable_scramble_quirk: set if we enable the disable scramble quirk 695 * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk 696 * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk 697 * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk 698 * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk 699 * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk 700 * @lfps_filter_quirk: set if we enable LFPS filter quirk 701 * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk 702 * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy 703 * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy 704 * @dis_u1u2_quirk: set if we reject transition to U1 or U2 state 705 * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk 706 * @tx_de_emphasis: Tx de-emphasis value 707 * 0 - -6dB de-emphasis 708 * 1 - -3.5dB de-emphasis 709 * 2 - No de-emphasis 710 * 3 - Reserved 711 * @index: index of _this_ controller 712 * @list: to maintain the list of dwc3 controllers 713 */ 714 struct dwc3 { 715 struct usb_ctrlrequest *ctrl_req; 716 struct dwc3_trb *ep0_trb; 717 void *ep0_bounce; 718 void *scratchbuf; 719 u8 *setup_buf; 720 dma_addr_t ctrl_req_addr; 721 dma_addr_t ep0_trb_addr; 722 dma_addr_t ep0_bounce_addr; 723 dma_addr_t scratch_addr; 724 struct dwc3_request ep0_usb_req; 725 726 /* device lock */ 727 spinlock_t lock; 728 729 #if defined(__UBOOT__) && CONFIG_IS_ENABLED(DM_USB) 730 struct udevice *dev; 731 #else 732 struct device *dev; 733 #endif 734 735 struct platform_device *xhci; 736 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM]; 737 738 struct dwc3_event_buffer **ev_buffs; 739 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; 740 741 struct usb_gadget gadget; 742 struct usb_gadget_driver *gadget_driver; 743 744 void __iomem *regs; 745 size_t regs_size; 746 747 enum usb_dr_mode dr_mode; 748 749 /* used for suspend/resume */ 750 u32 dcfg; 751 u32 gctl; 752 753 u32 nr_scratch; 754 u32 num_event_buffers; 755 u32 u1u2; 756 u32 maximum_speed; 757 u32 revision; 758 759 #define DWC3_REVISION_173A 0x5533173a 760 #define DWC3_REVISION_175A 0x5533175a 761 #define DWC3_REVISION_180A 0x5533180a 762 #define DWC3_REVISION_183A 0x5533183a 763 #define DWC3_REVISION_185A 0x5533185a 764 #define DWC3_REVISION_187A 0x5533187a 765 #define DWC3_REVISION_188A 0x5533188a 766 #define DWC3_REVISION_190A 0x5533190a 767 #define DWC3_REVISION_194A 0x5533194a 768 #define DWC3_REVISION_200A 0x5533200a 769 #define DWC3_REVISION_202A 0x5533202a 770 #define DWC3_REVISION_210A 0x5533210a 771 #define DWC3_REVISION_220A 0x5533220a 772 #define DWC3_REVISION_230A 0x5533230a 773 #define DWC3_REVISION_240A 0x5533240a 774 #define DWC3_REVISION_250A 0x5533250a 775 #define DWC3_REVISION_260A 0x5533260a 776 #define DWC3_REVISION_270A 0x5533270a 777 #define DWC3_REVISION_280A 0x5533280a 778 779 enum dwc3_ep0_next ep0_next_event; 780 enum dwc3_ep0_state ep0state; 781 enum dwc3_link_state link_state; 782 783 u16 isoch_delay; 784 u16 u2sel; 785 u16 u2pel; 786 u8 u1sel; 787 u8 u1pel; 788 789 u8 speed; 790 791 u8 num_out_eps; 792 u8 num_in_eps; 793 794 void *mem; 795 796 struct dwc3_hwparams hwparams; 797 struct dentry *root; 798 struct debugfs_regset32 *regset; 799 800 u8 test_mode; 801 u8 test_mode_nr; 802 u8 lpm_nyet_threshold; 803 u8 hird_threshold; 804 805 unsigned delayed_status:1; 806 unsigned ep0_bounced:1; 807 unsigned ep0_expect_in:1; 808 unsigned has_hibernation:1; 809 unsigned has_lpm_erratum:1; 810 unsigned is_utmi_l1_suspend:1; 811 unsigned is_selfpowered:1; 812 unsigned is_fpga:1; 813 unsigned needs_fifo_resize:1; 814 unsigned pullups_connected:1; 815 unsigned resize_fifos:1; 816 unsigned setup_packet_pending:1; 817 unsigned start_config_issued:1; 818 unsigned three_stage_setup:1; 819 820 unsigned disable_scramble_quirk:1; 821 unsigned u2exit_lfps_quirk:1; 822 unsigned u2ss_inp3_quirk:1; 823 unsigned req_p1p2p3_quirk:1; 824 unsigned del_p1p2p3_quirk:1; 825 unsigned del_phy_power_chg_quirk:1; 826 unsigned lfps_filter_quirk:1; 827 unsigned rx_detect_poll_quirk:1; 828 unsigned dis_u3_susphy_quirk:1; 829 unsigned dis_u2_susphy_quirk:1; 830 unsigned dis_u1u2_quirk:1; 831 832 unsigned tx_de_emphasis_quirk:1; 833 unsigned tx_de_emphasis:2; 834 unsigned usb2_phyif_utmi_width:5; 835 int index; 836 struct list_head list; 837 }; 838 839 /* -------------------------------------------------------------------------- */ 840 841 /* -------------------------------------------------------------------------- */ 842 843 struct dwc3_event_type { 844 u32 is_devspec:1; 845 u32 type:7; 846 u32 reserved8_31:24; 847 } __packed; 848 849 #define DWC3_DEPEVT_XFERCOMPLETE 0x01 850 #define DWC3_DEPEVT_XFERINPROGRESS 0x02 851 #define DWC3_DEPEVT_XFERNOTREADY 0x03 852 #define DWC3_DEPEVT_RXTXFIFOEVT 0x04 853 #define DWC3_DEPEVT_STREAMEVT 0x06 854 #define DWC3_DEPEVT_EPCMDCMPLT 0x07 855 856 /** 857 * dwc3_ep_event_string - returns event name 858 * @event: then event code 859 */ 860 static inline const char *dwc3_ep_event_string(u8 event) 861 { 862 switch (event) { 863 case DWC3_DEPEVT_XFERCOMPLETE: 864 return "Transfer Complete"; 865 case DWC3_DEPEVT_XFERINPROGRESS: 866 return "Transfer In-Progress"; 867 case DWC3_DEPEVT_XFERNOTREADY: 868 return "Transfer Not Ready"; 869 case DWC3_DEPEVT_RXTXFIFOEVT: 870 return "FIFO"; 871 case DWC3_DEPEVT_STREAMEVT: 872 return "Stream"; 873 case DWC3_DEPEVT_EPCMDCMPLT: 874 return "Endpoint Command Complete"; 875 } 876 877 return "UNKNOWN"; 878 } 879 880 /** 881 * struct dwc3_event_depvt - Device Endpoint Events 882 * @one_bit: indicates this is an endpoint event (not used) 883 * @endpoint_number: number of the endpoint 884 * @endpoint_event: The event we have: 885 * 0x00 - Reserved 886 * 0x01 - XferComplete 887 * 0x02 - XferInProgress 888 * 0x03 - XferNotReady 889 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) 890 * 0x05 - Reserved 891 * 0x06 - StreamEvt 892 * 0x07 - EPCmdCmplt 893 * @reserved11_10: Reserved, don't use. 894 * @status: Indicates the status of the event. Refer to databook for 895 * more information. 896 * @parameters: Parameters of the current event. Refer to databook for 897 * more information. 898 */ 899 struct dwc3_event_depevt { 900 u32 one_bit:1; 901 u32 endpoint_number:5; 902 u32 endpoint_event:4; 903 u32 reserved11_10:2; 904 u32 status:4; 905 906 /* Within XferNotReady */ 907 #define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3) 908 909 /* Within XferComplete */ 910 #define DEPEVT_STATUS_BUSERR (1 << 0) 911 #define DEPEVT_STATUS_SHORT (1 << 1) 912 #define DEPEVT_STATUS_IOC (1 << 2) 913 #define DEPEVT_STATUS_LST (1 << 3) 914 915 /* Stream event only */ 916 #define DEPEVT_STREAMEVT_FOUND 1 917 #define DEPEVT_STREAMEVT_NOTFOUND 2 918 919 /* Control-only Status */ 920 #define DEPEVT_STATUS_CONTROL_DATA 1 921 #define DEPEVT_STATUS_CONTROL_STATUS 2 922 923 u32 parameters:16; 924 } __packed; 925 926 /** 927 * struct dwc3_event_devt - Device Events 928 * @one_bit: indicates this is a non-endpoint event (not used) 929 * @device_event: indicates it's a device event. Should read as 0x00 930 * @type: indicates the type of device event. 931 * 0 - DisconnEvt 932 * 1 - USBRst 933 * 2 - ConnectDone 934 * 3 - ULStChng 935 * 4 - WkUpEvt 936 * 5 - Reserved 937 * 6 - EOPF 938 * 7 - SOF 939 * 8 - Reserved 940 * 9 - ErrticErr 941 * 10 - CmdCmplt 942 * 11 - EvntOverflow 943 * 12 - VndrDevTstRcved 944 * @reserved15_12: Reserved, not used 945 * @event_info: Information about this event 946 * @reserved31_25: Reserved, not used 947 */ 948 struct dwc3_event_devt { 949 u32 one_bit:1; 950 u32 device_event:7; 951 u32 type:4; 952 u32 reserved15_12:4; 953 u32 event_info:9; 954 u32 reserved31_25:7; 955 } __packed; 956 957 /** 958 * struct dwc3_event_gevt - Other Core Events 959 * @one_bit: indicates this is a non-endpoint event (not used) 960 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. 961 * @phy_port_number: self-explanatory 962 * @reserved31_12: Reserved, not used. 963 */ 964 struct dwc3_event_gevt { 965 u32 one_bit:1; 966 u32 device_event:7; 967 u32 phy_port_number:4; 968 u32 reserved31_12:20; 969 } __packed; 970 971 /** 972 * union dwc3_event - representation of Event Buffer contents 973 * @raw: raw 32-bit event 974 * @type: the type of the event 975 * @depevt: Device Endpoint Event 976 * @devt: Device Event 977 * @gevt: Global Event 978 */ 979 union dwc3_event { 980 u32 raw; 981 struct dwc3_event_type type; 982 struct dwc3_event_depevt depevt; 983 struct dwc3_event_devt devt; 984 struct dwc3_event_gevt gevt; 985 }; 986 987 /** 988 * struct dwc3_gadget_ep_cmd_params - representation of endpoint command 989 * parameters 990 * @param2: third parameter 991 * @param1: second parameter 992 * @param0: first parameter 993 */ 994 struct dwc3_gadget_ep_cmd_params { 995 u32 param2; 996 u32 param1; 997 u32 param0; 998 }; 999 1000 /* 1001 * DWC3 Features to be used as Driver Data 1002 */ 1003 1004 #define DWC3_HAS_PERIPHERAL BIT(0) 1005 #define DWC3_HAS_XHCI BIT(1) 1006 #define DWC3_HAS_OTG BIT(3) 1007 1008 /* prototypes */ 1009 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc); 1010 void dwc3_of_parse(struct dwc3 *dwc); 1011 int dwc3_init(struct dwc3 *dwc); 1012 void dwc3_remove(struct dwc3 *dwc); 1013 1014 static inline int dwc3_host_init(struct dwc3 *dwc) 1015 { return 0; } 1016 static inline void dwc3_host_exit(struct dwc3 *dwc) 1017 { } 1018 1019 #ifdef CONFIG_USB_DWC3_GADGET 1020 int dwc3_gadget_init(struct dwc3 *dwc); 1021 void dwc3_gadget_exit(struct dwc3 *dwc); 1022 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode); 1023 int dwc3_gadget_get_link_state(struct dwc3 *dwc); 1024 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state); 1025 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, 1026 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params); 1027 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param); 1028 #else 1029 static inline int dwc3_gadget_init(struct dwc3 *dwc) 1030 { return 0; } 1031 static inline void dwc3_gadget_exit(struct dwc3 *dwc) 1032 { } 1033 static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) 1034 { return 0; } 1035 static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc) 1036 { return 0; } 1037 static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc, 1038 enum dwc3_link_state state) 1039 { return 0; } 1040 1041 static inline int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, 1042 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params) 1043 { return 0; } 1044 static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc, 1045 int cmd, u32 param) 1046 { return 0; } 1047 #endif 1048 1049 #endif /* __DRIVERS_USB_DWC3_CORE_H */ 1050