1 /** 2 * core.h - DesignWare USB3 DRD Core Header 3 * 4 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.h) and ported 10 * to uboot. 11 * 12 * commit 460d098cb6 : usb: dwc3: make HIRD threshold configurable 13 * 14 * SPDX-License-Identifier: GPL-2.0 15 * 16 */ 17 18 #ifndef __DRIVERS_USB_DWC3_CORE_H 19 #define __DRIVERS_USB_DWC3_CORE_H 20 21 #include <linux/ioport.h> 22 23 #include <linux/usb/ch9.h> 24 #include <linux/usb/otg.h> 25 #include <linux/usb/phy.h> 26 27 #define DWC3_MSG_MAX 500 28 29 /* Global constants */ 30 #define DWC3_EP0_BOUNCE_SIZE 512 31 #define DWC3_ENDPOINTS_NUM 32 32 #define DWC3_XHCI_RESOURCES_NUM 2 33 34 #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */ 35 #define DWC3_EVENT_SIZE 4 /* bytes */ 36 #define DWC3_EVENT_MAX_NUM 64 /* 2 events/endpoint */ 37 #define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM) 38 #define DWC3_EVENT_TYPE_MASK 0xfe 39 40 #define DWC3_EVENT_TYPE_DEV 0 41 #define DWC3_EVENT_TYPE_CARKIT 3 42 #define DWC3_EVENT_TYPE_I2C 4 43 44 #define DWC3_DEVICE_EVENT_DISCONNECT 0 45 #define DWC3_DEVICE_EVENT_RESET 1 46 #define DWC3_DEVICE_EVENT_CONNECT_DONE 2 47 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 48 #define DWC3_DEVICE_EVENT_WAKEUP 4 49 #define DWC3_DEVICE_EVENT_HIBER_REQ 5 50 #define DWC3_DEVICE_EVENT_EOPF 6 51 #define DWC3_DEVICE_EVENT_SOF 7 52 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 53 #define DWC3_DEVICE_EVENT_CMD_CMPL 10 54 #define DWC3_DEVICE_EVENT_OVERFLOW 11 55 56 #define DWC3_GEVNTCOUNT_MASK 0xfffc 57 #define DWC3_GSNPSID_MASK 0xffff0000 58 #define DWC3_GSNPSREV_MASK 0xffff 59 60 /* DWC3 registers memory space boundries */ 61 #define DWC3_XHCI_REGS_START 0x0 62 #define DWC3_XHCI_REGS_END 0x7fff 63 #define DWC3_GLOBALS_REGS_START 0xc100 64 #define DWC3_GLOBALS_REGS_END 0xc6ff 65 #define DWC3_DEVICE_REGS_START 0xc700 66 #define DWC3_DEVICE_REGS_END 0xcbff 67 #define DWC3_OTG_REGS_START 0xcc00 68 #define DWC3_OTG_REGS_END 0xccff 69 70 /* Global Registers */ 71 #define DWC3_GSBUSCFG0 0xc100 72 #define DWC3_GSBUSCFG1 0xc104 73 #define DWC3_GTXTHRCFG 0xc108 74 #define DWC3_GRXTHRCFG 0xc10c 75 #define DWC3_GCTL 0xc110 76 #define DWC3_GEVTEN 0xc114 77 #define DWC3_GSTS 0xc118 78 #define DWC3_GUCTL1 0xc11c 79 #define DWC3_GSNPSID 0xc120 80 #define DWC3_GGPIO 0xc124 81 #define DWC3_GUID 0xc128 82 #define DWC3_GUCTL 0xc12c 83 #define DWC3_GBUSERRADDR0 0xc130 84 #define DWC3_GBUSERRADDR1 0xc134 85 #define DWC3_GPRTBIMAP0 0xc138 86 #define DWC3_GPRTBIMAP1 0xc13c 87 #define DWC3_GHWPARAMS0 0xc140 88 #define DWC3_GHWPARAMS1 0xc144 89 #define DWC3_GHWPARAMS2 0xc148 90 #define DWC3_GHWPARAMS3 0xc14c 91 #define DWC3_GHWPARAMS4 0xc150 92 #define DWC3_GHWPARAMS5 0xc154 93 #define DWC3_GHWPARAMS6 0xc158 94 #define DWC3_GHWPARAMS7 0xc15c 95 #define DWC3_GDBGFIFOSPACE 0xc160 96 #define DWC3_GDBGLTSSM 0xc164 97 #define DWC3_GPRTBIMAP_HS0 0xc180 98 #define DWC3_GPRTBIMAP_HS1 0xc184 99 #define DWC3_GPRTBIMAP_FS0 0xc188 100 #define DWC3_GPRTBIMAP_FS1 0xc18c 101 102 #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04)) 103 #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04)) 104 105 #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04)) 106 107 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04)) 108 109 #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04)) 110 #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04)) 111 112 #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10)) 113 #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10)) 114 #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10)) 115 #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10)) 116 117 #define DWC3_GHWPARAMS8 0xc600 118 119 /* Device Registers */ 120 #define DWC3_DCFG 0xc700 121 #define DWC3_DCTL 0xc704 122 #define DWC3_DEVTEN 0xc708 123 #define DWC3_DSTS 0xc70c 124 #define DWC3_DGCMDPAR 0xc710 125 #define DWC3_DGCMD 0xc714 126 #define DWC3_DALEPENA 0xc720 127 #define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10)) 128 #define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10)) 129 #define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10)) 130 #define DWC3_DEPCMD(n) (0xc80c + (n * 0x10)) 131 132 /* OTG Registers */ 133 #define DWC3_OCFG 0xcc00 134 #define DWC3_OCTL 0xcc04 135 #define DWC3_OEVT 0xcc08 136 #define DWC3_OEVTEN 0xcc0C 137 #define DWC3_OSTS 0xcc10 138 139 /* Bit fields */ 140 141 /* Global Configuration Register */ 142 #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) 143 #define DWC3_GCTL_U2RSTECN (1 << 16) 144 #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) 145 #define DWC3_GCTL_CLK_BUS (0) 146 #define DWC3_GCTL_CLK_PIPE (1) 147 #define DWC3_GCTL_CLK_PIPEHALF (2) 148 #define DWC3_GCTL_CLK_MASK (3) 149 150 #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) 151 #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) 152 #define DWC3_GCTL_PRTCAP_HOST 1 153 #define DWC3_GCTL_PRTCAP_DEVICE 2 154 #define DWC3_GCTL_PRTCAP_OTG 3 155 156 #define DWC3_GCTL_CORESOFTRESET (1 << 11) 157 #define DWC3_GCTL_SOFITPSYNC (1 << 10) 158 #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) 159 #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) 160 #define DWC3_GCTL_DISSCRAMBLE (1 << 3) 161 #define DWC3_GCTL_U2EXIT_LFPS (1 << 2) 162 #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1) 163 #define DWC3_GCTL_DSBLCLKGTNG (1 << 0) 164 165 /* Global USB2 PHY Configuration Register */ 166 #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) 167 #define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS (1 << 30) 168 #define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8) 169 #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) 170 #define DWC3_GUSB2PHYCFG_PHYIF_8BIT (0 << 3) 171 #define DWC3_GUSB2PHYCFG_PHYIF_16BIT (1 << 3) 172 #define DWC3_GUSB2PHYCFG_PHYIF(n) ((n) << 3) 173 #define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1) 174 #define DWC3_GUSB2PHYCFG_USBTRDTIM(n) ((n) << 10) 175 #define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf) 176 #define USBTRDTIM_UTMI_8_BIT 9 177 #define USBTRDTIM_UTMI_16_BIT 5 178 #define UTMI_PHYIF_16_BIT 1 179 #define UTMI_PHYIF_8_BIT 0 180 181 /* Global USB3 PIPE Control Register */ 182 #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) 183 #define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29) 184 #define DWC3_GUSB3PIPECTL_REQP1P2P3 (1 << 24) 185 #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19) 186 #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7) 187 #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1) 188 #define DWC3_GUSB3PIPECTL_DEPOCHANGE (1 << 18) 189 #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) 190 #define DWC3_GUSB3PIPECTL_LFPSFILT (1 << 9) 191 #define DWC3_GUSB3PIPECTL_RX_DETOPOLL (1 << 8) 192 #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3) 193 #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1) 194 195 /* Global TX Fifo Size Register */ 196 #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) 197 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) 198 199 /* Global Event Size Registers */ 200 #define DWC3_GEVNTSIZ_INTMASK (1 << 31) 201 #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff) 202 203 /* Global HWPARAMS1 Register */ 204 #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) 205 #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 206 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 207 #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2 208 #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24) 209 #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3) 210 211 /* Global HWPARAMS3 Register */ 212 #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3) 213 #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0 214 #define DWC3_GHWPARAMS3_SSPHY_IFC_ENA 1 215 #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2) 216 #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0 217 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1 218 #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2 219 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3 220 #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4) 221 #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0 222 #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1 223 224 /* Global HWPARAMS4 Register */ 225 #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13) 226 #define DWC3_MAX_HIBER_SCRATCHBUFS 15 227 228 /* Global HWPARAMS6 Register */ 229 #define DWC3_GHWPARAMS6_EN_FPGA (1 << 7) 230 231 /* Device Configuration Register */ 232 #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) 233 #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) 234 235 #define DWC3_DCFG_SPEED_MASK (7 << 0) 236 #define DWC3_DCFG_SUPERSPEED (4 << 0) 237 #define DWC3_DCFG_HIGHSPEED (0 << 0) 238 #define DWC3_DCFG_FULLSPEED2 (1 << 0) 239 #define DWC3_DCFG_LOWSPEED (2 << 0) 240 #define DWC3_DCFG_FULLSPEED1 (3 << 0) 241 242 #define DWC3_DCFG_LPM_CAP (1 << 22) 243 244 /* Device Control Register */ 245 #define DWC3_DCTL_RUN_STOP (1 << 31) 246 #define DWC3_DCTL_CSFTRST (1 << 30) 247 #define DWC3_DCTL_LSFTRST (1 << 29) 248 249 #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) 250 #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24) 251 252 #define DWC3_DCTL_APPL1RES (1 << 23) 253 254 /* These apply for core versions 1.87a and earlier */ 255 #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) 256 #define DWC3_DCTL_TRGTULST(n) ((n) << 17) 257 #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2)) 258 #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3)) 259 #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4)) 260 #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5)) 261 #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) 262 263 /* These apply for core versions 1.94a and later */ 264 #define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf) 265 #define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20) 266 267 #define DWC3_DCTL_KEEP_CONNECT (1 << 19) 268 #define DWC3_DCTL_L1_HIBER_EN (1 << 18) 269 #define DWC3_DCTL_CRS (1 << 17) 270 #define DWC3_DCTL_CSS (1 << 16) 271 272 #define DWC3_DCTL_INITU2ENA (1 << 12) 273 #define DWC3_DCTL_ACCEPTU2ENA (1 << 11) 274 #define DWC3_DCTL_INITU1ENA (1 << 10) 275 #define DWC3_DCTL_ACCEPTU1ENA (1 << 9) 276 #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) 277 278 #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) 279 #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) 280 281 #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) 282 #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) 283 #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) 284 #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) 285 #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) 286 #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) 287 #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) 288 289 /* Device Event Enable Register */ 290 #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12) 291 #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11) 292 #define DWC3_DEVTEN_CMDCMPLTEN (1 << 10) 293 #define DWC3_DEVTEN_ERRTICERREN (1 << 9) 294 #define DWC3_DEVTEN_SOFEN (1 << 7) 295 #define DWC3_DEVTEN_EOPFEN (1 << 6) 296 #define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5) 297 #define DWC3_DEVTEN_WKUPEVTEN (1 << 4) 298 #define DWC3_DEVTEN_ULSTCNGEN (1 << 3) 299 #define DWC3_DEVTEN_CONNECTDONEEN (1 << 2) 300 #define DWC3_DEVTEN_USBRSTEN (1 << 1) 301 #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0) 302 303 /* Device Status Register */ 304 #define DWC3_DSTS_DCNRD (1 << 29) 305 306 /* This applies for core versions 1.87a and earlier */ 307 #define DWC3_DSTS_PWRUPREQ (1 << 24) 308 309 /* These apply for core versions 1.94a and later */ 310 #define DWC3_DSTS_RSS (1 << 25) 311 #define DWC3_DSTS_SSS (1 << 24) 312 313 #define DWC3_DSTS_COREIDLE (1 << 23) 314 #define DWC3_DSTS_DEVCTRLHLT (1 << 22) 315 316 #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) 317 #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) 318 319 #define DWC3_DSTS_RXFIFOEMPTY (1 << 17) 320 321 #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3) 322 #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) 323 324 #define DWC3_DSTS_CONNECTSPD (7 << 0) 325 326 #define DWC3_DSTS_SUPERSPEED (4 << 0) 327 #define DWC3_DSTS_HIGHSPEED (0 << 0) 328 #define DWC3_DSTS_FULLSPEED2 (1 << 0) 329 #define DWC3_DSTS_LOWSPEED (2 << 0) 330 #define DWC3_DSTS_FULLSPEED1 (3 << 0) 331 332 /* Device Generic Command Register */ 333 #define DWC3_DGCMD_SET_LMP 0x01 334 #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 335 #define DWC3_DGCMD_XMIT_FUNCTION 0x03 336 337 /* These apply for core versions 1.94a and later */ 338 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04 339 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05 340 341 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 342 #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a 343 #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c 344 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 345 346 #define DWC3_DGCMD_STATUS(n) (((n) >> 15) & 1) 347 #define DWC3_DGCMD_CMDACT (1 << 10) 348 #define DWC3_DGCMD_CMDIOC (1 << 8) 349 350 /* Device Generic Command Parameter Register */ 351 #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0) 352 #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0) 353 #define DWC3_DGCMDPAR_RX_FIFO (0 << 5) 354 #define DWC3_DGCMDPAR_TX_FIFO (1 << 5) 355 #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0) 356 #define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0) 357 358 /* Device Endpoint Command Register */ 359 #define DWC3_DEPCMD_PARAM_SHIFT 16 360 #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT) 361 #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) 362 #define DWC3_DEPCMD_STATUS(x) (((x) >> 15) & 1) 363 #define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11) 364 #define DWC3_DEPCMD_CMDACT (1 << 10) 365 #define DWC3_DEPCMD_CMDIOC (1 << 8) 366 367 #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) 368 #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) 369 #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) 370 #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) 371 #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) 372 #define DWC3_DEPCMD_SETSTALL (0x04 << 0) 373 /* This applies for core versions 1.90a and earlier */ 374 #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) 375 /* This applies for core versions 1.94a and later */ 376 #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0) 377 #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) 378 #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) 379 380 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ 381 #define DWC3_DALEPENA_EP(n) (1 << n) 382 383 #define DWC3_DEPCMD_TYPE_CONTROL 0 384 #define DWC3_DEPCMD_TYPE_ISOC 1 385 #define DWC3_DEPCMD_TYPE_BULK 2 386 #define DWC3_DEPCMD_TYPE_INTR 3 387 388 /* Structures */ 389 390 struct dwc3_trb; 391 392 /** 393 * struct dwc3_event_buffer - Software event buffer representation 394 * @buf: _THE_ buffer 395 * @length: size of this buffer 396 * @lpos: event offset 397 * @count: cache of last read event count register 398 * @flags: flags related to this event buffer 399 * @dma: dma_addr_t 400 * @dwc: pointer to DWC controller 401 */ 402 struct dwc3_event_buffer { 403 void *buf; 404 unsigned length; 405 unsigned int lpos; 406 unsigned int count; 407 unsigned int flags; 408 409 #define DWC3_EVENT_PENDING (1UL << 0) 410 411 dma_addr_t dma; 412 413 struct dwc3 *dwc; 414 }; 415 416 #define DWC3_EP_FLAG_STALLED (1 << 0) 417 #define DWC3_EP_FLAG_WEDGED (1 << 1) 418 419 #define DWC3_EP_DIRECTION_TX true 420 #define DWC3_EP_DIRECTION_RX false 421 422 #define DWC3_TRB_NUM 32 423 #define DWC3_TRB_MASK (DWC3_TRB_NUM - 1) 424 425 /** 426 * struct dwc3_ep - device side endpoint representation 427 * @endpoint: usb endpoint 428 * @request_list: list of requests for this endpoint 429 * @req_queued: list of requests on this ep which have TRBs setup 430 * @trb_pool: array of transaction buffers 431 * @trb_pool_dma: dma address of @trb_pool 432 * @free_slot: next slot which is going to be used 433 * @busy_slot: first slot which is owned by HW 434 * @desc: usb_endpoint_descriptor pointer 435 * @dwc: pointer to DWC controller 436 * @saved_state: ep state saved during hibernation 437 * @flags: endpoint flags (wedged, stalled, ...) 438 * @current_trb: index of current used trb 439 * @number: endpoint number (1 - 15) 440 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK 441 * @resource_index: Resource transfer index 442 * @interval: the interval on which the ISOC transfer is started 443 * @name: a human readable name e.g. ep1out-bulk 444 * @direction: true for TX, false for RX 445 * @stream_capable: true when streams are enabled 446 */ 447 struct dwc3_ep { 448 struct usb_ep endpoint; 449 struct list_head request_list; 450 struct list_head req_queued; 451 452 struct dwc3_trb *trb_pool; 453 dma_addr_t trb_pool_dma; 454 u32 free_slot; 455 u32 busy_slot; 456 const struct usb_ss_ep_comp_descriptor *comp_desc; 457 struct dwc3 *dwc; 458 459 u32 saved_state; 460 unsigned flags; 461 #define DWC3_EP_ENABLED (1 << 0) 462 #define DWC3_EP_STALL (1 << 1) 463 #define DWC3_EP_WEDGE (1 << 2) 464 #define DWC3_EP_BUSY (1 << 4) 465 #define DWC3_EP_PENDING_REQUEST (1 << 5) 466 #define DWC3_EP_MISSED_ISOC (1 << 6) 467 468 /* This last one is specific to EP0 */ 469 #define DWC3_EP0_DIR_IN (1 << 31) 470 471 unsigned current_trb; 472 473 u8 number; 474 u8 type; 475 u8 resource_index; 476 u32 interval; 477 478 char name[20]; 479 480 unsigned direction:1; 481 unsigned stream_capable:1; 482 }; 483 484 enum dwc3_phy { 485 DWC3_PHY_UNKNOWN = 0, 486 DWC3_PHY_USB3, 487 DWC3_PHY_USB2, 488 }; 489 490 enum dwc3_ep0_next { 491 DWC3_EP0_UNKNOWN = 0, 492 DWC3_EP0_COMPLETE, 493 DWC3_EP0_NRDY_DATA, 494 DWC3_EP0_NRDY_STATUS, 495 }; 496 497 enum dwc3_ep0_state { 498 EP0_UNCONNECTED = 0, 499 EP0_SETUP_PHASE, 500 EP0_DATA_PHASE, 501 EP0_STATUS_PHASE, 502 }; 503 504 enum dwc3_link_state { 505 /* In SuperSpeed */ 506 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ 507 DWC3_LINK_STATE_U1 = 0x01, 508 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ 509 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ 510 DWC3_LINK_STATE_SS_DIS = 0x04, 511 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ 512 DWC3_LINK_STATE_SS_INACT = 0x06, 513 DWC3_LINK_STATE_POLL = 0x07, 514 DWC3_LINK_STATE_RECOV = 0x08, 515 DWC3_LINK_STATE_HRESET = 0x09, 516 DWC3_LINK_STATE_CMPLY = 0x0a, 517 DWC3_LINK_STATE_LPBK = 0x0b, 518 DWC3_LINK_STATE_RESET = 0x0e, 519 DWC3_LINK_STATE_RESUME = 0x0f, 520 DWC3_LINK_STATE_MASK = 0x0f, 521 }; 522 523 /* TRB Length, PCM and Status */ 524 #define DWC3_TRB_SIZE_MASK (0x00ffffff) 525 #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK) 526 #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24) 527 #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28) 528 529 #define DWC3_TRBSTS_OK 0 530 #define DWC3_TRBSTS_MISSED_ISOC 1 531 #define DWC3_TRBSTS_SETUP_PENDING 2 532 #define DWC3_TRB_STS_XFER_IN_PROG 4 533 534 /* TRB Control */ 535 #define DWC3_TRB_CTRL_HWO (1 << 0) 536 #define DWC3_TRB_CTRL_LST (1 << 1) 537 #define DWC3_TRB_CTRL_CHN (1 << 2) 538 #define DWC3_TRB_CTRL_CSP (1 << 3) 539 #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) 540 #define DWC3_TRB_CTRL_ISP_IMI (1 << 10) 541 #define DWC3_TRB_CTRL_IOC (1 << 11) 542 #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) 543 544 #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1) 545 #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2) 546 #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3) 547 #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4) 548 #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5) 549 #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6) 550 #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7) 551 #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8) 552 553 /** 554 * struct dwc3_trb - transfer request block (hw format) 555 * @bpl: DW0-3 556 * @bph: DW4-7 557 * @size: DW8-B 558 * @trl: DWC-F 559 */ 560 struct dwc3_trb { 561 u32 bpl; 562 u32 bph; 563 u32 size; 564 u32 ctrl; 565 } __packed; 566 567 /** 568 * dwc3_hwparams - copy of HWPARAMS registers 569 * @hwparams0 - GHWPARAMS0 570 * @hwparams1 - GHWPARAMS1 571 * @hwparams2 - GHWPARAMS2 572 * @hwparams3 - GHWPARAMS3 573 * @hwparams4 - GHWPARAMS4 574 * @hwparams5 - GHWPARAMS5 575 * @hwparams6 - GHWPARAMS6 576 * @hwparams7 - GHWPARAMS7 577 * @hwparams8 - GHWPARAMS8 578 */ 579 struct dwc3_hwparams { 580 u32 hwparams0; 581 u32 hwparams1; 582 u32 hwparams2; 583 u32 hwparams3; 584 u32 hwparams4; 585 u32 hwparams5; 586 u32 hwparams6; 587 u32 hwparams7; 588 u32 hwparams8; 589 }; 590 591 /* HWPARAMS0 */ 592 #define DWC3_MODE(n) ((n) & 0x7) 593 594 #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8) 595 596 /* HWPARAMS1 */ 597 #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) 598 599 /* HWPARAMS3 */ 600 #define DWC3_NUM_IN_EPS_MASK (0x1f << 18) 601 #define DWC3_NUM_EPS_MASK (0x3f << 12) 602 #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \ 603 (DWC3_NUM_EPS_MASK)) >> 12) 604 #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \ 605 (DWC3_NUM_IN_EPS_MASK)) >> 18) 606 607 /* HWPARAMS7 */ 608 #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff) 609 610 struct dwc3_request { 611 struct usb_request request; 612 struct list_head list; 613 struct dwc3_ep *dep; 614 u32 start_slot; 615 616 u8 epnum; 617 struct dwc3_trb *trb; 618 dma_addr_t trb_dma; 619 620 unsigned direction:1; 621 unsigned mapped:1; 622 unsigned queued:1; 623 }; 624 625 /* 626 * struct dwc3_scratchpad_array - hibernation scratchpad array 627 * (format defined by hw) 628 */ 629 struct dwc3_scratchpad_array { 630 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS]; 631 }; 632 633 /** 634 * struct dwc3 - representation of our controller 635 * @ctrl_req: usb control request which is used for ep0 636 * @ep0_trb: trb which is used for the ctrl_req 637 * @ep0_bounce: bounce buffer for ep0 638 * @setup_buf: used while precessing STD USB requests 639 * @ctrl_req_addr: dma address of ctrl_req 640 * @ep0_trb: dma address of ep0_trb 641 * @ep0_usb_req: dummy req used while handling STD USB requests 642 * @ep0_bounce_addr: dma address of ep0_bounce 643 * @scratch_addr: dma address of scratchbuf 644 * @lock: for synchronizing 645 * @dev: pointer to our struct device 646 * @xhci: pointer to our xHCI child 647 * @event_buffer_list: a list of event buffers 648 * @gadget: device side representation of the peripheral controller 649 * @gadget_driver: pointer to the gadget driver 650 * @regs: base address for our registers 651 * @regs_size: address space size 652 * @nr_scratch: number of scratch buffers 653 * @num_event_buffers: calculated number of event buffers 654 * @u1u2: only used on revisions <1.83a for workaround 655 * @maximum_speed: maximum speed requested (mainly for testing purposes) 656 * @revision: revision register contents 657 * @dr_mode: requested mode of operation 658 * @hsphy_mode: UTMI phy mode, one of following: 659 * - USBPHY_INTERFACE_MODE_UTMI 660 * - USBPHY_INTERFACE_MODE_UTMIW 661 * @dcfg: saved contents of DCFG register 662 * @gctl: saved contents of GCTL register 663 * @isoch_delay: wValue from Set Isochronous Delay request; 664 * @u2sel: parameter from Set SEL request. 665 * @u2pel: parameter from Set SEL request. 666 * @u1sel: parameter from Set SEL request. 667 * @u1pel: parameter from Set SEL request. 668 * @num_out_eps: number of out endpoints 669 * @num_in_eps: number of in endpoints 670 * @ep0_next_event: hold the next expected event 671 * @ep0state: state of endpoint zero 672 * @link_state: link state 673 * @speed: device speed (super, high, full, low) 674 * @mem: points to start of memory which is used for this struct. 675 * @hwparams: copy of hwparams registers 676 * @root: debugfs root folder pointer 677 * @regset: debugfs pointer to regdump file 678 * @test_mode: true when we're entering a USB test mode 679 * @test_mode_nr: test feature selector 680 * @lpm_nyet_threshold: LPM NYET response threshold 681 * @hird_threshold: HIRD threshold 682 * @delayed_status: true when gadget driver asks for delayed status 683 * @ep0_bounced: true when we used bounce buffer 684 * @ep0_expect_in: true when we expect a DATA IN transfer 685 * @has_hibernation: true when dwc3 was configured with Hibernation 686 * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that 687 * there's now way for software to detect this in runtime. 688 * @is_utmi_l1_suspend: the core asserts output signal 689 * 0 - utmi_sleep_n 690 * 1 - utmi_l1_suspend_n 691 * @is_selfpowered: true when we are selfpowered 692 * @is_fpga: true when we are using the FPGA board 693 * @needs_fifo_resize: not all users might want fifo resizing, flag it 694 * @pullups_connected: true when Run/Stop bit is set 695 * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes. 696 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround 697 * @start_config_issued: true when StartConfig command has been issued 698 * @three_stage_setup: set if we perform a three phase setup 699 * @disable_scramble_quirk: set if we enable the disable scramble quirk 700 * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk 701 * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk 702 * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk 703 * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk 704 * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk 705 * @lfps_filter_quirk: set if we enable LFPS filter quirk 706 * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk 707 * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy 708 * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy 709 * @dis_u1u2_quirk: set if we reject transition to U1 or U2 state 710 * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk 711 * @tx_de_emphasis: Tx de-emphasis value 712 * 0 - -6dB de-emphasis 713 * 1 - -3.5dB de-emphasis 714 * 2 - No de-emphasis 715 * 3 - Reserved 716 * @index: index of _this_ controller 717 * @list: to maintain the list of dwc3 controllers 718 */ 719 struct dwc3 { 720 struct usb_ctrlrequest *ctrl_req; 721 struct dwc3_trb *ep0_trb; 722 void *ep0_bounce; 723 void *scratchbuf; 724 u8 *setup_buf; 725 dma_addr_t ctrl_req_addr; 726 dma_addr_t ep0_trb_addr; 727 dma_addr_t ep0_bounce_addr; 728 dma_addr_t scratch_addr; 729 struct dwc3_request ep0_usb_req; 730 731 /* device lock */ 732 spinlock_t lock; 733 734 #if defined(__UBOOT__) && CONFIG_IS_ENABLED(DM_USB) 735 struct udevice *dev; 736 #else 737 struct device *dev; 738 #endif 739 740 struct platform_device *xhci; 741 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM]; 742 743 struct dwc3_event_buffer **ev_buffs; 744 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; 745 746 struct usb_gadget gadget; 747 struct usb_gadget_driver *gadget_driver; 748 749 void __iomem *regs; 750 size_t regs_size; 751 752 enum usb_dr_mode dr_mode; 753 enum usb_phy_interface hsphy_mode; 754 755 /* used for suspend/resume */ 756 u32 dcfg; 757 u32 gctl; 758 759 u32 nr_scratch; 760 u32 num_event_buffers; 761 u32 u1u2; 762 u32 maximum_speed; 763 u32 revision; 764 765 #define DWC3_REVISION_173A 0x5533173a 766 #define DWC3_REVISION_175A 0x5533175a 767 #define DWC3_REVISION_180A 0x5533180a 768 #define DWC3_REVISION_183A 0x5533183a 769 #define DWC3_REVISION_185A 0x5533185a 770 #define DWC3_REVISION_187A 0x5533187a 771 #define DWC3_REVISION_188A 0x5533188a 772 #define DWC3_REVISION_190A 0x5533190a 773 #define DWC3_REVISION_194A 0x5533194a 774 #define DWC3_REVISION_200A 0x5533200a 775 #define DWC3_REVISION_202A 0x5533202a 776 #define DWC3_REVISION_210A 0x5533210a 777 #define DWC3_REVISION_220A 0x5533220a 778 #define DWC3_REVISION_230A 0x5533230a 779 #define DWC3_REVISION_240A 0x5533240a 780 #define DWC3_REVISION_250A 0x5533250a 781 #define DWC3_REVISION_260A 0x5533260a 782 #define DWC3_REVISION_270A 0x5533270a 783 #define DWC3_REVISION_280A 0x5533280a 784 785 enum dwc3_ep0_next ep0_next_event; 786 enum dwc3_ep0_state ep0state; 787 enum dwc3_link_state link_state; 788 789 u16 isoch_delay; 790 u16 u2sel; 791 u16 u2pel; 792 u8 u1sel; 793 u8 u1pel; 794 795 u8 speed; 796 797 u8 num_out_eps; 798 u8 num_in_eps; 799 800 void *mem; 801 802 struct dwc3_hwparams hwparams; 803 struct dentry *root; 804 struct debugfs_regset32 *regset; 805 806 u8 test_mode; 807 u8 test_mode_nr; 808 u8 lpm_nyet_threshold; 809 u8 hird_threshold; 810 811 unsigned delayed_status:1; 812 unsigned ep0_bounced:1; 813 unsigned ep0_expect_in:1; 814 unsigned has_hibernation:1; 815 unsigned has_lpm_erratum:1; 816 unsigned is_utmi_l1_suspend:1; 817 unsigned is_selfpowered:1; 818 unsigned is_fpga:1; 819 unsigned needs_fifo_resize:1; 820 unsigned pullups_connected:1; 821 unsigned resize_fifos:1; 822 unsigned setup_packet_pending:1; 823 unsigned start_config_issued:1; 824 unsigned three_stage_setup:1; 825 826 unsigned disable_scramble_quirk:1; 827 unsigned u2exit_lfps_quirk:1; 828 unsigned u2ss_inp3_quirk:1; 829 unsigned req_p1p2p3_quirk:1; 830 unsigned del_p1p2p3_quirk:1; 831 unsigned del_phy_power_chg_quirk:1; 832 unsigned lfps_filter_quirk:1; 833 unsigned rx_detect_poll_quirk:1; 834 unsigned dis_u3_susphy_quirk:1; 835 unsigned dis_u2_susphy_quirk:1; 836 unsigned dis_u1u2_quirk:1; 837 unsigned dis_enblslpm_quirk:1; 838 unsigned dis_u2_freeclk_exists_quirk:1; 839 840 unsigned tx_de_emphasis_quirk:1; 841 unsigned tx_de_emphasis:2; 842 unsigned usb2_phyif_utmi_width:5; 843 int index; 844 struct list_head list; 845 }; 846 847 /* -------------------------------------------------------------------------- */ 848 849 /* -------------------------------------------------------------------------- */ 850 851 struct dwc3_event_type { 852 u32 is_devspec:1; 853 u32 type:7; 854 u32 reserved8_31:24; 855 } __packed; 856 857 #define DWC3_DEPEVT_XFERCOMPLETE 0x01 858 #define DWC3_DEPEVT_XFERINPROGRESS 0x02 859 #define DWC3_DEPEVT_XFERNOTREADY 0x03 860 #define DWC3_DEPEVT_RXTXFIFOEVT 0x04 861 #define DWC3_DEPEVT_STREAMEVT 0x06 862 #define DWC3_DEPEVT_EPCMDCMPLT 0x07 863 864 /** 865 * dwc3_ep_event_string - returns event name 866 * @event: then event code 867 */ 868 static inline const char *dwc3_ep_event_string(u8 event) 869 { 870 switch (event) { 871 case DWC3_DEPEVT_XFERCOMPLETE: 872 return "Transfer Complete"; 873 case DWC3_DEPEVT_XFERINPROGRESS: 874 return "Transfer In-Progress"; 875 case DWC3_DEPEVT_XFERNOTREADY: 876 return "Transfer Not Ready"; 877 case DWC3_DEPEVT_RXTXFIFOEVT: 878 return "FIFO"; 879 case DWC3_DEPEVT_STREAMEVT: 880 return "Stream"; 881 case DWC3_DEPEVT_EPCMDCMPLT: 882 return "Endpoint Command Complete"; 883 } 884 885 return "UNKNOWN"; 886 } 887 888 /** 889 * struct dwc3_event_depvt - Device Endpoint Events 890 * @one_bit: indicates this is an endpoint event (not used) 891 * @endpoint_number: number of the endpoint 892 * @endpoint_event: The event we have: 893 * 0x00 - Reserved 894 * 0x01 - XferComplete 895 * 0x02 - XferInProgress 896 * 0x03 - XferNotReady 897 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) 898 * 0x05 - Reserved 899 * 0x06 - StreamEvt 900 * 0x07 - EPCmdCmplt 901 * @reserved11_10: Reserved, don't use. 902 * @status: Indicates the status of the event. Refer to databook for 903 * more information. 904 * @parameters: Parameters of the current event. Refer to databook for 905 * more information. 906 */ 907 struct dwc3_event_depevt { 908 u32 one_bit:1; 909 u32 endpoint_number:5; 910 u32 endpoint_event:4; 911 u32 reserved11_10:2; 912 u32 status:4; 913 914 /* Within XferNotReady */ 915 #define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3) 916 917 /* Within XferComplete */ 918 #define DEPEVT_STATUS_BUSERR (1 << 0) 919 #define DEPEVT_STATUS_SHORT (1 << 1) 920 #define DEPEVT_STATUS_IOC (1 << 2) 921 #define DEPEVT_STATUS_LST (1 << 3) 922 923 /* Stream event only */ 924 #define DEPEVT_STREAMEVT_FOUND 1 925 #define DEPEVT_STREAMEVT_NOTFOUND 2 926 927 /* Control-only Status */ 928 #define DEPEVT_STATUS_CONTROL_DATA 1 929 #define DEPEVT_STATUS_CONTROL_STATUS 2 930 931 u32 parameters:16; 932 } __packed; 933 934 /** 935 * struct dwc3_event_devt - Device Events 936 * @one_bit: indicates this is a non-endpoint event (not used) 937 * @device_event: indicates it's a device event. Should read as 0x00 938 * @type: indicates the type of device event. 939 * 0 - DisconnEvt 940 * 1 - USBRst 941 * 2 - ConnectDone 942 * 3 - ULStChng 943 * 4 - WkUpEvt 944 * 5 - Reserved 945 * 6 - EOPF 946 * 7 - SOF 947 * 8 - Reserved 948 * 9 - ErrticErr 949 * 10 - CmdCmplt 950 * 11 - EvntOverflow 951 * 12 - VndrDevTstRcved 952 * @reserved15_12: Reserved, not used 953 * @event_info: Information about this event 954 * @reserved31_25: Reserved, not used 955 */ 956 struct dwc3_event_devt { 957 u32 one_bit:1; 958 u32 device_event:7; 959 u32 type:4; 960 u32 reserved15_12:4; 961 u32 event_info:9; 962 u32 reserved31_25:7; 963 } __packed; 964 965 /** 966 * struct dwc3_event_gevt - Other Core Events 967 * @one_bit: indicates this is a non-endpoint event (not used) 968 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. 969 * @phy_port_number: self-explanatory 970 * @reserved31_12: Reserved, not used. 971 */ 972 struct dwc3_event_gevt { 973 u32 one_bit:1; 974 u32 device_event:7; 975 u32 phy_port_number:4; 976 u32 reserved31_12:20; 977 } __packed; 978 979 /** 980 * union dwc3_event - representation of Event Buffer contents 981 * @raw: raw 32-bit event 982 * @type: the type of the event 983 * @depevt: Device Endpoint Event 984 * @devt: Device Event 985 * @gevt: Global Event 986 */ 987 union dwc3_event { 988 u32 raw; 989 struct dwc3_event_type type; 990 struct dwc3_event_depevt depevt; 991 struct dwc3_event_devt devt; 992 struct dwc3_event_gevt gevt; 993 }; 994 995 /** 996 * struct dwc3_gadget_ep_cmd_params - representation of endpoint command 997 * parameters 998 * @param2: third parameter 999 * @param1: second parameter 1000 * @param0: first parameter 1001 */ 1002 struct dwc3_gadget_ep_cmd_params { 1003 u32 param2; 1004 u32 param1; 1005 u32 param0; 1006 }; 1007 1008 /* 1009 * DWC3 Features to be used as Driver Data 1010 */ 1011 1012 #define DWC3_HAS_PERIPHERAL BIT(0) 1013 #define DWC3_HAS_XHCI BIT(1) 1014 #define DWC3_HAS_OTG BIT(3) 1015 1016 /* prototypes */ 1017 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc); 1018 void dwc3_of_parse(struct dwc3 *dwc); 1019 int dwc3_init(struct dwc3 *dwc); 1020 void dwc3_remove(struct dwc3 *dwc); 1021 1022 static inline int dwc3_host_init(struct dwc3 *dwc) 1023 { return 0; } 1024 static inline void dwc3_host_exit(struct dwc3 *dwc) 1025 { } 1026 1027 #ifdef CONFIG_USB_DWC3_GADGET 1028 int dwc3_gadget_init(struct dwc3 *dwc); 1029 void dwc3_gadget_exit(struct dwc3 *dwc); 1030 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode); 1031 int dwc3_gadget_get_link_state(struct dwc3 *dwc); 1032 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state); 1033 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, 1034 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params); 1035 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param); 1036 #else 1037 static inline int dwc3_gadget_init(struct dwc3 *dwc) 1038 { return 0; } 1039 static inline void dwc3_gadget_exit(struct dwc3 *dwc) 1040 { } 1041 static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) 1042 { return 0; } 1043 static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc) 1044 { return 0; } 1045 static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc, 1046 enum dwc3_link_state state) 1047 { return 0; } 1048 1049 static inline int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, 1050 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params) 1051 { return 0; } 1052 static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc, 1053 int cmd, u32 param) 1054 { return 0; } 1055 #endif 1056 1057 #endif /* __DRIVERS_USB_DWC3_CORE_H */ 1058