1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 #ifndef __UFS_H 3 #define __UFS_H 4 5 #include "unipro.h" 6 7 struct udevice; 8 9 #define UFS_CDB_SIZE 16 10 #define UPIU_TRANSACTION_UIC_CMD 0x1F 11 #define UIC_CMD_SIZE (sizeof(u32) * 4) 12 #define RESPONSE_UPIU_SENSE_DATA_LENGTH 18 13 #define UFS_MAX_LUNS 0x7F 14 15 enum { 16 TASK_REQ_UPIU_SIZE_DWORDS = 8, 17 TASK_RSP_UPIU_SIZE_DWORDS = 8, 18 ALIGNED_UPIU_SIZE = 512, 19 }; 20 21 /* UFS device power modes */ 22 enum ufs_dev_pwr_mode { 23 UFS_ACTIVE_PWR_MODE = 1, 24 UFS_SLEEP_PWR_MODE = 2, 25 UFS_POWERDOWN_PWR_MODE = 3, 26 }; 27 28 enum ufs_notify_change_status { 29 PRE_CHANGE, 30 POST_CHANGE, 31 }; 32 33 struct ufs_pa_layer_attr { 34 u32 gear_rx; 35 u32 gear_tx; 36 u32 lane_rx; 37 u32 lane_tx; 38 u32 pwr_rx; 39 u32 pwr_tx; 40 u32 hs_rate; 41 }; 42 43 struct ufs_pwr_mode_info { 44 bool is_valid; 45 struct ufs_pa_layer_attr info; 46 }; 47 48 enum ufs_desc_def_size { 49 QUERY_DESC_DEVICE_DEF_SIZE = 0x40, 50 QUERY_DESC_CONFIGURATION_DEF_SIZE = 0x90, 51 QUERY_DESC_UNIT_DEF_SIZE = 0x23, 52 QUERY_DESC_INTERCONNECT_DEF_SIZE = 0x06, 53 QUERY_DESC_GEOMETRY_DEF_SIZE = 0x48, 54 QUERY_DESC_POWER_DEF_SIZE = 0x62, 55 QUERY_DESC_HEALTH_DEF_SIZE = 0x25, 56 }; 57 58 struct ufs_desc_size { 59 int dev_desc; 60 int pwr_desc; 61 int geom_desc; 62 int interc_desc; 63 int unit_desc; 64 int conf_desc; 65 int hlth_desc; 66 }; 67 68 struct ufs_device_descriptor { 69 uint8_t b_length; 70 uint8_t b_descriptor_idn; 71 uint8_t b_device; 72 uint8_t b_device_class; 73 uint8_t b_device_sub_class; 74 uint8_t b_protocol; 75 uint8_t b_number_lu; 76 uint8_t b_number_wlu; 77 uint8_t b_boot_enable; 78 uint8_t b_descr_access_en; 79 uint8_t b_init_power_mode; 80 uint8_t b_high_priority_lun; 81 uint8_t b_secure_removal_type; 82 uint8_t b_security_lu; 83 uint8_t b_background_ops_term_lat; 84 uint8_t b_init_active_icc_level; 85 uint16_t w_spec_version; 86 uint16_t w_manufacture_date; 87 uint8_t i_manufacturer_name; 88 uint8_t i_product_name; 89 uint8_t i_serial_number; 90 uint8_t i_oem_id; 91 uint16_t w_manufacturer_id; 92 uint8_t b_ud_0base_offset; 93 uint8_t b_ud_config_plength; 94 uint8_t b_device_rtt_cap; 95 uint16_t w_periodic_rtc_update; 96 uint8_t b_ufs_feature_support; 97 uint8_t b_ffu_timeout; 98 uint8_t b_queue_depth; 99 uint16_t w_device_version; 100 uint8_t b_num_secure_wp_area; 101 uint32_t d_psa_max_data_size; 102 uint8_t b_psa_state_timeout; 103 uint8_t i_product_revision_level; 104 uint8_t reserved[5]; /* 5 reserved */ 105 uint8_t reserved_ume[16]; /* 16 reserved */ 106 } __attribute__ ((packed)); 107 108 /* 109 * Request Descriptor Definitions 110 */ 111 112 /* Transfer request command type */ 113 enum { 114 UTP_CMD_TYPE_SCSI = 0x0, 115 UTP_CMD_TYPE_UFS = 0x1, 116 UTP_CMD_TYPE_DEV_MANAGE = 0x2, 117 }; 118 119 /* UTP Transfer Request Command Offset */ 120 #define UPIU_COMMAND_TYPE_OFFSET 28 121 122 /* Offset of the response code in the UPIU header */ 123 #define UPIU_RSP_CODE_OFFSET 8 124 125 /* To accommodate UFS2.0 required Command type */ 126 enum { 127 UTP_CMD_TYPE_UFS_STORAGE = 0x1, 128 }; 129 130 enum { 131 UTP_SCSI_COMMAND = 0x00000000, 132 UTP_NATIVE_UFS_COMMAND = 0x10000000, 133 UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000, 134 UTP_REQ_DESC_INT_CMD = 0x01000000, 135 }; 136 137 /* UTP Transfer Request Data Direction (DD) */ 138 enum { 139 UTP_NO_DATA_TRANSFER = 0x00000000, 140 UTP_HOST_TO_DEVICE = 0x02000000, 141 UTP_DEVICE_TO_HOST = 0x04000000, 142 }; 143 144 /* Overall command status values */ 145 enum { 146 OCS_SUCCESS = 0x0, 147 OCS_INVALID_CMD_TABLE_ATTR = 0x1, 148 OCS_INVALID_PRDT_ATTR = 0x2, 149 OCS_MISMATCH_DATA_BUF_SIZE = 0x3, 150 OCS_MISMATCH_RESP_UPIU_SIZE = 0x4, 151 OCS_PEER_COMM_FAILURE = 0x5, 152 OCS_ABORTED = 0x6, 153 OCS_FATAL_ERROR = 0x7, 154 OCS_INVALID_COMMAND_STATUS = 0x0F, 155 MASK_OCS = 0x0F, 156 }; 157 158 /* The maximum length of the data byte count field in the PRDT is 256KB */ 159 #define PRDT_DATA_BYTE_COUNT_MAX (256 * 1024) 160 /* The granularity of the data byte count field in the PRDT is 32-bit */ 161 #define PRDT_DATA_BYTE_COUNT_PAD 4 162 163 #define GENERAL_UPIU_REQUEST_SIZE (sizeof(struct utp_upiu_req)) 164 #define QUERY_DESC_MAX_SIZE 255 165 #define QUERY_DESC_MIN_SIZE 2 166 #define QUERY_DESC_HDR_SIZE 2 167 #define QUERY_OSF_SIZE (GENERAL_UPIU_REQUEST_SIZE - \ 168 (sizeof(struct utp_upiu_header))) 169 #define RESPONSE_UPIU_SENSE_DATA_LENGTH 18 170 #define UPIU_HEADER_DWORD(byte3, byte2, byte1, byte0)\ 171 cpu_to_be32((byte3 << 24) | (byte2 << 16) |\ 172 (byte1 << 8) | (byte0)) 173 /* 174 * UFS Protocol Information Unit related definitions 175 */ 176 177 /* Task management functions */ 178 enum { 179 UFS_ABORT_TASK = 0x01, 180 UFS_ABORT_TASK_SET = 0x02, 181 UFS_CLEAR_TASK_SET = 0x04, 182 UFS_LOGICAL_RESET = 0x08, 183 UFS_QUERY_TASK = 0x80, 184 UFS_QUERY_TASK_SET = 0x81, 185 }; 186 187 /* UTP UPIU Transaction Codes Initiator to Target */ 188 enum { 189 UPIU_TRANSACTION_NOP_OUT = 0x00, 190 UPIU_TRANSACTION_COMMAND = 0x01, 191 UPIU_TRANSACTION_DATA_OUT = 0x02, 192 UPIU_TRANSACTION_TASK_REQ = 0x04, 193 UPIU_TRANSACTION_QUERY_REQ = 0x16, 194 }; 195 196 /* UTP UPIU Transaction Codes Target to Initiator */ 197 enum { 198 UPIU_TRANSACTION_NOP_IN = 0x20, 199 UPIU_TRANSACTION_RESPONSE = 0x21, 200 UPIU_TRANSACTION_DATA_IN = 0x22, 201 UPIU_TRANSACTION_TASK_RSP = 0x24, 202 UPIU_TRANSACTION_READY_XFER = 0x31, 203 UPIU_TRANSACTION_QUERY_RSP = 0x36, 204 UPIU_TRANSACTION_REJECT_UPIU = 0x3F, 205 }; 206 207 /* UPIU Read/Write flags */ 208 enum { 209 UPIU_CMD_FLAGS_NONE = 0x00, 210 UPIU_CMD_FLAGS_WRITE = 0x20, 211 UPIU_CMD_FLAGS_READ = 0x40, 212 }; 213 214 /* UPIU Task Attributes */ 215 enum { 216 UPIU_TASK_ATTR_SIMPLE = 0x00, 217 UPIU_TASK_ATTR_ORDERED = 0x01, 218 UPIU_TASK_ATTR_HEADQ = 0x02, 219 UPIU_TASK_ATTR_ACA = 0x03, 220 }; 221 222 /* UPIU Query request function */ 223 enum { 224 UPIU_QUERY_FUNC_STANDARD_READ_REQUEST = 0x01, 225 UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST = 0x81, 226 }; 227 228 /* Offset of the response code in the UPIU header */ 229 #define UPIU_RSP_CODE_OFFSET 8 230 231 enum { 232 MASK_SCSI_STATUS = 0xFF, 233 MASK_TASK_RESPONSE = 0xFF00, 234 MASK_RSP_UPIU_RESULT = 0xFFFF, 235 MASK_QUERY_DATA_SEG_LEN = 0xFFFF, 236 MASK_RSP_UPIU_DATA_SEG_LEN = 0xFFFF, 237 MASK_RSP_EXCEPTION_EVENT = 0x10000, 238 MASK_TM_SERVICE_RESP = 0xFF, 239 MASK_TM_FUNC = 0xFF, 240 }; 241 242 /* UTP QUERY Transaction Specific Fields OpCode */ 243 enum query_opcode { 244 UPIU_QUERY_OPCODE_NOP = 0x0, 245 UPIU_QUERY_OPCODE_READ_DESC = 0x1, 246 UPIU_QUERY_OPCODE_WRITE_DESC = 0x2, 247 UPIU_QUERY_OPCODE_READ_ATTR = 0x3, 248 UPIU_QUERY_OPCODE_WRITE_ATTR = 0x4, 249 UPIU_QUERY_OPCODE_READ_FLAG = 0x5, 250 UPIU_QUERY_OPCODE_SET_FLAG = 0x6, 251 UPIU_QUERY_OPCODE_CLEAR_FLAG = 0x7, 252 UPIU_QUERY_OPCODE_TOGGLE_FLAG = 0x8, 253 }; 254 255 /* Query response result code */ 256 enum { 257 QUERY_RESULT_SUCCESS = 0x00, 258 QUERY_RESULT_NOT_READABLE = 0xF6, 259 QUERY_RESULT_NOT_WRITEABLE = 0xF7, 260 QUERY_RESULT_ALREADY_WRITTEN = 0xF8, 261 QUERY_RESULT_INVALID_LENGTH = 0xF9, 262 QUERY_RESULT_INVALID_VALUE = 0xFA, 263 QUERY_RESULT_INVALID_SELECTOR = 0xFB, 264 QUERY_RESULT_INVALID_INDEX = 0xFC, 265 QUERY_RESULT_INVALID_IDN = 0xFD, 266 QUERY_RESULT_INVALID_OPCODE = 0xFE, 267 QUERY_RESULT_GENERAL_FAILURE = 0xFF, 268 }; 269 270 enum { 271 UPIU_COMMAND_SET_TYPE_SCSI = 0x0, 272 UPIU_COMMAND_SET_TYPE_UFS = 0x1, 273 UPIU_COMMAND_SET_TYPE_QUERY = 0x2, 274 }; 275 276 /* Flag idn for Query Requests*/ 277 enum flag_idn { 278 QUERY_FLAG_IDN_FDEVICEINIT = 0x01, 279 QUERY_FLAG_IDN_PERMANENT_WPE = 0x02, 280 QUERY_FLAG_IDN_PWR_ON_WPE = 0x03, 281 QUERY_FLAG_IDN_BKOPS_EN = 0x04, 282 QUERY_FLAG_IDN_LIFE_SPAN_MODE_ENABLE = 0x05, 283 QUERY_FLAG_IDN_PURGE_ENABLE = 0x06, 284 QUERY_FLAG_IDN_RESERVED2 = 0x07, 285 QUERY_FLAG_IDN_FPHYRESOURCEREMOVAL = 0x08, 286 QUERY_FLAG_IDN_BUSY_RTC = 0x09, 287 QUERY_FLAG_IDN_RESERVED3 = 0x0A, 288 QUERY_FLAG_IDN_PERMANENTLY_DISABLE_FW_UPDATE = 0x0B, 289 }; 290 291 /* Attribute idn for Query requests */ 292 enum attr_idn { 293 QUERY_ATTR_IDN_BOOT_LU_EN = 0x00, 294 QUERY_ATTR_IDN_RESERVED = 0x01, 295 QUERY_ATTR_IDN_POWER_MODE = 0x02, 296 QUERY_ATTR_IDN_ACTIVE_ICC_LVL = 0x03, 297 QUERY_ATTR_IDN_OOO_DATA_EN = 0x04, 298 QUERY_ATTR_IDN_BKOPS_STATUS = 0x05, 299 QUERY_ATTR_IDN_PURGE_STATUS = 0x06, 300 QUERY_ATTR_IDN_MAX_DATA_IN = 0x07, 301 QUERY_ATTR_IDN_MAX_DATA_OUT = 0x08, 302 QUERY_ATTR_IDN_DYN_CAP_NEEDED = 0x09, 303 QUERY_ATTR_IDN_REF_CLK_FREQ = 0x0A, 304 QUERY_ATTR_IDN_CONF_DESC_LOCK = 0x0B, 305 QUERY_ATTR_IDN_MAX_NUM_OF_RTT = 0x0C, 306 QUERY_ATTR_IDN_EE_CONTROL = 0x0D, 307 QUERY_ATTR_IDN_EE_STATUS = 0x0E, 308 QUERY_ATTR_IDN_SECONDS_PASSED = 0x0F, 309 QUERY_ATTR_IDN_CNTX_CONF = 0x10, 310 QUERY_ATTR_IDN_CORR_PRG_BLK_NUM = 0x11, 311 QUERY_ATTR_IDN_RESERVED2 = 0x12, 312 QUERY_ATTR_IDN_RESERVED3 = 0x13, 313 QUERY_ATTR_IDN_FFU_STATUS = 0x14, 314 QUERY_ATTR_IDN_PSA_STATE = 0x15, 315 QUERY_ATTR_IDN_PSA_DATA_SIZE = 0x16, 316 }; 317 318 /* Descriptor idn for Query requests */ 319 enum desc_idn { 320 QUERY_DESC_IDN_DEVICE = 0x0, 321 QUERY_DESC_IDN_CONFIGURATION = 0x1, 322 QUERY_DESC_IDN_UNIT = 0x2, 323 QUERY_DESC_IDN_RFU_0 = 0x3, 324 QUERY_DESC_IDN_INTERCONNECT = 0x4, 325 QUERY_DESC_IDN_STRING = 0x5, 326 QUERY_DESC_IDN_RFU_1 = 0x6, 327 QUERY_DESC_IDN_GEOMETRY = 0x7, 328 QUERY_DESC_IDN_POWER = 0x8, 329 QUERY_DESC_IDN_HEALTH = 0x9, 330 QUERY_DESC_IDN_MAX, 331 }; 332 333 enum desc_header_offset { 334 QUERY_DESC_LENGTH_OFFSET = 0x00, 335 QUERY_DESC_DESC_TYPE_OFFSET = 0x01, 336 }; 337 338 struct ufshcd_sg_entry { 339 __le32 base_addr; 340 __le32 upper_addr; 341 __le32 reserved; 342 __le32 size; 343 }; 344 345 #define MAX_BUFF 128 346 /** 347 * struct utp_transfer_cmd_desc - UFS Command Descriptor structure 348 * @command_upiu: Command UPIU Frame address 349 * @response_upiu: Response UPIU Frame address 350 * @prd_table: Physical Region Descriptor 351 */ 352 struct utp_transfer_cmd_desc { 353 u8 command_upiu[ALIGNED_UPIU_SIZE]; 354 u8 response_upiu[ALIGNED_UPIU_SIZE]; 355 struct ufshcd_sg_entry prd_table[MAX_BUFF]; 356 }; 357 358 /** 359 * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD 360 * @dword0: Descriptor Header DW0 361 * @dword1: Descriptor Header DW1 362 * @dword2: Descriptor Header DW2 363 * @dword3: Descriptor Header DW3 364 */ 365 struct request_desc_header { 366 __le32 dword_0; 367 __le32 dword_1; 368 __le32 dword_2; 369 __le32 dword_3; 370 }; 371 372 /** 373 * struct utp_transfer_req_desc - UTRD structure 374 * @header: UTRD header DW-0 to DW-3 375 * @command_desc_base_addr_lo: UCD base address low DW-4 376 * @command_desc_base_addr_hi: UCD base address high DW-5 377 * @response_upiu_length: response UPIU length DW-6 378 * @response_upiu_offset: response UPIU offset DW-6 379 * @prd_table_length: Physical region descriptor length DW-7 380 * @prd_table_offset: Physical region descriptor offset DW-7 381 */ 382 struct utp_transfer_req_desc { 383 /* DW 0-3 */ 384 struct request_desc_header header; 385 386 /* DW 4-5*/ 387 __le32 command_desc_base_addr_lo; 388 __le32 command_desc_base_addr_hi; 389 390 /* DW 6 */ 391 __le16 response_upiu_length; 392 __le16 response_upiu_offset; 393 394 /* DW 7 */ 395 __le16 prd_table_length; 396 __le16 prd_table_offset; 397 }; 398 399 /** 400 * struct utp_upiu_header - UPIU header structure 401 * @dword_0: UPIU header DW-0 402 * @dword_1: UPIU header DW-1 403 * @dword_2: UPIU header DW-2 404 */ 405 struct utp_upiu_header { 406 __be32 dword_0; 407 __be32 dword_1; 408 __be32 dword_2; 409 }; 410 411 /** 412 * struct utp_upiu_query - upiu request buffer structure for 413 * query request. 414 * @opcode: command to perform B-0 415 * @idn: a value that indicates the particular type of data B-1 416 * @index: Index to further identify data B-2 417 * @selector: Index to further identify data B-3 418 * @reserved_osf: spec reserved field B-4,5 419 * @length: number of descriptor bytes to read/write B-6,7 420 * @value: Attribute value to be written DW-5 421 * @reserved: spec reserved DW-6,7 422 */ 423 struct utp_upiu_query { 424 __u8 opcode; 425 __u8 idn; 426 __u8 index; 427 __u8 selector; 428 __be16 reserved_osf; 429 __be16 length; 430 __be32 value; 431 __be32 reserved[2]; 432 }; 433 434 /** 435 * struct utp_upiu_cmd - Command UPIU structure 436 * @data_transfer_len: Data Transfer Length DW-3 437 * @cdb: Command Descriptor Block CDB DW-4 to DW-7 438 */ 439 struct utp_upiu_cmd { 440 __be32 exp_data_transfer_len; 441 u8 cdb[UFS_CDB_SIZE]; 442 }; 443 444 /* 445 * UTMRD structure. 446 */ 447 struct utp_task_req_desc { 448 /* DW 0-3 */ 449 struct request_desc_header header; 450 451 /* DW 4-11 - Task request UPIU structure */ 452 struct utp_upiu_header req_header; 453 __be32 input_param1; 454 __be32 input_param2; 455 __be32 input_param3; 456 __be32 __reserved1[2]; 457 458 /* DW 12-19 - Task Management Response UPIU structure */ 459 struct utp_upiu_header rsp_header; 460 __be32 output_param1; 461 __be32 output_param2; 462 __be32 __reserved2[3]; 463 }; 464 465 /** 466 * struct utp_upiu_req - general upiu request structure 467 * @header:UPIU header structure DW-0 to DW-2 468 * @sc: fields structure for scsi command DW-3 to DW-7 469 * @qr: fields structure for query request DW-3 to DW-7 470 */ 471 struct utp_upiu_req { 472 struct utp_upiu_header header; 473 union { 474 struct utp_upiu_cmd sc; 475 struct utp_upiu_query qr; 476 struct utp_upiu_query tr; 477 /* use utp_upiu_query to host the 4 dwords of uic command */ 478 struct utp_upiu_query uc; 479 }; 480 }; 481 482 /** 483 * struct utp_cmd_rsp - Response UPIU structure 484 * @residual_transfer_count: Residual transfer count DW-3 485 * @reserved: Reserved double words DW-4 to DW-7 486 * @sense_data_len: Sense data length DW-8 U16 487 * @sense_data: Sense data field DW-8 to DW-12 488 */ 489 struct utp_cmd_rsp { 490 __be32 residual_transfer_count; 491 __be32 reserved[4]; 492 __be16 sense_data_len; 493 u8 sense_data[RESPONSE_UPIU_SENSE_DATA_LENGTH]; 494 }; 495 496 /** 497 * struct utp_upiu_rsp - general upiu response structure 498 * @header: UPIU header structure DW-0 to DW-2 499 * @sr: fields structure for scsi command DW-3 to DW-12 500 * @qr: fields structure for query request DW-3 to DW-7 501 */ 502 struct utp_upiu_rsp { 503 struct utp_upiu_header header; 504 union { 505 struct utp_cmd_rsp sr; 506 struct utp_upiu_query qr; 507 }; 508 }; 509 510 #define MAX_MODEL_LEN 16 511 /** 512 * ufs_dev_desc - ufs device details from the device descriptor 513 * 514 * @wmanufacturerid: card details 515 * @model: card model 516 */ 517 struct ufs_dev_desc { 518 u16 wmanufacturerid; 519 char model[MAX_MODEL_LEN + 1]; 520 }; 521 522 /* Device descriptor parameters offsets in bytes*/ 523 enum device_desc_param { 524 DEVICE_DESC_PARAM_LEN = 0x0, 525 DEVICE_DESC_PARAM_TYPE = 0x1, 526 DEVICE_DESC_PARAM_DEVICE_TYPE = 0x2, 527 DEVICE_DESC_PARAM_DEVICE_CLASS = 0x3, 528 DEVICE_DESC_PARAM_DEVICE_SUB_CLASS = 0x4, 529 DEVICE_DESC_PARAM_PRTCL = 0x5, 530 DEVICE_DESC_PARAM_NUM_LU = 0x6, 531 DEVICE_DESC_PARAM_NUM_WLU = 0x7, 532 DEVICE_DESC_PARAM_BOOT_ENBL = 0x8, 533 DEVICE_DESC_PARAM_DESC_ACCSS_ENBL = 0x9, 534 DEVICE_DESC_PARAM_INIT_PWR_MODE = 0xA, 535 DEVICE_DESC_PARAM_HIGH_PR_LUN = 0xB, 536 DEVICE_DESC_PARAM_SEC_RMV_TYPE = 0xC, 537 DEVICE_DESC_PARAM_SEC_LU = 0xD, 538 DEVICE_DESC_PARAM_BKOP_TERM_LT = 0xE, 539 DEVICE_DESC_PARAM_ACTVE_ICC_LVL = 0xF, 540 DEVICE_DESC_PARAM_SPEC_VER = 0x10, 541 DEVICE_DESC_PARAM_MANF_DATE = 0x12, 542 DEVICE_DESC_PARAM_MANF_NAME = 0x14, 543 DEVICE_DESC_PARAM_PRDCT_NAME = 0x15, 544 DEVICE_DESC_PARAM_SN = 0x16, 545 DEVICE_DESC_PARAM_OEM_ID = 0x17, 546 DEVICE_DESC_PARAM_MANF_ID = 0x18, 547 DEVICE_DESC_PARAM_UD_OFFSET = 0x1A, 548 DEVICE_DESC_PARAM_UD_LEN = 0x1B, 549 DEVICE_DESC_PARAM_RTT_CAP = 0x1C, 550 DEVICE_DESC_PARAM_FRQ_RTC = 0x1D, 551 DEVICE_DESC_PARAM_UFS_FEAT = 0x1F, 552 DEVICE_DESC_PARAM_FFU_TMT = 0x20, 553 DEVICE_DESC_PARAM_Q_DPTH = 0x21, 554 DEVICE_DESC_PARAM_DEV_VER = 0x22, 555 DEVICE_DESC_PARAM_NUM_SEC_WPA = 0x24, 556 DEVICE_DESC_PARAM_PSA_MAX_DATA = 0x25, 557 DEVICE_DESC_PARAM_PSA_TMT = 0x29, 558 DEVICE_DESC_PARAM_PRDCT_REV = 0x2A, 559 }; 560 561 struct ufs_hba; 562 563 enum { 564 UFSHCD_MAX_CHANNEL = 0, 565 UFSHCD_MAX_ID = 1, 566 }; 567 568 enum dev_cmd_type { 569 DEV_CMD_TYPE_NOP = 0x0, 570 DEV_CMD_TYPE_QUERY = 0x1, 571 }; 572 573 /** 574 * struct uic_command - UIC command structure 575 * @command: UIC command 576 * @argument1: UIC command argument 1 577 * @argument2: UIC command argument 2 578 * @argument3: UIC command argument 3 579 * @cmd_active: Indicate if UIC command is outstanding 580 * @result: UIC command result 581 * @done: UIC command completion 582 */ 583 struct uic_command { 584 u32 command; 585 u32 argument1; 586 u32 argument2; 587 u32 argument3; 588 int cmd_active; 589 int result; 590 }; 591 592 /* GenSelectorIndex calculation macros for M-PHY attributes */ 593 #define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane) 594 #define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane)) 595 596 #define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\ 597 ((sel) & 0xFFFF)) 598 #define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0) 599 #define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16) 600 #define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF) 601 602 /* Link Status*/ 603 enum link_status { 604 UFSHCD_LINK_IS_DOWN = 1, 605 UFSHCD_LINK_IS_UP = 2, 606 }; 607 608 #define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\ 609 ((sel) & 0xFFFF)) 610 #define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0) 611 #define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16) 612 #define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF) 613 614 /* UIC Commands */ 615 enum uic_cmd_dme { 616 UIC_CMD_DME_GET = 0x01, 617 UIC_CMD_DME_SET = 0x02, 618 UIC_CMD_DME_PEER_GET = 0x03, 619 UIC_CMD_DME_PEER_SET = 0x04, 620 UIC_CMD_DME_POWERON = 0x10, 621 UIC_CMD_DME_POWEROFF = 0x11, 622 UIC_CMD_DME_ENABLE = 0x12, 623 UIC_CMD_DME_RESET = 0x14, 624 UIC_CMD_DME_END_PT_RST = 0x15, 625 UIC_CMD_DME_LINK_STARTUP = 0x16, 626 UIC_CMD_DME_HIBER_ENTER = 0x17, 627 UIC_CMD_DME_HIBER_EXIT = 0x18, 628 UIC_CMD_DME_TEST_MODE = 0x1A, 629 }; 630 631 /* UIC Config result code / Generic error code */ 632 enum { 633 UIC_CMD_RESULT_SUCCESS = 0x00, 634 UIC_CMD_RESULT_INVALID_ATTR = 0x01, 635 UIC_CMD_RESULT_FAILURE = 0x01, 636 UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02, 637 UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03, 638 UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04, 639 UIC_CMD_RESULT_BAD_INDEX = 0x05, 640 UIC_CMD_RESULT_LOCKED_ATTR = 0x06, 641 UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07, 642 UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08, 643 UIC_CMD_RESULT_BUSY = 0x09, 644 UIC_CMD_RESULT_DME_FAILURE = 0x0A, 645 }; 646 647 #define MASK_UIC_COMMAND_RESULT 0xFF 648 649 /* Host <-> Device UniPro Link state */ 650 enum uic_link_state { 651 UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */ 652 UIC_LINK_ACTIVE_STATE = 1, /* Link is in Fast/Slow/Sleep state */ 653 UIC_LINK_HIBERN8_STATE = 2, /* Link is in Hibernate state */ 654 }; 655 656 /* UIC command interfaces for DME primitives */ 657 #define DME_LOCAL 0 658 #define DME_PEER 1 659 #define ATTR_SET_NOR 0 /* NORMAL */ 660 #define ATTR_SET_ST 1 /* STATIC */ 661 662 int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, 663 u8 attr_set, u32 mib_val, u8 peer); 664 int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, 665 u32 *mib_val, u8 peer); 666 667 static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel, 668 u32 mib_val) 669 { 670 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, 671 mib_val, DME_LOCAL); 672 } 673 674 static inline int ufshcd_dme_get(struct ufs_hba *hba, 675 u32 attr_sel, u32 *mib_val) 676 { 677 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL); 678 } 679 680 static inline int ufshcd_dme_peer_get(struct ufs_hba *hba, 681 u32 attr_sel, u32 *mib_val) 682 { 683 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER); 684 } 685 686 static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel, 687 u32 mib_val) 688 { 689 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, 690 mib_val, DME_PEER); 691 } 692 693 /** 694 * struct ufs_query_req - parameters for building a query request 695 * @query_func: UPIU header query function 696 * @upiu_req: the query request data 697 */ 698 struct ufs_query_req { 699 u8 query_func; 700 struct utp_upiu_query upiu_req; 701 }; 702 703 /** 704 * struct ufs_query_resp - UPIU QUERY 705 * @response: device response code 706 * @upiu_res: query response data 707 */ 708 struct ufs_query_res { 709 u8 response; 710 struct utp_upiu_query upiu_res; 711 }; 712 713 /** 714 * struct ufs_query - holds relevant data structures for query request 715 * @request: request upiu and function 716 * @descriptor: buffer for sending/receiving descriptor 717 * @response: response upiu and response 718 */ 719 struct ufs_query { 720 struct ufs_query_req request; 721 u8 *descriptor; 722 struct ufs_query_res response; 723 }; 724 725 /** 726 * struct ufs_dev_cmd - all assosiated fields with device management commands 727 * @type: device management command type - Query, NOP OUT 728 * @tag_wq: wait queue until free command slot is available 729 */ 730 struct ufs_dev_cmd { 731 enum dev_cmd_type type; 732 struct ufs_query query; 733 }; 734 735 struct ufs_hba_ops { 736 int (*init)(struct ufs_hba *hba); 737 int (*hce_enable_notify)(struct ufs_hba *hba, 738 enum ufs_notify_change_status); 739 int (*link_startup_notify)(struct ufs_hba *hba, 740 enum ufs_notify_change_status); 741 int (*phy_initialization)(struct ufs_hba *hba); 742 }; 743 744 struct ufs_hba { 745 struct udevice *dev; 746 void __iomem *mmio_base; 747 struct ufs_hba_ops *ops; 748 struct ufs_desc_size desc_size; 749 u32 capabilities; 750 u32 version; 751 u32 intr_mask; 752 u32 quirks; 753 /* 754 * If UFS host controller is having issue in processing LCC (Line 755 * Control Command) coming from device then enable this quirk. 756 * When this quirk is enabled, host controller driver should disable 757 * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE 758 * attribute of device to 0). 759 */ 760 #define UFSHCD_QUIRK_BROKEN_LCC BIT(0) 761 762 /* 763 * This quirk needs to be enabled if the host controller has 764 * 64-bit addressing supported capability but it doesn't work. 765 */ 766 #define UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS BIT(1) 767 768 /* 769 * This quirk needs to be enabled if the host controller has 770 * auto-hibernate capability but it's FASTAUTO only. 771 */ 772 #define UFSHCD_QUIRK_HIBERN_FASTAUTO BIT(2) 773 774 /* Virtual memory reference */ 775 struct utp_transfer_cmd_desc *ucdl; 776 struct utp_transfer_req_desc *utrdl; 777 /* TODO: Add Task Manegement Support */ 778 struct utp_task_req_desc *utmrdl; 779 780 struct utp_upiu_req *ucd_req_ptr; 781 struct utp_upiu_rsp *ucd_rsp_ptr; 782 struct ufshcd_sg_entry *ucd_prdt_ptr; 783 784 /* Power Mode information */ 785 enum ufs_dev_pwr_mode curr_dev_pwr_mode; 786 struct ufs_pa_layer_attr pwr_info; 787 struct ufs_pwr_mode_info max_pwr_info; 788 789 struct ufs_dev_cmd dev_cmd; 790 struct ufs_device_descriptor *dev_desc; 791 }; 792 793 static inline int ufshcd_ops_init(struct ufs_hba *hba) 794 { 795 if (hba->ops && hba->ops->init) 796 return hba->ops->init(hba); 797 798 return 0; 799 } 800 801 static inline int ufshcd_ops_hce_enable_notify(struct ufs_hba *hba, 802 bool status) 803 { 804 if (hba->ops && hba->ops->hce_enable_notify) 805 return hba->ops->hce_enable_notify(hba, status); 806 807 return 0; 808 } 809 810 static inline int ufshcd_ops_link_startup_notify(struct ufs_hba *hba, 811 bool status) 812 { 813 if (hba->ops && hba->ops->link_startup_notify) 814 return hba->ops->link_startup_notify(hba, status); 815 816 return 0; 817 } 818 819 /* Controller UFSHCI version */ 820 enum { 821 UFSHCI_VERSION_10 = 0x00010000, /* 1.0 */ 822 UFSHCI_VERSION_11 = 0x00010100, /* 1.1 */ 823 UFSHCI_VERSION_20 = 0x00000200, /* 2.0 */ 824 UFSHCI_VERSION_21 = 0x00000210, /* 2.1 */ 825 UFSHCI_VERSION_30 = 0x00000300, /* 3.0 */ 826 UFSHCI_VERSION_31 = 0x00000310, /* 3.1 */ 827 }; 828 829 /* Interrupt disable masks */ 830 enum { 831 /* Interrupt disable mask for UFSHCI v1.0 */ 832 INTERRUPT_MASK_ALL_VER_10 = 0x30FFF, 833 INTERRUPT_MASK_RW_VER_10 = 0x30000, 834 835 /* Interrupt disable mask for UFSHCI v1.1 */ 836 INTERRUPT_MASK_ALL_VER_11 = 0x31FFF, 837 838 /* Interrupt disable mask for UFSHCI v2.1 */ 839 INTERRUPT_MASK_ALL_VER_21 = 0x71FFF, 840 }; 841 842 /* UFSHCI Registers */ 843 enum { 844 REG_CONTROLLER_CAPABILITIES = 0x00, 845 REG_UFS_VERSION = 0x08, 846 REG_CONTROLLER_DEV_ID = 0x10, 847 REG_CONTROLLER_PROD_ID = 0x14, 848 REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18, 849 REG_INTERRUPT_STATUS = 0x20, 850 REG_INTERRUPT_ENABLE = 0x24, 851 REG_CONTROLLER_STATUS = 0x30, 852 REG_CONTROLLER_ENABLE = 0x34, 853 REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38, 854 REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C, 855 REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40, 856 REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44, 857 REG_UIC_ERROR_CODE_DME = 0x48, 858 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C, 859 REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50, 860 REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54, 861 REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58, 862 REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C, 863 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60, 864 REG_UTP_TASK_REQ_LIST_BASE_L = 0x70, 865 REG_UTP_TASK_REQ_LIST_BASE_H = 0x74, 866 REG_UTP_TASK_REQ_DOOR_BELL = 0x78, 867 REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C, 868 REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80, 869 REG_UIC_COMMAND = 0x90, 870 REG_UIC_COMMAND_ARG_1 = 0x94, 871 REG_UIC_COMMAND_ARG_2 = 0x98, 872 REG_UIC_COMMAND_ARG_3 = 0x9C, 873 874 UFSHCI_REG_SPACE_SIZE = 0xA0, 875 876 REG_UFS_CCAP = 0x100, 877 REG_UFS_CRYPTOCAP = 0x104, 878 879 UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400, 880 }; 881 882 /* Controller capability masks */ 883 enum { 884 MASK_TRANSFER_REQUESTS_SLOTS = 0x0000001F, 885 MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000, 886 MASK_AUTO_HIBERN8_SUPPORT = 0x00800000, 887 MASK_64_ADDRESSING_SUPPORT = 0x01000000, 888 MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000, 889 MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000, 890 }; 891 892 /* Interrupt Status 20h */ 893 #define UTP_TRANSFER_REQ_COMPL 0x1 894 #define UIC_DME_END_PT_RESET 0x2 895 #define UIC_ERROR 0x4 896 #define UIC_TEST_MODE 0x8 897 #define UIC_POWER_MODE 0x10 898 #define UIC_HIBERNATE_EXIT 0x20 899 #define UIC_HIBERNATE_ENTER 0x40 900 #define UIC_LINK_LOST 0x80 901 #define UIC_LINK_STARTUP 0x100 902 #define UTP_TASK_REQ_COMPL 0x200 903 #define UIC_COMMAND_COMPL 0x400 904 #define DEVICE_FATAL_ERROR 0x800 905 #define CONTROLLER_FATAL_ERROR 0x10000 906 #define SYSTEM_BUS_FATAL_ERROR 0x20000 907 908 #define UFSHCD_UIC_PWR_MASK (UIC_HIBERNATE_ENTER |\ 909 UIC_HIBERNATE_EXIT |\ 910 UIC_POWER_MODE) 911 912 #define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL | UIC_POWER_MODE) 913 914 #define UFSHCD_ERROR_MASK (UIC_ERROR |\ 915 DEVICE_FATAL_ERROR |\ 916 CONTROLLER_FATAL_ERROR |\ 917 SYSTEM_BUS_FATAL_ERROR) 918 919 #define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\ 920 CONTROLLER_FATAL_ERROR |\ 921 SYSTEM_BUS_FATAL_ERROR) 922 923 /* Host Controller Enable 0x34h */ 924 #define CONTROLLER_ENABLE 0x1 925 #define CONTROLLER_DISABLE 0x0 926 /* HCS - Host Controller Status 30h */ 927 #define DEVICE_PRESENT 0x1 928 #define UTP_TRANSFER_REQ_LIST_READY 0x2 929 #define UTP_TASK_REQ_LIST_READY 0x4 930 #define UIC_COMMAND_READY 0x8 931 #define HOST_ERROR_INDICATOR 0x10 932 #define DEVICE_ERROR_INDICATOR 0x20 933 #define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8) 934 935 #define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY |\ 936 UTP_TASK_REQ_LIST_READY |\ 937 UIC_COMMAND_READY) 938 939 enum { 940 PWR_OK = 0x0, 941 PWR_LOCAL = 0x01, 942 PWR_REMOTE = 0x02, 943 PWR_BUSY = 0x03, 944 PWR_ERROR_CAP = 0x04, 945 PWR_FATAL_ERROR = 0x05, 946 }; 947 948 /* UICCMD - UIC Command */ 949 #define COMMAND_OPCODE_MASK 0xFF 950 #define GEN_SELECTOR_INDEX_MASK 0xFFFF 951 952 #define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16) 953 #define RESET_LEVEL 0xFF 954 955 #define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16) 956 #define CFG_RESULT_CODE_MASK 0xFF 957 #define GENERIC_ERROR_CODE_MASK 0xFF 958 959 #define ufshcd_writel(hba, val, reg) \ 960 writel((val), (hba)->mmio_base + (reg)) 961 #define ufshcd_readl(hba, reg) \ 962 readl((hba)->mmio_base + (reg)) 963 964 /* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */ 965 #define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1 966 967 /* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */ 968 #define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1 969 970 int ufshcd_probe(struct udevice *dev, struct ufs_hba_ops *hba_ops); 971 int ufshcd_dme_reset(struct ufs_hba *hba); 972 int ufshcd_dme_enable(struct ufs_hba *hba); 973 #endif 974