1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 #ifndef __UFS_H 3 #define __UFS_H 4 5 #include "unipro.h" 6 7 struct udevice; 8 9 #define UFS_CDB_SIZE 16 10 #define UPIU_TRANSACTION_UIC_CMD 0x1F 11 #define UIC_CMD_SIZE (sizeof(u32) * 4) 12 #define RESPONSE_UPIU_SENSE_DATA_LENGTH 18 13 14 #ifdef CONFIG_ARCH_ROCKCHIP 15 #define UFS_MAX_LUNS 0x4 16 #else 17 #define UFS_MAX_LUNS 0x7F 18 #endif 19 20 enum { 21 TASK_REQ_UPIU_SIZE_DWORDS = 8, 22 TASK_RSP_UPIU_SIZE_DWORDS = 8, 23 ALIGNED_UPIU_SIZE = 512, 24 }; 25 26 /* UFS device power modes */ 27 enum ufs_dev_pwr_mode { 28 UFS_ACTIVE_PWR_MODE = 1, 29 UFS_SLEEP_PWR_MODE = 2, 30 UFS_POWERDOWN_PWR_MODE = 3, 31 }; 32 33 enum ufs_notify_change_status { 34 PRE_CHANGE, 35 POST_CHANGE, 36 }; 37 38 struct ufs_pa_layer_attr { 39 u32 gear_rx; 40 u32 gear_tx; 41 u32 lane_rx; 42 u32 lane_tx; 43 u32 pwr_rx; 44 u32 pwr_tx; 45 u32 hs_rate; 46 }; 47 48 struct ufs_pwr_mode_info { 49 bool is_valid; 50 struct ufs_pa_layer_attr info; 51 }; 52 53 enum ufs_desc_def_size { 54 QUERY_DESC_DEVICE_DEF_SIZE = 0x40, 55 QUERY_DESC_CONFIGURATION_DEF_SIZE = 0x90, 56 QUERY_DESC_UNIT_DEF_SIZE = 0x23, 57 QUERY_DESC_INTERCONNECT_DEF_SIZE = 0x06, 58 QUERY_DESC_GEOMETRY_DEF_SIZE = 0x48, 59 QUERY_DESC_POWER_DEF_SIZE = 0x62, 60 QUERY_DESC_HEALTH_DEF_SIZE = 0x25, 61 }; 62 63 struct ufs_desc_size { 64 int dev_desc; 65 int pwr_desc; 66 int geom_desc; 67 int interc_desc; 68 int unit_desc; 69 int conf_desc; 70 int hlth_desc; 71 }; 72 73 struct ufs_device_descriptor { 74 uint8_t b_length; 75 uint8_t b_descriptor_idn; 76 uint8_t b_device; 77 uint8_t b_device_class; 78 uint8_t b_device_sub_class; 79 uint8_t b_protocol; 80 uint8_t b_number_lu; 81 uint8_t b_number_wlu; 82 uint8_t b_boot_enable; 83 uint8_t b_descr_access_en; 84 uint8_t b_init_power_mode; 85 uint8_t b_high_priority_lun; 86 uint8_t b_secure_removal_type; 87 uint8_t b_security_lu; 88 uint8_t b_background_ops_term_lat; 89 uint8_t b_init_active_icc_level; 90 uint16_t w_spec_version; 91 uint16_t w_manufacture_date; 92 uint8_t i_manufacturer_name; 93 uint8_t i_product_name; 94 uint8_t i_serial_number; 95 uint8_t i_oem_id; 96 uint16_t w_manufacturer_id; 97 uint8_t b_ud_0base_offset; 98 uint8_t b_ud_config_plength; 99 uint8_t b_device_rtt_cap; 100 uint16_t w_periodic_rtc_update; 101 uint8_t b_ufs_feature_support; 102 uint8_t b_ffu_timeout; 103 uint8_t b_queue_depth; 104 uint16_t w_device_version; 105 uint8_t b_num_secure_wp_area; 106 uint32_t d_psa_max_data_size; 107 uint8_t b_psa_state_timeout; 108 uint8_t i_product_revision_level; 109 uint8_t reserved[5]; /* 5 reserved */ 110 uint8_t reserved_ume[16]; /* 16 reserved */ 111 } __attribute__ ((packed)); 112 113 /* 114 * Request Descriptor Definitions 115 */ 116 117 /* Transfer request command type */ 118 enum { 119 UTP_CMD_TYPE_SCSI = 0x0, 120 UTP_CMD_TYPE_UFS = 0x1, 121 UTP_CMD_TYPE_DEV_MANAGE = 0x2, 122 }; 123 124 /* UTP Transfer Request Command Offset */ 125 #define UPIU_COMMAND_TYPE_OFFSET 28 126 127 /* Offset of the response code in the UPIU header */ 128 #define UPIU_RSP_CODE_OFFSET 8 129 130 /* To accommodate UFS2.0 required Command type */ 131 enum { 132 UTP_CMD_TYPE_UFS_STORAGE = 0x1, 133 }; 134 135 enum { 136 UTP_SCSI_COMMAND = 0x00000000, 137 UTP_NATIVE_UFS_COMMAND = 0x10000000, 138 UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000, 139 UTP_REQ_DESC_INT_CMD = 0x01000000, 140 }; 141 142 /* UTP Transfer Request Data Direction (DD) */ 143 enum { 144 UTP_NO_DATA_TRANSFER = 0x00000000, 145 UTP_HOST_TO_DEVICE = 0x02000000, 146 UTP_DEVICE_TO_HOST = 0x04000000, 147 }; 148 149 /* Overall command status values */ 150 enum { 151 OCS_SUCCESS = 0x0, 152 OCS_INVALID_CMD_TABLE_ATTR = 0x1, 153 OCS_INVALID_PRDT_ATTR = 0x2, 154 OCS_MISMATCH_DATA_BUF_SIZE = 0x3, 155 OCS_MISMATCH_RESP_UPIU_SIZE = 0x4, 156 OCS_PEER_COMM_FAILURE = 0x5, 157 OCS_ABORTED = 0x6, 158 OCS_FATAL_ERROR = 0x7, 159 OCS_INVALID_COMMAND_STATUS = 0x0F, 160 MASK_OCS = 0x0F, 161 }; 162 163 /* The maximum length of the data byte count field in the PRDT is 256KB */ 164 #define PRDT_DATA_BYTE_COUNT_MAX (256 * 1024) 165 /* The granularity of the data byte count field in the PRDT is 32-bit */ 166 #define PRDT_DATA_BYTE_COUNT_PAD 4 167 168 #define GENERAL_UPIU_REQUEST_SIZE (sizeof(struct utp_upiu_req)) 169 #define QUERY_DESC_MAX_SIZE 255 170 #define QUERY_DESC_MIN_SIZE 2 171 #define QUERY_DESC_HDR_SIZE 2 172 #define QUERY_OSF_SIZE (GENERAL_UPIU_REQUEST_SIZE - \ 173 (sizeof(struct utp_upiu_header))) 174 #define RESPONSE_UPIU_SENSE_DATA_LENGTH 18 175 #define UPIU_HEADER_DWORD(byte3, byte2, byte1, byte0)\ 176 cpu_to_be32((byte3 << 24) | (byte2 << 16) |\ 177 (byte1 << 8) | (byte0)) 178 /* 179 * UFS Protocol Information Unit related definitions 180 */ 181 182 /* Task management functions */ 183 enum { 184 UFS_ABORT_TASK = 0x01, 185 UFS_ABORT_TASK_SET = 0x02, 186 UFS_CLEAR_TASK_SET = 0x04, 187 UFS_LOGICAL_RESET = 0x08, 188 UFS_QUERY_TASK = 0x80, 189 UFS_QUERY_TASK_SET = 0x81, 190 }; 191 192 /* UTP UPIU Transaction Codes Initiator to Target */ 193 enum { 194 UPIU_TRANSACTION_NOP_OUT = 0x00, 195 UPIU_TRANSACTION_COMMAND = 0x01, 196 UPIU_TRANSACTION_DATA_OUT = 0x02, 197 UPIU_TRANSACTION_TASK_REQ = 0x04, 198 UPIU_TRANSACTION_QUERY_REQ = 0x16, 199 }; 200 201 /* UTP UPIU Transaction Codes Target to Initiator */ 202 enum { 203 UPIU_TRANSACTION_NOP_IN = 0x20, 204 UPIU_TRANSACTION_RESPONSE = 0x21, 205 UPIU_TRANSACTION_DATA_IN = 0x22, 206 UPIU_TRANSACTION_TASK_RSP = 0x24, 207 UPIU_TRANSACTION_READY_XFER = 0x31, 208 UPIU_TRANSACTION_QUERY_RSP = 0x36, 209 UPIU_TRANSACTION_REJECT_UPIU = 0x3F, 210 }; 211 212 /* UPIU Read/Write flags */ 213 enum { 214 UPIU_CMD_FLAGS_NONE = 0x00, 215 UPIU_CMD_FLAGS_WRITE = 0x20, 216 UPIU_CMD_FLAGS_READ = 0x40, 217 }; 218 219 /* UPIU Task Attributes */ 220 enum { 221 UPIU_TASK_ATTR_SIMPLE = 0x00, 222 UPIU_TASK_ATTR_ORDERED = 0x01, 223 UPIU_TASK_ATTR_HEADQ = 0x02, 224 UPIU_TASK_ATTR_ACA = 0x03, 225 }; 226 227 /* UPIU Query request function */ 228 enum { 229 UPIU_QUERY_FUNC_STANDARD_READ_REQUEST = 0x01, 230 UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST = 0x81, 231 }; 232 233 /* Offset of the response code in the UPIU header */ 234 #define UPIU_RSP_CODE_OFFSET 8 235 236 enum { 237 MASK_SCSI_STATUS = 0xFF, 238 MASK_TASK_RESPONSE = 0xFF00, 239 MASK_RSP_UPIU_RESULT = 0xFFFF, 240 MASK_QUERY_DATA_SEG_LEN = 0xFFFF, 241 MASK_RSP_UPIU_DATA_SEG_LEN = 0xFFFF, 242 MASK_RSP_EXCEPTION_EVENT = 0x10000, 243 MASK_TM_SERVICE_RESP = 0xFF, 244 MASK_TM_FUNC = 0xFF, 245 }; 246 247 /* UTP QUERY Transaction Specific Fields OpCode */ 248 enum query_opcode { 249 UPIU_QUERY_OPCODE_NOP = 0x0, 250 UPIU_QUERY_OPCODE_READ_DESC = 0x1, 251 UPIU_QUERY_OPCODE_WRITE_DESC = 0x2, 252 UPIU_QUERY_OPCODE_READ_ATTR = 0x3, 253 UPIU_QUERY_OPCODE_WRITE_ATTR = 0x4, 254 UPIU_QUERY_OPCODE_READ_FLAG = 0x5, 255 UPIU_QUERY_OPCODE_SET_FLAG = 0x6, 256 UPIU_QUERY_OPCODE_CLEAR_FLAG = 0x7, 257 UPIU_QUERY_OPCODE_TOGGLE_FLAG = 0x8, 258 }; 259 260 /* Query response result code */ 261 enum { 262 QUERY_RESULT_SUCCESS = 0x00, 263 QUERY_RESULT_NOT_READABLE = 0xF6, 264 QUERY_RESULT_NOT_WRITEABLE = 0xF7, 265 QUERY_RESULT_ALREADY_WRITTEN = 0xF8, 266 QUERY_RESULT_INVALID_LENGTH = 0xF9, 267 QUERY_RESULT_INVALID_VALUE = 0xFA, 268 QUERY_RESULT_INVALID_SELECTOR = 0xFB, 269 QUERY_RESULT_INVALID_INDEX = 0xFC, 270 QUERY_RESULT_INVALID_IDN = 0xFD, 271 QUERY_RESULT_INVALID_OPCODE = 0xFE, 272 QUERY_RESULT_GENERAL_FAILURE = 0xFF, 273 }; 274 275 enum { 276 UPIU_COMMAND_SET_TYPE_SCSI = 0x0, 277 UPIU_COMMAND_SET_TYPE_UFS = 0x1, 278 UPIU_COMMAND_SET_TYPE_QUERY = 0x2, 279 }; 280 281 /* Flag idn for Query Requests*/ 282 enum flag_idn { 283 QUERY_FLAG_IDN_FDEVICEINIT = 0x01, 284 QUERY_FLAG_IDN_PERMANENT_WPE = 0x02, 285 QUERY_FLAG_IDN_PWR_ON_WPE = 0x03, 286 QUERY_FLAG_IDN_BKOPS_EN = 0x04, 287 QUERY_FLAG_IDN_LIFE_SPAN_MODE_ENABLE = 0x05, 288 QUERY_FLAG_IDN_PURGE_ENABLE = 0x06, 289 QUERY_FLAG_IDN_RESERVED2 = 0x07, 290 QUERY_FLAG_IDN_FPHYRESOURCEREMOVAL = 0x08, 291 QUERY_FLAG_IDN_BUSY_RTC = 0x09, 292 QUERY_FLAG_IDN_RESERVED3 = 0x0A, 293 QUERY_FLAG_IDN_PERMANENTLY_DISABLE_FW_UPDATE = 0x0B, 294 }; 295 296 /* Attribute idn for Query requests */ 297 enum attr_idn { 298 QUERY_ATTR_IDN_BOOT_LU_EN = 0x00, 299 QUERY_ATTR_IDN_RESERVED = 0x01, 300 QUERY_ATTR_IDN_POWER_MODE = 0x02, 301 QUERY_ATTR_IDN_ACTIVE_ICC_LVL = 0x03, 302 QUERY_ATTR_IDN_OOO_DATA_EN = 0x04, 303 QUERY_ATTR_IDN_BKOPS_STATUS = 0x05, 304 QUERY_ATTR_IDN_PURGE_STATUS = 0x06, 305 QUERY_ATTR_IDN_MAX_DATA_IN = 0x07, 306 QUERY_ATTR_IDN_MAX_DATA_OUT = 0x08, 307 QUERY_ATTR_IDN_DYN_CAP_NEEDED = 0x09, 308 QUERY_ATTR_IDN_REF_CLK_FREQ = 0x0A, 309 QUERY_ATTR_IDN_CONF_DESC_LOCK = 0x0B, 310 QUERY_ATTR_IDN_MAX_NUM_OF_RTT = 0x0C, 311 QUERY_ATTR_IDN_EE_CONTROL = 0x0D, 312 QUERY_ATTR_IDN_EE_STATUS = 0x0E, 313 QUERY_ATTR_IDN_SECONDS_PASSED = 0x0F, 314 QUERY_ATTR_IDN_CNTX_CONF = 0x10, 315 QUERY_ATTR_IDN_CORR_PRG_BLK_NUM = 0x11, 316 QUERY_ATTR_IDN_RESERVED2 = 0x12, 317 QUERY_ATTR_IDN_RESERVED3 = 0x13, 318 QUERY_ATTR_IDN_FFU_STATUS = 0x14, 319 QUERY_ATTR_IDN_PSA_STATE = 0x15, 320 QUERY_ATTR_IDN_PSA_DATA_SIZE = 0x16, 321 }; 322 323 /* Descriptor idn for Query requests */ 324 enum desc_idn { 325 QUERY_DESC_IDN_DEVICE = 0x0, 326 QUERY_DESC_IDN_CONFIGURATION = 0x1, 327 QUERY_DESC_IDN_UNIT = 0x2, 328 QUERY_DESC_IDN_RFU_0 = 0x3, 329 QUERY_DESC_IDN_INTERCONNECT = 0x4, 330 QUERY_DESC_IDN_STRING = 0x5, 331 QUERY_DESC_IDN_RFU_1 = 0x6, 332 QUERY_DESC_IDN_GEOMETRY = 0x7, 333 QUERY_DESC_IDN_POWER = 0x8, 334 QUERY_DESC_IDN_HEALTH = 0x9, 335 QUERY_DESC_IDN_MAX, 336 }; 337 338 enum desc_header_offset { 339 QUERY_DESC_LENGTH_OFFSET = 0x00, 340 QUERY_DESC_DESC_TYPE_OFFSET = 0x01, 341 }; 342 343 struct ufshcd_sg_entry { 344 __le32 base_addr; 345 __le32 upper_addr; 346 __le32 reserved; 347 __le32 size; 348 }; 349 350 #define MAX_BUFF 128 351 /** 352 * struct utp_transfer_cmd_desc - UFS Command Descriptor structure 353 * @command_upiu: Command UPIU Frame address 354 * @response_upiu: Response UPIU Frame address 355 * @prd_table: Physical Region Descriptor 356 */ 357 struct utp_transfer_cmd_desc { 358 u8 command_upiu[ALIGNED_UPIU_SIZE]; 359 u8 response_upiu[ALIGNED_UPIU_SIZE]; 360 struct ufshcd_sg_entry prd_table[MAX_BUFF]; 361 }; 362 363 /** 364 * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD 365 * @dword0: Descriptor Header DW0 366 * @dword1: Descriptor Header DW1 367 * @dword2: Descriptor Header DW2 368 * @dword3: Descriptor Header DW3 369 */ 370 struct request_desc_header { 371 __le32 dword_0; 372 __le32 dword_1; 373 __le32 dword_2; 374 __le32 dword_3; 375 }; 376 377 /** 378 * struct utp_transfer_req_desc - UTRD structure 379 * @header: UTRD header DW-0 to DW-3 380 * @command_desc_base_addr_lo: UCD base address low DW-4 381 * @command_desc_base_addr_hi: UCD base address high DW-5 382 * @response_upiu_length: response UPIU length DW-6 383 * @response_upiu_offset: response UPIU offset DW-6 384 * @prd_table_length: Physical region descriptor length DW-7 385 * @prd_table_offset: Physical region descriptor offset DW-7 386 */ 387 struct utp_transfer_req_desc { 388 /* DW 0-3 */ 389 struct request_desc_header header; 390 391 /* DW 4-5*/ 392 __le32 command_desc_base_addr_lo; 393 __le32 command_desc_base_addr_hi; 394 395 /* DW 6 */ 396 __le16 response_upiu_length; 397 __le16 response_upiu_offset; 398 399 /* DW 7 */ 400 __le16 prd_table_length; 401 __le16 prd_table_offset; 402 }; 403 404 /** 405 * struct utp_upiu_header - UPIU header structure 406 * @dword_0: UPIU header DW-0 407 * @dword_1: UPIU header DW-1 408 * @dword_2: UPIU header DW-2 409 */ 410 struct utp_upiu_header { 411 __be32 dword_0; 412 __be32 dword_1; 413 __be32 dword_2; 414 }; 415 416 /** 417 * struct utp_upiu_query - upiu request buffer structure for 418 * query request. 419 * @opcode: command to perform B-0 420 * @idn: a value that indicates the particular type of data B-1 421 * @index: Index to further identify data B-2 422 * @selector: Index to further identify data B-3 423 * @reserved_osf: spec reserved field B-4,5 424 * @length: number of descriptor bytes to read/write B-6,7 425 * @value: Attribute value to be written DW-5 426 * @reserved: spec reserved DW-6,7 427 */ 428 struct utp_upiu_query { 429 __u8 opcode; 430 __u8 idn; 431 __u8 index; 432 __u8 selector; 433 __be16 reserved_osf; 434 __be16 length; 435 __be32 value; 436 __be32 reserved[2]; 437 }; 438 439 /** 440 * struct utp_upiu_cmd - Command UPIU structure 441 * @data_transfer_len: Data Transfer Length DW-3 442 * @cdb: Command Descriptor Block CDB DW-4 to DW-7 443 */ 444 struct utp_upiu_cmd { 445 __be32 exp_data_transfer_len; 446 u8 cdb[UFS_CDB_SIZE]; 447 }; 448 449 /* 450 * UTMRD structure. 451 */ 452 struct utp_task_req_desc { 453 /* DW 0-3 */ 454 struct request_desc_header header; 455 456 /* DW 4-11 - Task request UPIU structure */ 457 struct utp_upiu_header req_header; 458 __be32 input_param1; 459 __be32 input_param2; 460 __be32 input_param3; 461 __be32 __reserved1[2]; 462 463 /* DW 12-19 - Task Management Response UPIU structure */ 464 struct utp_upiu_header rsp_header; 465 __be32 output_param1; 466 __be32 output_param2; 467 __be32 __reserved2[3]; 468 }; 469 470 /** 471 * struct utp_upiu_req - general upiu request structure 472 * @header:UPIU header structure DW-0 to DW-2 473 * @sc: fields structure for scsi command DW-3 to DW-7 474 * @qr: fields structure for query request DW-3 to DW-7 475 */ 476 struct utp_upiu_req { 477 struct utp_upiu_header header; 478 union { 479 struct utp_upiu_cmd sc; 480 struct utp_upiu_query qr; 481 struct utp_upiu_query tr; 482 /* use utp_upiu_query to host the 4 dwords of uic command */ 483 struct utp_upiu_query uc; 484 }; 485 }; 486 487 /** 488 * struct utp_cmd_rsp - Response UPIU structure 489 * @residual_transfer_count: Residual transfer count DW-3 490 * @reserved: Reserved double words DW-4 to DW-7 491 * @sense_data_len: Sense data length DW-8 U16 492 * @sense_data: Sense data field DW-8 to DW-12 493 */ 494 struct utp_cmd_rsp { 495 __be32 residual_transfer_count; 496 __be32 reserved[4]; 497 __be16 sense_data_len; 498 u8 sense_data[RESPONSE_UPIU_SENSE_DATA_LENGTH]; 499 }; 500 501 /** 502 * struct utp_upiu_rsp - general upiu response structure 503 * @header: UPIU header structure DW-0 to DW-2 504 * @sr: fields structure for scsi command DW-3 to DW-12 505 * @qr: fields structure for query request DW-3 to DW-7 506 */ 507 struct utp_upiu_rsp { 508 struct utp_upiu_header header; 509 union { 510 struct utp_cmd_rsp sr; 511 struct utp_upiu_query qr; 512 }; 513 }; 514 515 #define MAX_MODEL_LEN 16 516 /** 517 * ufs_dev_desc - ufs device details from the device descriptor 518 * 519 * @wmanufacturerid: card details 520 * @model: card model 521 */ 522 struct ufs_dev_desc { 523 u16 wmanufacturerid; 524 char model[MAX_MODEL_LEN + 1]; 525 }; 526 527 /* Device descriptor parameters offsets in bytes*/ 528 enum device_desc_param { 529 DEVICE_DESC_PARAM_LEN = 0x0, 530 DEVICE_DESC_PARAM_TYPE = 0x1, 531 DEVICE_DESC_PARAM_DEVICE_TYPE = 0x2, 532 DEVICE_DESC_PARAM_DEVICE_CLASS = 0x3, 533 DEVICE_DESC_PARAM_DEVICE_SUB_CLASS = 0x4, 534 DEVICE_DESC_PARAM_PRTCL = 0x5, 535 DEVICE_DESC_PARAM_NUM_LU = 0x6, 536 DEVICE_DESC_PARAM_NUM_WLU = 0x7, 537 DEVICE_DESC_PARAM_BOOT_ENBL = 0x8, 538 DEVICE_DESC_PARAM_DESC_ACCSS_ENBL = 0x9, 539 DEVICE_DESC_PARAM_INIT_PWR_MODE = 0xA, 540 DEVICE_DESC_PARAM_HIGH_PR_LUN = 0xB, 541 DEVICE_DESC_PARAM_SEC_RMV_TYPE = 0xC, 542 DEVICE_DESC_PARAM_SEC_LU = 0xD, 543 DEVICE_DESC_PARAM_BKOP_TERM_LT = 0xE, 544 DEVICE_DESC_PARAM_ACTVE_ICC_LVL = 0xF, 545 DEVICE_DESC_PARAM_SPEC_VER = 0x10, 546 DEVICE_DESC_PARAM_MANF_DATE = 0x12, 547 DEVICE_DESC_PARAM_MANF_NAME = 0x14, 548 DEVICE_DESC_PARAM_PRDCT_NAME = 0x15, 549 DEVICE_DESC_PARAM_SN = 0x16, 550 DEVICE_DESC_PARAM_OEM_ID = 0x17, 551 DEVICE_DESC_PARAM_MANF_ID = 0x18, 552 DEVICE_DESC_PARAM_UD_OFFSET = 0x1A, 553 DEVICE_DESC_PARAM_UD_LEN = 0x1B, 554 DEVICE_DESC_PARAM_RTT_CAP = 0x1C, 555 DEVICE_DESC_PARAM_FRQ_RTC = 0x1D, 556 DEVICE_DESC_PARAM_UFS_FEAT = 0x1F, 557 DEVICE_DESC_PARAM_FFU_TMT = 0x20, 558 DEVICE_DESC_PARAM_Q_DPTH = 0x21, 559 DEVICE_DESC_PARAM_DEV_VER = 0x22, 560 DEVICE_DESC_PARAM_NUM_SEC_WPA = 0x24, 561 DEVICE_DESC_PARAM_PSA_MAX_DATA = 0x25, 562 DEVICE_DESC_PARAM_PSA_TMT = 0x29, 563 DEVICE_DESC_PARAM_PRDCT_REV = 0x2A, 564 }; 565 566 struct ufs_hba; 567 568 enum { 569 UFSHCD_MAX_CHANNEL = 0, 570 UFSHCD_MAX_ID = 1, 571 }; 572 573 enum dev_cmd_type { 574 DEV_CMD_TYPE_NOP = 0x0, 575 DEV_CMD_TYPE_QUERY = 0x1, 576 }; 577 578 /** 579 * struct uic_command - UIC command structure 580 * @command: UIC command 581 * @argument1: UIC command argument 1 582 * @argument2: UIC command argument 2 583 * @argument3: UIC command argument 3 584 * @cmd_active: Indicate if UIC command is outstanding 585 * @result: UIC command result 586 * @done: UIC command completion 587 */ 588 struct uic_command { 589 u32 command; 590 u32 argument1; 591 u32 argument2; 592 u32 argument3; 593 int cmd_active; 594 int result; 595 }; 596 597 /* GenSelectorIndex calculation macros for M-PHY attributes */ 598 #define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane) 599 #define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane)) 600 601 #define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\ 602 ((sel) & 0xFFFF)) 603 #define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0) 604 #define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16) 605 #define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF) 606 607 /* Link Status*/ 608 enum link_status { 609 UFSHCD_LINK_IS_DOWN = 1, 610 UFSHCD_LINK_IS_UP = 2, 611 }; 612 613 #define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\ 614 ((sel) & 0xFFFF)) 615 #define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0) 616 #define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16) 617 #define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF) 618 619 /* UIC Commands */ 620 enum uic_cmd_dme { 621 UIC_CMD_DME_GET = 0x01, 622 UIC_CMD_DME_SET = 0x02, 623 UIC_CMD_DME_PEER_GET = 0x03, 624 UIC_CMD_DME_PEER_SET = 0x04, 625 UIC_CMD_DME_POWERON = 0x10, 626 UIC_CMD_DME_POWEROFF = 0x11, 627 UIC_CMD_DME_ENABLE = 0x12, 628 UIC_CMD_DME_RESET = 0x14, 629 UIC_CMD_DME_END_PT_RST = 0x15, 630 UIC_CMD_DME_LINK_STARTUP = 0x16, 631 UIC_CMD_DME_HIBER_ENTER = 0x17, 632 UIC_CMD_DME_HIBER_EXIT = 0x18, 633 UIC_CMD_DME_TEST_MODE = 0x1A, 634 }; 635 636 /* UIC Config result code / Generic error code */ 637 enum { 638 UIC_CMD_RESULT_SUCCESS = 0x00, 639 UIC_CMD_RESULT_INVALID_ATTR = 0x01, 640 UIC_CMD_RESULT_FAILURE = 0x01, 641 UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02, 642 UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03, 643 UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04, 644 UIC_CMD_RESULT_BAD_INDEX = 0x05, 645 UIC_CMD_RESULT_LOCKED_ATTR = 0x06, 646 UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07, 647 UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08, 648 UIC_CMD_RESULT_BUSY = 0x09, 649 UIC_CMD_RESULT_DME_FAILURE = 0x0A, 650 }; 651 652 #define MASK_UIC_COMMAND_RESULT 0xFF 653 654 /* Host <-> Device UniPro Link state */ 655 enum uic_link_state { 656 UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */ 657 UIC_LINK_ACTIVE_STATE = 1, /* Link is in Fast/Slow/Sleep state */ 658 UIC_LINK_HIBERN8_STATE = 2, /* Link is in Hibernate state */ 659 }; 660 661 /* UIC command interfaces for DME primitives */ 662 #define DME_LOCAL 0 663 #define DME_PEER 1 664 #define ATTR_SET_NOR 0 /* NORMAL */ 665 #define ATTR_SET_ST 1 /* STATIC */ 666 667 int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, 668 u8 attr_set, u32 mib_val, u8 peer); 669 int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, 670 u32 *mib_val, u8 peer); 671 672 static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel, 673 u32 mib_val) 674 { 675 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, 676 mib_val, DME_LOCAL); 677 } 678 679 static inline int ufshcd_dme_get(struct ufs_hba *hba, 680 u32 attr_sel, u32 *mib_val) 681 { 682 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL); 683 } 684 685 static inline int ufshcd_dme_peer_get(struct ufs_hba *hba, 686 u32 attr_sel, u32 *mib_val) 687 { 688 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER); 689 } 690 691 static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel, 692 u32 mib_val) 693 { 694 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, 695 mib_val, DME_PEER); 696 } 697 698 /** 699 * struct ufs_query_req - parameters for building a query request 700 * @query_func: UPIU header query function 701 * @upiu_req: the query request data 702 */ 703 struct ufs_query_req { 704 u8 query_func; 705 struct utp_upiu_query upiu_req; 706 }; 707 708 /** 709 * struct ufs_query_resp - UPIU QUERY 710 * @response: device response code 711 * @upiu_res: query response data 712 */ 713 struct ufs_query_res { 714 u8 response; 715 struct utp_upiu_query upiu_res; 716 }; 717 718 /** 719 * struct ufs_query - holds relevant data structures for query request 720 * @request: request upiu and function 721 * @descriptor: buffer for sending/receiving descriptor 722 * @response: response upiu and response 723 */ 724 struct ufs_query { 725 struct ufs_query_req request; 726 u8 *descriptor; 727 struct ufs_query_res response; 728 }; 729 730 /** 731 * struct ufs_dev_cmd - all assosiated fields with device management commands 732 * @type: device management command type - Query, NOP OUT 733 * @tag_wq: wait queue until free command slot is available 734 */ 735 struct ufs_dev_cmd { 736 enum dev_cmd_type type; 737 struct ufs_query query; 738 }; 739 740 struct ufs_hba_ops { 741 int (*init)(struct ufs_hba *hba); 742 int (*hce_enable_notify)(struct ufs_hba *hba, 743 enum ufs_notify_change_status); 744 int (*link_startup_notify)(struct ufs_hba *hba, 745 enum ufs_notify_change_status); 746 int (*phy_initialization)(struct ufs_hba *hba); 747 }; 748 749 struct ufs_hba { 750 struct udevice *dev; 751 void __iomem *mmio_base; 752 struct ufs_hba_ops *ops; 753 struct ufs_desc_size desc_size; 754 u32 capabilities; 755 u32 version; 756 u32 intr_mask; 757 u32 quirks; 758 /* 759 * If UFS host controller is having issue in processing LCC (Line 760 * Control Command) coming from device then enable this quirk. 761 * When this quirk is enabled, host controller driver should disable 762 * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE 763 * attribute of device to 0). 764 */ 765 #define UFSHCD_QUIRK_BROKEN_LCC BIT(0) 766 767 /* 768 * This quirk needs to be enabled if the host controller has 769 * 64-bit addressing supported capability but it doesn't work. 770 */ 771 #define UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS BIT(1) 772 773 /* 774 * This quirk needs to be enabled if the host controller has 775 * auto-hibernate capability but it's FASTAUTO only. 776 */ 777 #define UFSHCD_QUIRK_HIBERN_FASTAUTO BIT(2) 778 779 /* Virtual memory reference */ 780 struct utp_transfer_cmd_desc *ucdl; 781 struct utp_transfer_req_desc *utrdl; 782 /* TODO: Add Task Manegement Support */ 783 struct utp_task_req_desc *utmrdl; 784 785 struct utp_upiu_req *ucd_req_ptr; 786 struct utp_upiu_rsp *ucd_rsp_ptr; 787 struct ufshcd_sg_entry *ucd_prdt_ptr; 788 789 /* Power Mode information */ 790 enum ufs_dev_pwr_mode curr_dev_pwr_mode; 791 struct ufs_pa_layer_attr pwr_info; 792 struct ufs_pwr_mode_info max_pwr_info; 793 794 struct ufs_dev_cmd dev_cmd; 795 struct ufs_device_descriptor *dev_desc; 796 #if defined(CONFIG_SUPPORT_USBPLUG) 797 struct ufs_configuration_descriptor *rc_desc; 798 struct ufs_configuration_descriptor *wc_desc; 799 struct ufs_geometry_descriptor *geo_desc; 800 #endif 801 }; 802 803 static inline int ufshcd_ops_init(struct ufs_hba *hba) 804 { 805 if (hba->ops && hba->ops->init) 806 return hba->ops->init(hba); 807 808 return 0; 809 } 810 811 static inline int ufshcd_ops_hce_enable_notify(struct ufs_hba *hba, 812 bool status) 813 { 814 if (hba->ops && hba->ops->hce_enable_notify) 815 return hba->ops->hce_enable_notify(hba, status); 816 817 return 0; 818 } 819 820 static inline int ufshcd_ops_link_startup_notify(struct ufs_hba *hba, 821 bool status) 822 { 823 if (hba->ops && hba->ops->link_startup_notify) 824 return hba->ops->link_startup_notify(hba, status); 825 826 return 0; 827 } 828 829 /* Controller UFSHCI version */ 830 enum { 831 UFSHCI_VERSION_10 = 0x00010000, /* 1.0 */ 832 UFSHCI_VERSION_11 = 0x00010100, /* 1.1 */ 833 UFSHCI_VERSION_20 = 0x00000200, /* 2.0 */ 834 UFSHCI_VERSION_21 = 0x00000210, /* 2.1 */ 835 UFSHCI_VERSION_30 = 0x00000300, /* 3.0 */ 836 UFSHCI_VERSION_31 = 0x00000310, /* 3.1 */ 837 }; 838 839 /* Interrupt disable masks */ 840 enum { 841 /* Interrupt disable mask for UFSHCI v1.0 */ 842 INTERRUPT_MASK_ALL_VER_10 = 0x30FFF, 843 INTERRUPT_MASK_RW_VER_10 = 0x30000, 844 845 /* Interrupt disable mask for UFSHCI v1.1 */ 846 INTERRUPT_MASK_ALL_VER_11 = 0x31FFF, 847 848 /* Interrupt disable mask for UFSHCI v2.1 */ 849 INTERRUPT_MASK_ALL_VER_21 = 0x71FFF, 850 }; 851 852 /* UFSHCI Registers */ 853 enum { 854 REG_CONTROLLER_CAPABILITIES = 0x00, 855 REG_UFS_VERSION = 0x08, 856 REG_CONTROLLER_DEV_ID = 0x10, 857 REG_CONTROLLER_PROD_ID = 0x14, 858 REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18, 859 REG_INTERRUPT_STATUS = 0x20, 860 REG_INTERRUPT_ENABLE = 0x24, 861 REG_CONTROLLER_STATUS = 0x30, 862 REG_CONTROLLER_ENABLE = 0x34, 863 REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38, 864 REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C, 865 REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40, 866 REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44, 867 REG_UIC_ERROR_CODE_DME = 0x48, 868 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C, 869 REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50, 870 REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54, 871 REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58, 872 REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C, 873 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60, 874 REG_UTP_TASK_REQ_LIST_BASE_L = 0x70, 875 REG_UTP_TASK_REQ_LIST_BASE_H = 0x74, 876 REG_UTP_TASK_REQ_DOOR_BELL = 0x78, 877 REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C, 878 REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80, 879 REG_UIC_COMMAND = 0x90, 880 REG_UIC_COMMAND_ARG_1 = 0x94, 881 REG_UIC_COMMAND_ARG_2 = 0x98, 882 REG_UIC_COMMAND_ARG_3 = 0x9C, 883 884 UFSHCI_REG_SPACE_SIZE = 0xA0, 885 886 REG_UFS_CCAP = 0x100, 887 REG_UFS_CRYPTOCAP = 0x104, 888 889 UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400, 890 }; 891 892 /* Controller capability masks */ 893 enum { 894 MASK_TRANSFER_REQUESTS_SLOTS = 0x0000001F, 895 MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000, 896 MASK_AUTO_HIBERN8_SUPPORT = 0x00800000, 897 MASK_64_ADDRESSING_SUPPORT = 0x01000000, 898 MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000, 899 MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000, 900 }; 901 902 /* Interrupt Status 20h */ 903 #define UTP_TRANSFER_REQ_COMPL 0x1 904 #define UIC_DME_END_PT_RESET 0x2 905 #define UIC_ERROR 0x4 906 #define UIC_TEST_MODE 0x8 907 #define UIC_POWER_MODE 0x10 908 #define UIC_HIBERNATE_EXIT 0x20 909 #define UIC_HIBERNATE_ENTER 0x40 910 #define UIC_LINK_LOST 0x80 911 #define UIC_LINK_STARTUP 0x100 912 #define UTP_TASK_REQ_COMPL 0x200 913 #define UIC_COMMAND_COMPL 0x400 914 #define DEVICE_FATAL_ERROR 0x800 915 #define CONTROLLER_FATAL_ERROR 0x10000 916 #define SYSTEM_BUS_FATAL_ERROR 0x20000 917 918 #define UFSHCD_UIC_PWR_MASK (UIC_HIBERNATE_ENTER |\ 919 UIC_HIBERNATE_EXIT |\ 920 UIC_POWER_MODE) 921 922 #define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL | UIC_POWER_MODE) 923 924 #define UFSHCD_ERROR_MASK (UIC_ERROR |\ 925 DEVICE_FATAL_ERROR |\ 926 CONTROLLER_FATAL_ERROR |\ 927 SYSTEM_BUS_FATAL_ERROR) 928 929 #define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\ 930 CONTROLLER_FATAL_ERROR |\ 931 SYSTEM_BUS_FATAL_ERROR) 932 933 /* Host Controller Enable 0x34h */ 934 #define CONTROLLER_ENABLE 0x1 935 #define CONTROLLER_DISABLE 0x0 936 /* HCS - Host Controller Status 30h */ 937 #define DEVICE_PRESENT 0x1 938 #define UTP_TRANSFER_REQ_LIST_READY 0x2 939 #define UTP_TASK_REQ_LIST_READY 0x4 940 #define UIC_COMMAND_READY 0x8 941 #define HOST_ERROR_INDICATOR 0x10 942 #define DEVICE_ERROR_INDICATOR 0x20 943 #define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8) 944 945 #define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY |\ 946 UTP_TASK_REQ_LIST_READY |\ 947 UIC_COMMAND_READY) 948 949 enum { 950 PWR_OK = 0x0, 951 PWR_LOCAL = 0x01, 952 PWR_REMOTE = 0x02, 953 PWR_BUSY = 0x03, 954 PWR_ERROR_CAP = 0x04, 955 PWR_FATAL_ERROR = 0x05, 956 }; 957 958 /* UICCMD - UIC Command */ 959 #define COMMAND_OPCODE_MASK 0xFF 960 #define GEN_SELECTOR_INDEX_MASK 0xFFFF 961 962 #define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16) 963 #define RESET_LEVEL 0xFF 964 965 #define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16) 966 #define CFG_RESULT_CODE_MASK 0xFF 967 #define GENERIC_ERROR_CODE_MASK 0xFF 968 969 #define ufshcd_writel(hba, val, reg) \ 970 writel((val), (hba)->mmio_base + (reg)) 971 #define ufshcd_readl(hba, reg) \ 972 readl((hba)->mmio_base + (reg)) 973 974 /* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */ 975 #define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1 976 977 /* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */ 978 #define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1 979 980 int ufshcd_probe(struct udevice *dev, struct ufs_hba_ops *hba_ops); 981 int ufshcd_dme_reset(struct ufs_hba *hba); 982 int ufshcd_dme_enable(struct ufs_hba *hba); 983 int ufs_create_partition_inventory(struct ufs_hba *hba); 984 int ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id, int *desc_len); 985 int ufshcd_read_desc_param(struct ufs_hba *hba, enum desc_idn desc_id, 986 int desc_index, u8 param_offset, u8 *param_read_buf, 987 u8 param_size); 988 int ufshcd_query_descriptor_retry(struct ufs_hba *hba, enum query_opcode opcode, 989 enum desc_idn idn, u8 index, u8 selector, 990 u8 *desc_buf, int *buf_len); 991 #endif 992