1 // SPDX-License-Identifier: GPL-2.0+ 2 /** 3 * ufs.c - Universal Flash Subsystem (UFS) driver 4 * 5 * Taken from Linux Kernel v5.2 (drivers/scsi/ufs/ufshcd.c) and ported 6 * to u-boot. 7 * 8 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com 9 */ 10 #include <charset.h> 11 #include <common.h> 12 #include <dm.h> 13 #include <log.h> 14 #include <dm/lists.h> 15 #include <dm/device-internal.h> 16 #include <malloc.h> 17 #include <hexdump.h> 18 #include <scsi.h> 19 #include <asm/io.h> 20 #include <asm/dma-mapping.h> 21 #include <linux/bitops.h> 22 #include <linux/delay.h> 23 24 #if defined(CONFIG_SUPPORT_USBPLUG) 25 #include "ufs-rockchip-usbplug.h" 26 #endif 27 #include "ufs.h" 28 29 #define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\ 30 UTP_TASK_REQ_COMPL |\ 31 UFSHCD_ERROR_MASK) 32 /* maximum number of link-startup retries */ 33 #define DME_LINKSTARTUP_RETRIES 3 34 35 /* maximum number of retries for a general UIC command */ 36 #define UFS_UIC_COMMAND_RETRIES 3 37 38 /* Query request retries */ 39 #define QUERY_REQ_RETRIES 3 40 /* Query request timeout */ 41 #define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */ 42 43 /* maximum timeout in ms for a general UIC command */ 44 #define UFS_UIC_CMD_TIMEOUT 1000 45 46 #define UFS_UIC_LINKUP_TIMEOUT 150 47 /* NOP OUT retries waiting for NOP IN response */ 48 /* Polling time to wait for fDeviceInit */ 49 #define FDEVICEINIT_COMPL_TIMEOUT 1500 /* millisecs */ 50 51 #define NOP_OUT_RETRIES 10 52 /* Timeout after 30 msecs if NOP OUT hangs without response */ 53 #define NOP_OUT_TIMEOUT 30 /* msecs */ 54 55 /* Only use one Task Tag for all requests */ 56 #define TASK_TAG 0 57 58 /* Expose the flag value from utp_upiu_query.value */ 59 #define MASK_QUERY_UPIU_FLAG_LOC 0xFF 60 61 #define MAX_PRDT_ENTRY 262144 62 63 /* maximum bytes per request */ 64 #define UFS_MAX_BYTES (128 * 256 * 1024) 65 66 static inline bool ufshcd_is_hba_active(struct ufs_hba *hba); 67 static inline void ufshcd_hba_stop(struct ufs_hba *hba); 68 static int ufshcd_hba_enable(struct ufs_hba *hba); 69 70 /* 71 * ufshcd_wait_for_register - wait for register value to change 72 */ 73 static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask, 74 u32 val, unsigned long timeout_ms) 75 { 76 int err = 0; 77 unsigned long start = get_timer(0); 78 79 /* ignore bits that we don't intend to wait on */ 80 val = val & mask; 81 82 while ((ufshcd_readl(hba, reg) & mask) != val) { 83 if (get_timer(start) > timeout_ms) { 84 if ((ufshcd_readl(hba, reg) & mask) != val) 85 err = -ETIMEDOUT; 86 break; 87 } 88 } 89 90 return err; 91 } 92 93 /** 94 * ufshcd_init_pwr_info - setting the POR (power on reset) 95 * values in hba power info 96 */ 97 static void ufshcd_init_pwr_info(struct ufs_hba *hba) 98 { 99 hba->pwr_info.gear_rx = UFS_PWM_G1; 100 hba->pwr_info.gear_tx = UFS_PWM_G1; 101 hba->pwr_info.lane_rx = 1; 102 hba->pwr_info.lane_tx = 1; 103 hba->pwr_info.pwr_rx = SLOWAUTO_MODE; 104 hba->pwr_info.pwr_tx = SLOWAUTO_MODE; 105 hba->pwr_info.hs_rate = 0; 106 } 107 108 /** 109 * ufshcd_print_pwr_info - print power params as saved in hba 110 * power info 111 */ 112 static void ufshcd_print_pwr_info(struct ufs_hba *hba) 113 { 114 static const char * const names[] = { 115 "INVALID MODE", 116 "FAST MODE", 117 "SLOW_MODE", 118 "INVALID MODE", 119 "FASTAUTO_MODE", 120 "SLOWAUTO_MODE", 121 "INVALID MODE", 122 }; 123 124 dev_err(hba->dev, "[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n", 125 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx, 126 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx, 127 names[hba->pwr_info.pwr_rx], 128 names[hba->pwr_info.pwr_tx], 129 hba->pwr_info.hs_rate); 130 } 131 132 /** 133 * ufshcd_ready_for_uic_cmd - Check if controller is ready 134 * to accept UIC commands 135 */ 136 static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba) 137 { 138 if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY) 139 return true; 140 else 141 return false; 142 } 143 144 /** 145 * ufshcd_get_uic_cmd_result - Get the UIC command result 146 */ 147 static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba) 148 { 149 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) & 150 MASK_UIC_COMMAND_RESULT; 151 } 152 153 /** 154 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command 155 */ 156 static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba) 157 { 158 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3); 159 } 160 161 /** 162 * ufshcd_is_device_present - Check if any device connected to 163 * the host controller 164 */ 165 static inline bool ufshcd_is_device_present(struct ufs_hba *hba) 166 { 167 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & 168 DEVICE_PRESENT) ? true : false; 169 } 170 171 /** 172 * ufshcd_send_uic_cmd - UFS Interconnect layer command API 173 * 174 */ 175 static int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 176 { 177 unsigned long start = 0; 178 u32 intr_status; 179 u32 enabled_intr_status; 180 int timeout = UFS_UIC_CMD_TIMEOUT; 181 182 if (!ufshcd_ready_for_uic_cmd(hba)) { 183 dev_err(hba->dev, 184 "Controller not ready to accept UIC commands\n"); 185 return -EIO; 186 } 187 188 if (uic_cmd->command == UIC_CMD_DME_LINK_STARTUP) 189 timeout = UFS_UIC_LINKUP_TIMEOUT; 190 191 debug("sending uic command:%d\n", uic_cmd->command); 192 193 /* Write Args */ 194 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1); 195 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2); 196 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3); 197 198 /* Write UIC Cmd */ 199 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK, 200 REG_UIC_COMMAND); 201 202 start = get_timer(0); 203 do { 204 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 205 enabled_intr_status = intr_status & hba->intr_mask; 206 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS); 207 208 if (get_timer(start) > timeout) { 209 dev_err(hba->dev, 210 "Timedout waiting for UIC response\n"); 211 212 return -ETIMEDOUT; 213 } 214 215 if (enabled_intr_status & UFSHCD_ERROR_MASK) { 216 dev_err(hba->dev, "Error in status:%08x\n", 217 enabled_intr_status); 218 219 return -1; 220 } 221 } while (!(enabled_intr_status & UFSHCD_UIC_MASK)); 222 223 uic_cmd->argument2 = ufshcd_get_uic_cmd_result(hba); 224 uic_cmd->argument3 = ufshcd_get_dme_attr_val(hba); 225 226 debug("Sent successfully\n"); 227 228 return 0; 229 } 230 231 /** 232 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET 233 * 234 */ 235 int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, u8 attr_set, 236 u32 mib_val, u8 peer) 237 { 238 struct uic_command uic_cmd = {0}; 239 static const char *const action[] = { 240 "dme-set", 241 "dme-peer-set" 242 }; 243 const char *set = action[!!peer]; 244 int ret; 245 int retries = UFS_UIC_COMMAND_RETRIES; 246 247 uic_cmd.command = peer ? 248 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET; 249 uic_cmd.argument1 = attr_sel; 250 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set); 251 uic_cmd.argument3 = mib_val; 252 253 do { 254 /* for peer attributes we retry upon failure */ 255 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 256 if (ret) 257 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n", 258 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret); 259 } while (ret && peer && --retries); 260 261 if (ret) 262 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n", 263 set, UIC_GET_ATTR_ID(attr_sel), mib_val, 264 UFS_UIC_COMMAND_RETRIES - retries); 265 266 return ret; 267 } 268 269 /** 270 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET 271 * 272 */ 273 int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, 274 u32 *mib_val, u8 peer) 275 { 276 struct uic_command uic_cmd = {0}; 277 static const char *const action[] = { 278 "dme-get", 279 "dme-peer-get" 280 }; 281 const char *get = action[!!peer]; 282 int ret; 283 int retries = UFS_UIC_COMMAND_RETRIES; 284 285 uic_cmd.command = peer ? 286 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET; 287 uic_cmd.argument1 = attr_sel; 288 289 do { 290 /* for peer attributes we retry upon failure */ 291 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 292 if (ret) 293 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n", 294 get, UIC_GET_ATTR_ID(attr_sel), ret); 295 } while (ret && peer && --retries); 296 297 if (ret) 298 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n", 299 get, UIC_GET_ATTR_ID(attr_sel), 300 UFS_UIC_COMMAND_RETRIES - retries); 301 302 if (mib_val && !ret) 303 *mib_val = uic_cmd.argument3; 304 305 return ret; 306 } 307 308 static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer) 309 { 310 u32 tx_lanes, i, err = 0; 311 312 if (!peer) 313 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 314 &tx_lanes); 315 else 316 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 317 &tx_lanes); 318 for (i = 0; i < tx_lanes; i++) { 319 if (!peer) 320 err = ufshcd_dme_set(hba, 321 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, 322 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), 323 0); 324 else 325 err = ufshcd_dme_peer_set(hba, 326 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, 327 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), 328 0); 329 if (err) { 330 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d\n", 331 __func__, peer, i, err); 332 break; 333 } 334 } 335 336 return err; 337 } 338 339 static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba) 340 { 341 return ufshcd_disable_tx_lcc(hba, true); 342 } 343 344 /** 345 * ufshcd_dme_link_startup - Notify Unipro to perform link startup 346 * 347 */ 348 static int ufshcd_dme_link_startup(struct ufs_hba *hba) 349 { 350 struct uic_command uic_cmd = {0}; 351 int ret; 352 353 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP; 354 355 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 356 if (ret) 357 dev_dbg(hba->dev, 358 "dme-link-startup: error code %d\n", ret); 359 return ret; 360 } 361 362 int ufshcd_dme_enable(struct ufs_hba *hba) 363 { 364 struct uic_command uic_cmd = {0}; 365 int ret; 366 367 uic_cmd.command = UIC_CMD_DME_ENABLE; 368 369 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 370 if (ret) 371 dev_err(hba->dev, 372 "dme-enable: error code %d\n", ret); 373 return ret; 374 } 375 376 int ufshcd_dme_reset(struct ufs_hba *hba) 377 { 378 struct uic_command uic_cmd = {0}; 379 int ret; 380 381 uic_cmd.command = UIC_CMD_DME_RESET; 382 383 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 384 if (ret) 385 dev_err(hba->dev, 386 "dme-reset: error code %d\n", ret); 387 return ret; 388 } 389 390 /** 391 * ufshcd_disable_intr_aggr - Disables interrupt aggregation. 392 * 393 */ 394 static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba) 395 { 396 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 397 } 398 399 /** 400 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY 401 */ 402 static inline int ufshcd_get_lists_status(u32 reg) 403 { 404 return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY); 405 } 406 407 /** 408 * ufshcd_enable_run_stop_reg - Enable run-stop registers, 409 * When run-stop registers are set to 1, it indicates the 410 * host controller that it can process the requests 411 */ 412 static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba) 413 { 414 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT, 415 REG_UTP_TASK_REQ_LIST_RUN_STOP); 416 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT, 417 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP); 418 } 419 420 /** 421 * ufshcd_enable_intr - enable interrupts 422 */ 423 static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs) 424 { 425 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 426 u32 rw; 427 428 if (hba->version == UFSHCI_VERSION_10) { 429 rw = set & INTERRUPT_MASK_RW_VER_10; 430 set = rw | ((set ^ intrs) & intrs); 431 } else { 432 set |= intrs; 433 } 434 435 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); 436 437 hba->intr_mask = set; 438 } 439 440 /** 441 * ufshcd_make_hba_operational - Make UFS controller operational 442 * 443 * To bring UFS host controller to operational state, 444 * 1. Enable required interrupts 445 * 2. Configure interrupt aggregation 446 * 3. Program UTRL and UTMRL base address 447 * 4. Configure run-stop-registers 448 * 449 */ 450 static int ufshcd_make_hba_operational(struct ufs_hba *hba) 451 { 452 int err = 0; 453 u32 reg; 454 455 /* Enable required interrupts */ 456 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS); 457 458 /* Disable interrupt aggregation */ 459 ufshcd_disable_intr_aggr(hba); 460 461 /* Configure UTRL and UTMRL base address registers */ 462 ufshcd_writel(hba, lower_32_bits((dma_addr_t)hba->utrdl), 463 REG_UTP_TRANSFER_REQ_LIST_BASE_L); 464 ufshcd_writel(hba, upper_32_bits((dma_addr_t)hba->utrdl), 465 REG_UTP_TRANSFER_REQ_LIST_BASE_H); 466 ufshcd_writel(hba, lower_32_bits((dma_addr_t)hba->utmrdl), 467 REG_UTP_TASK_REQ_LIST_BASE_L); 468 ufshcd_writel(hba, upper_32_bits((dma_addr_t)hba->utmrdl), 469 REG_UTP_TASK_REQ_LIST_BASE_H); 470 471 /* 472 * UCRDY, UTMRLDY and UTRLRDY bits must be 1 473 */ 474 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS); 475 if (!(ufshcd_get_lists_status(reg))) { 476 ufshcd_enable_run_stop_reg(hba); 477 } else { 478 dev_err(hba->dev, 479 "Host controller not ready to process requests\n"); 480 err = -EIO; 481 goto out; 482 } 483 484 out: 485 return err; 486 } 487 488 /** 489 * ufshcd_link_startup - Initialize unipro link startup 490 */ 491 static int ufshcd_link_startup(struct ufs_hba *hba) 492 { 493 int ret; 494 int retries = DME_LINKSTARTUP_RETRIES; 495 bool link_startup_again = true; 496 497 link_startup: 498 do { 499 ufshcd_ops_link_startup_notify(hba, PRE_CHANGE); 500 501 ret = ufshcd_dme_link_startup(hba); 502 503 /* check if device is detected by inter-connect layer */ 504 if (!ret && !ufshcd_is_device_present(hba)) { 505 dev_err(hba->dev, "%s: Device not present\n", __func__); 506 ret = -ENXIO; 507 goto out; 508 } 509 510 /* 511 * DME link lost indication is only received when link is up, 512 * but we can't be sure if the link is up until link startup 513 * succeeds. So reset the local Uni-Pro and try again. 514 */ 515 if (ret && ufshcd_hba_enable(hba)) 516 goto out; 517 } while (ret && retries--); 518 519 if (ret) 520 /* failed to get the link up... retire */ 521 goto out; 522 523 if (link_startup_again) { 524 link_startup_again = false; 525 retries = DME_LINKSTARTUP_RETRIES; 526 goto link_startup; 527 } 528 529 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */ 530 ufshcd_init_pwr_info(hba); 531 532 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) { 533 ret = ufshcd_disable_device_tx_lcc(hba); 534 if (ret) 535 goto out; 536 } 537 538 /* Include any host controller configuration via UIC commands */ 539 ret = ufshcd_ops_link_startup_notify(hba, POST_CHANGE); 540 if (ret) 541 goto out; 542 543 ret = ufshcd_make_hba_operational(hba); 544 out: 545 if (ret) 546 dev_err(hba->dev, "link startup failed %d\n", ret); 547 548 return ret; 549 } 550 551 /** 552 * ufshcd_hba_stop - Send controller to reset state 553 */ 554 static inline void ufshcd_hba_stop(struct ufs_hba *hba) 555 { 556 int err; 557 558 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE); 559 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE, 560 CONTROLLER_ENABLE, CONTROLLER_DISABLE, 561 10); 562 if (err) 563 dev_err(hba->dev, "%s: Controller disable failed\n", __func__); 564 } 565 566 /** 567 * ufshcd_is_hba_active - Get controller state 568 */ 569 static inline bool ufshcd_is_hba_active(struct ufs_hba *hba) 570 { 571 return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE) 572 ? false : true; 573 } 574 575 /** 576 * ufshcd_hba_start - Start controller initialization sequence 577 */ 578 static inline void ufshcd_hba_start(struct ufs_hba *hba) 579 { 580 ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE); 581 } 582 583 /** 584 * ufshcd_hba_enable - initialize the controller 585 */ 586 static int ufshcd_hba_enable(struct ufs_hba *hba) 587 { 588 int retry; 589 590 if (!ufshcd_is_hba_active(hba)) 591 /* change controller state to "reset state" */ 592 ufshcd_hba_stop(hba); 593 594 ufshcd_ops_hce_enable_notify(hba, PRE_CHANGE); 595 596 /* start controller initialization sequence */ 597 ufshcd_hba_start(hba); 598 599 /* 600 * To initialize a UFS host controller HCE bit must be set to 1. 601 * During initialization the HCE bit value changes from 1->0->1. 602 * When the host controller completes initialization sequence 603 * it sets the value of HCE bit to 1. The same HCE bit is read back 604 * to check if the controller has completed initialization sequence. 605 * So without this delay the value HCE = 1, set in the previous 606 * instruction might be read back. 607 * This delay can be changed based on the controller. 608 */ 609 mdelay(1); 610 611 /* wait for the host controller to complete initialization */ 612 retry = 10; 613 while (ufshcd_is_hba_active(hba)) { 614 if (retry) { 615 retry--; 616 } else { 617 dev_err(hba->dev, "Controller enable failed\n"); 618 return -EIO; 619 } 620 mdelay(5); 621 } 622 623 /* enable UIC related interrupts */ 624 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK); 625 626 if (ufshcd_ops_hce_enable_notify(hba, POST_CHANGE)) 627 return -EIO; 628 629 return 0; 630 } 631 632 /** 633 * ufshcd_host_memory_configure - configure local reference block with 634 * memory offsets 635 */ 636 static void ufshcd_host_memory_configure(struct ufs_hba *hba) 637 { 638 struct utp_transfer_req_desc *utrdlp; 639 dma_addr_t cmd_desc_dma_addr; 640 u16 response_offset; 641 u16 prdt_offset; 642 643 utrdlp = hba->utrdl; 644 cmd_desc_dma_addr = (dma_addr_t)hba->ucdl; 645 646 utrdlp->command_desc_base_addr_lo = 647 cpu_to_le32(lower_32_bits(cmd_desc_dma_addr)); 648 utrdlp->command_desc_base_addr_hi = 649 cpu_to_le32(upper_32_bits(cmd_desc_dma_addr)); 650 651 response_offset = offsetof(struct utp_transfer_cmd_desc, response_upiu); 652 prdt_offset = offsetof(struct utp_transfer_cmd_desc, prd_table); 653 654 utrdlp->response_upiu_offset = cpu_to_le16(response_offset >> 2); 655 utrdlp->prd_table_offset = cpu_to_le16(prdt_offset >> 2); 656 utrdlp->response_upiu_length = cpu_to_le16(ALIGNED_UPIU_SIZE >> 2); 657 658 hba->ucd_req_ptr = (struct utp_upiu_req *)hba->ucdl; 659 hba->ucd_rsp_ptr = 660 (struct utp_upiu_rsp *)&hba->ucdl->response_upiu; 661 hba->ucd_prdt_ptr = 662 (struct ufshcd_sg_entry *)&hba->ucdl->prd_table; 663 } 664 665 /** 666 * ufshcd_memory_alloc - allocate memory for host memory space data structures 667 */ 668 static int ufshcd_memory_alloc(struct ufs_hba *hba) 669 { 670 /* Allocate one Transfer Request Descriptor 671 * Should be aligned to 1k boundary. 672 */ 673 hba->utrdl = memalign(1024, sizeof(struct utp_transfer_req_desc)); 674 if (!hba->utrdl) { 675 dev_err(hba->dev, "Transfer Descriptor memory allocation failed\n"); 676 return -ENOMEM; 677 } 678 679 /* Allocate one Command Descriptor 680 * Should be aligned to 1k boundary. 681 */ 682 hba->ucdl = memalign(1024, sizeof(struct utp_transfer_cmd_desc)); 683 if (!hba->ucdl) { 684 dev_err(hba->dev, "Command descriptor memory allocation failed\n"); 685 return -ENOMEM; 686 } 687 688 hba->dev_desc = memalign(ARCH_DMA_MINALIGN, sizeof(struct ufs_device_descriptor)); 689 if (!hba->dev_desc) { 690 dev_err(hba->dev, "memory allocation failed\n"); 691 return -ENOMEM; 692 } 693 694 #if defined(CONFIG_SUPPORT_USBPLUG) 695 hba->rc_desc = memalign(ARCH_DMA_MINALIGN, sizeof(struct ufs_configuration_descriptor)); 696 hba->wc_desc = memalign(ARCH_DMA_MINALIGN, sizeof(struct ufs_configuration_descriptor)); 697 hba->geo_desc = memalign(ARCH_DMA_MINALIGN, sizeof(struct ufs_geometry_descriptor)); 698 if (!hba->rc_desc || !hba->wc_desc || !hba->geo_desc) { 699 dev_err(hba->dev, "memory allocation failed\n"); 700 return -ENOMEM; 701 } 702 #endif 703 return 0; 704 } 705 706 /** 707 * ufshcd_get_intr_mask - Get the interrupt bit mask 708 */ 709 static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba) 710 { 711 u32 intr_mask = 0; 712 713 switch (hba->version) { 714 case UFSHCI_VERSION_10: 715 intr_mask = INTERRUPT_MASK_ALL_VER_10; 716 break; 717 case UFSHCI_VERSION_11: 718 case UFSHCI_VERSION_20: 719 intr_mask = INTERRUPT_MASK_ALL_VER_11; 720 break; 721 case UFSHCI_VERSION_21: 722 default: 723 intr_mask = INTERRUPT_MASK_ALL_VER_21; 724 break; 725 } 726 727 return intr_mask; 728 } 729 730 /** 731 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA 732 */ 733 static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba) 734 { 735 return ufshcd_readl(hba, REG_UFS_VERSION); 736 } 737 738 /** 739 * ufshcd_get_upmcrs - Get the power mode change request status 740 */ 741 static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba) 742 { 743 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7; 744 } 745 746 /** 747 * ufshcd_cache_flush_and_invalidate - Flush and invalidate cache 748 * 749 * Flush and invalidate cache in aligned address..address+size range. 750 * The invalidation is in place to avoid stale data in cache. 751 */ 752 static void ufshcd_cache_flush_and_invalidate(void *addr, unsigned long size) 753 { 754 uintptr_t aaddr = (uintptr_t)addr & ~(ARCH_DMA_MINALIGN - 1); 755 unsigned long asize = ALIGN(size, ARCH_DMA_MINALIGN); 756 757 flush_dcache_range(aaddr, aaddr + asize); 758 invalidate_dcache_range(aaddr, aaddr + asize); 759 } 760 761 /** 762 * ufshcd_prepare_req_desc_hdr() - Fills the requests header 763 * descriptor according to request 764 */ 765 static void ufshcd_prepare_req_desc_hdr(struct utp_transfer_req_desc *req_desc, 766 u32 *upiu_flags, 767 enum dma_data_direction cmd_dir) 768 { 769 u32 data_direction; 770 u32 dword_0; 771 772 if (cmd_dir == DMA_FROM_DEVICE) { 773 data_direction = UTP_DEVICE_TO_HOST; 774 *upiu_flags = UPIU_CMD_FLAGS_READ; 775 } else if (cmd_dir == DMA_TO_DEVICE) { 776 data_direction = UTP_HOST_TO_DEVICE; 777 *upiu_flags = UPIU_CMD_FLAGS_WRITE; 778 } else { 779 data_direction = UTP_NO_DATA_TRANSFER; 780 *upiu_flags = UPIU_CMD_FLAGS_NONE; 781 } 782 783 dword_0 = data_direction | (0x1 << UPIU_COMMAND_TYPE_OFFSET); 784 785 /* Enable Interrupt for command */ 786 dword_0 |= UTP_REQ_DESC_INT_CMD; 787 788 /* Transfer request descriptor header fields */ 789 req_desc->header.dword_0 = cpu_to_le32(dword_0); 790 /* dword_1 is reserved, hence it is set to 0 */ 791 req_desc->header.dword_1 = 0; 792 /* 793 * assigning invalid value for command status. Controller 794 * updates OCS on command completion, with the command 795 * status 796 */ 797 req_desc->header.dword_2 = 798 cpu_to_le32(OCS_INVALID_COMMAND_STATUS); 799 /* dword_3 is reserved, hence it is set to 0 */ 800 req_desc->header.dword_3 = 0; 801 802 req_desc->prd_table_length = 0; 803 804 ufshcd_cache_flush_and_invalidate(req_desc, sizeof(*req_desc)); 805 } 806 807 static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba, 808 u32 upiu_flags) 809 { 810 struct utp_upiu_req *ucd_req_ptr = hba->ucd_req_ptr; 811 struct ufs_query *query = &hba->dev_cmd.query; 812 u16 len = be16_to_cpu(query->request.upiu_req.length); 813 814 /* Query request header */ 815 ucd_req_ptr->header.dword_0 = 816 UPIU_HEADER_DWORD(UPIU_TRANSACTION_QUERY_REQ, 817 upiu_flags, 0, TASK_TAG); 818 ucd_req_ptr->header.dword_1 = 819 UPIU_HEADER_DWORD(0, query->request.query_func, 820 0, 0); 821 822 /* Data segment length only need for WRITE_DESC */ 823 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC) 824 ucd_req_ptr->header.dword_2 = 825 UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len); 826 else 827 ucd_req_ptr->header.dword_2 = 0; 828 829 /* Copy the Query Request buffer as is */ 830 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req, QUERY_OSF_SIZE); 831 832 /* Copy the Descriptor */ 833 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC) { 834 memcpy(ucd_req_ptr + 1, query->descriptor, len); 835 ufshcd_cache_flush_and_invalidate(ucd_req_ptr, 836 ALIGN(sizeof(*ucd_req_ptr) + len, ARCH_DMA_MINALIGN)); 837 } else { 838 ufshcd_cache_flush_and_invalidate(ucd_req_ptr, sizeof(*ucd_req_ptr)); 839 } 840 841 memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 842 ufshcd_cache_flush_and_invalidate(hba->ucd_rsp_ptr, sizeof(*hba->ucd_rsp_ptr)); 843 } 844 845 static inline void ufshcd_prepare_utp_nop_upiu(struct ufs_hba *hba) 846 { 847 struct utp_upiu_req *ucd_req_ptr = hba->ucd_req_ptr; 848 849 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req)); 850 851 /* command descriptor fields */ 852 ucd_req_ptr->header.dword_0 = 853 UPIU_HEADER_DWORD(UPIU_TRANSACTION_NOP_OUT, 0, 0, TASK_TAG); 854 /* clear rest of the fields of basic header */ 855 ucd_req_ptr->header.dword_1 = 0; 856 ucd_req_ptr->header.dword_2 = 0; 857 858 memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 859 860 ufshcd_cache_flush_and_invalidate(ucd_req_ptr, sizeof(*ucd_req_ptr)); 861 ufshcd_cache_flush_and_invalidate(hba->ucd_rsp_ptr, sizeof(*hba->ucd_rsp_ptr)); 862 } 863 864 /** 865 * ufshcd_comp_devman_upiu - UFS Protocol Information Unit(UPIU) 866 * for Device Management Purposes 867 */ 868 static int ufshcd_comp_devman_upiu(struct ufs_hba *hba, 869 enum dev_cmd_type cmd_type) 870 { 871 u32 upiu_flags; 872 int ret = 0; 873 struct utp_transfer_req_desc *req_desc = hba->utrdl; 874 875 hba->dev_cmd.type = cmd_type; 876 877 ufshcd_prepare_req_desc_hdr(req_desc, &upiu_flags, DMA_NONE); 878 switch (cmd_type) { 879 case DEV_CMD_TYPE_QUERY: 880 ufshcd_prepare_utp_query_req_upiu(hba, upiu_flags); 881 break; 882 case DEV_CMD_TYPE_NOP: 883 ufshcd_prepare_utp_nop_upiu(hba); 884 break; 885 default: 886 ret = -EINVAL; 887 } 888 889 return ret; 890 } 891 892 static int ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag) 893 { 894 unsigned long start; 895 u32 intr_status; 896 u32 enabled_intr_status; 897 898 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL); 899 900 start = get_timer(0); 901 do { 902 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 903 enabled_intr_status = intr_status & hba->intr_mask; 904 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS); 905 906 if (get_timer(start) > QUERY_REQ_TIMEOUT) { 907 dev_err(hba->dev, 908 "Timedout waiting for UTP response\n"); 909 910 return -ETIMEDOUT; 911 } 912 913 if (enabled_intr_status & UFSHCD_ERROR_MASK) { 914 dev_err(hba->dev, "Error in status:%08x\n", 915 enabled_intr_status); 916 917 return -1; 918 } 919 } while (!(enabled_intr_status & UTP_TRANSFER_REQ_COMPL)); 920 921 return 0; 922 } 923 924 /** 925 * ufshcd_get_req_rsp - returns the TR response transaction type 926 */ 927 static inline int ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr) 928 { 929 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24; 930 } 931 932 /** 933 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status 934 * 935 */ 936 static inline int ufshcd_get_tr_ocs(struct ufs_hba *hba) 937 { 938 return le32_to_cpu(hba->utrdl->header.dword_2) & MASK_OCS; 939 } 940 941 static inline int ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr) 942 { 943 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT; 944 } 945 946 static int ufshcd_check_query_response(struct ufs_hba *hba) 947 { 948 struct ufs_query_res *query_res = &hba->dev_cmd.query.response; 949 950 /* Get the UPIU response */ 951 query_res->response = ufshcd_get_rsp_upiu_result(hba->ucd_rsp_ptr) >> 952 UPIU_RSP_CODE_OFFSET; 953 return query_res->response; 954 } 955 956 /** 957 * ufshcd_copy_query_response() - Copy the Query Response and the data 958 * descriptor 959 */ 960 static int ufshcd_copy_query_response(struct ufs_hba *hba) 961 { 962 struct ufs_query_res *query_res = &hba->dev_cmd.query.response; 963 964 memcpy(&query_res->upiu_res, &hba->ucd_rsp_ptr->qr, QUERY_OSF_SIZE); 965 966 /* Get the descriptor */ 967 if (hba->dev_cmd.query.descriptor && 968 hba->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) { 969 u8 *descp = (u8 *)hba->ucd_rsp_ptr + 970 GENERAL_UPIU_REQUEST_SIZE; 971 u16 resp_len; 972 u16 buf_len; 973 974 /* data segment length */ 975 resp_len = be32_to_cpu(hba->ucd_rsp_ptr->header.dword_2) & 976 MASK_QUERY_DATA_SEG_LEN; 977 buf_len = 978 be16_to_cpu(hba->dev_cmd.query.request.upiu_req.length); 979 if (likely(buf_len >= resp_len)) { 980 int size = ALIGN(GENERAL_UPIU_REQUEST_SIZE + resp_len, ARCH_DMA_MINALIGN); 981 982 invalidate_dcache_range((uintptr_t)hba->ucd_rsp_ptr, (uintptr_t)hba->ucd_rsp_ptr + size); 983 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len); 984 } else { 985 dev_warn(hba->dev, 986 "%s: Response size is bigger than buffer", 987 __func__); 988 return -EINVAL; 989 } 990 } 991 992 return 0; 993 } 994 995 /** 996 * ufshcd_exec_dev_cmd - API for sending device management requests 997 */ 998 int ufshcd_exec_dev_cmd(struct ufs_hba *hba, enum dev_cmd_type cmd_type, int timeout) 999 { 1000 int err; 1001 int resp; 1002 1003 err = ufshcd_comp_devman_upiu(hba, cmd_type); 1004 if (err) 1005 return err; 1006 1007 err = ufshcd_send_command(hba, TASK_TAG); 1008 if (err) 1009 return err; 1010 1011 err = ufshcd_get_tr_ocs(hba); 1012 if (err) { 1013 dev_err(hba->dev, "Error in OCS:%d\n", err); 1014 return -EINVAL; 1015 } 1016 1017 resp = ufshcd_get_req_rsp(hba->ucd_rsp_ptr); 1018 switch (resp) { 1019 case UPIU_TRANSACTION_NOP_IN: 1020 break; 1021 case UPIU_TRANSACTION_QUERY_RSP: 1022 err = ufshcd_check_query_response(hba); 1023 if (!err) 1024 err = ufshcd_copy_query_response(hba); 1025 break; 1026 case UPIU_TRANSACTION_REJECT_UPIU: 1027 /* TODO: handle Reject UPIU Response */ 1028 err = -EPERM; 1029 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n", 1030 __func__); 1031 break; 1032 default: 1033 err = -EINVAL; 1034 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n", 1035 __func__, resp); 1036 } 1037 1038 return err; 1039 } 1040 1041 /** 1042 * ufshcd_init_query() - init the query response and request parameters 1043 */ 1044 static inline void ufshcd_init_query(struct ufs_hba *hba, 1045 struct ufs_query_req **request, 1046 struct ufs_query_res **response, 1047 enum query_opcode opcode, 1048 u8 idn, u8 index, u8 selector) 1049 { 1050 *request = &hba->dev_cmd.query.request; 1051 *response = &hba->dev_cmd.query.response; 1052 memset(*request, 0, sizeof(struct ufs_query_req)); 1053 memset(*response, 0, sizeof(struct ufs_query_res)); 1054 (*request)->upiu_req.opcode = opcode; 1055 (*request)->upiu_req.idn = idn; 1056 (*request)->upiu_req.index = index; 1057 (*request)->upiu_req.selector = selector; 1058 } 1059 1060 /** 1061 * ufshcd_query_flag() - API function for sending flag query requests 1062 */ 1063 int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode, 1064 enum flag_idn idn, bool *flag_res) 1065 { 1066 struct ufs_query_req *request = NULL; 1067 struct ufs_query_res *response = NULL; 1068 int err, index = 0, selector = 0; 1069 int timeout = QUERY_REQ_TIMEOUT; 1070 1071 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 1072 selector); 1073 1074 switch (opcode) { 1075 case UPIU_QUERY_OPCODE_SET_FLAG: 1076 case UPIU_QUERY_OPCODE_CLEAR_FLAG: 1077 case UPIU_QUERY_OPCODE_TOGGLE_FLAG: 1078 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 1079 break; 1080 case UPIU_QUERY_OPCODE_READ_FLAG: 1081 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 1082 if (!flag_res) { 1083 /* No dummy reads */ 1084 dev_err(hba->dev, "%s: Invalid argument for read request\n", 1085 __func__); 1086 err = -EINVAL; 1087 goto out; 1088 } 1089 break; 1090 default: 1091 dev_err(hba->dev, 1092 "%s: Expected query flag opcode but got = %d\n", 1093 __func__, opcode); 1094 err = -EINVAL; 1095 goto out; 1096 } 1097 1098 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout); 1099 1100 if (err) { 1101 dev_err(hba->dev, 1102 "%s: Sending flag query for idn %d failed, err = %d\n", 1103 __func__, idn, err); 1104 goto out; 1105 } 1106 1107 if (flag_res) 1108 *flag_res = (be32_to_cpu(response->upiu_res.value) & 1109 MASK_QUERY_UPIU_FLAG_LOC) & 0x1; 1110 1111 out: 1112 return err; 1113 } 1114 1115 static int ufshcd_query_flag_retry(struct ufs_hba *hba, 1116 enum query_opcode opcode, 1117 enum flag_idn idn, bool *flag_res) 1118 { 1119 int ret; 1120 int retries; 1121 1122 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) { 1123 ret = ufshcd_query_flag(hba, opcode, idn, flag_res); 1124 if (ret) 1125 dev_dbg(hba->dev, 1126 "%s: failed with error %d, retries %d\n", 1127 __func__, ret, retries); 1128 else 1129 break; 1130 } 1131 1132 if (ret) 1133 dev_err(hba->dev, 1134 "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n", 1135 __func__, opcode, idn, ret, retries); 1136 return ret; 1137 } 1138 1139 static int __ufshcd_query_descriptor(struct ufs_hba *hba, 1140 enum query_opcode opcode, 1141 enum desc_idn idn, u8 index, u8 selector, 1142 u8 *desc_buf, int *buf_len) 1143 { 1144 struct ufs_query_req *request = NULL; 1145 struct ufs_query_res *response = NULL; 1146 int err; 1147 1148 if (!desc_buf) { 1149 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n", 1150 __func__, opcode); 1151 err = -EINVAL; 1152 goto out; 1153 } 1154 1155 if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) { 1156 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n", 1157 __func__, *buf_len); 1158 err = -EINVAL; 1159 goto out; 1160 } 1161 1162 ufshcd_init_query(hba, &request, &response, opcode, idn, index, selector); 1163 hba->dev_cmd.query.descriptor = desc_buf; 1164 request->upiu_req.length = cpu_to_be16(*buf_len); 1165 1166 switch (opcode) { 1167 case UPIU_QUERY_OPCODE_WRITE_DESC: 1168 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 1169 break; 1170 case UPIU_QUERY_OPCODE_READ_DESC: 1171 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 1172 break; 1173 default: 1174 dev_err(hba->dev, "%s: Expected query descriptor opcode but got = 0x%.2x\n", 1175 __func__, opcode); 1176 err = -EINVAL; 1177 goto out; 1178 } 1179 1180 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 1181 1182 if (err) { 1183 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n", 1184 __func__, opcode, idn, index, err); 1185 goto out; 1186 } 1187 1188 hba->dev_cmd.query.descriptor = NULL; 1189 *buf_len = be16_to_cpu(response->upiu_res.length); 1190 1191 out: 1192 return err; 1193 } 1194 1195 /** 1196 * ufshcd_query_descriptor_retry - API function for sending descriptor requests 1197 */ 1198 int ufshcd_query_descriptor_retry(struct ufs_hba *hba, enum query_opcode opcode, 1199 enum desc_idn idn, u8 index, u8 selector, 1200 u8 *desc_buf, int *buf_len) 1201 { 1202 int err; 1203 int retries; 1204 1205 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) { 1206 err = __ufshcd_query_descriptor(hba, opcode, idn, index, 1207 selector, desc_buf, buf_len); 1208 if (!err || err == -EINVAL) 1209 break; 1210 } 1211 1212 return err; 1213 } 1214 1215 /** 1216 * ufshcd_read_desc_length - read the specified descriptor length from header 1217 */ 1218 int ufshcd_read_desc_length(struct ufs_hba *hba, enum desc_idn desc_id, 1219 int desc_index, int *desc_length) 1220 { 1221 int ret; 1222 u8 header[QUERY_DESC_HDR_SIZE]; 1223 int header_len = QUERY_DESC_HDR_SIZE; 1224 1225 if (desc_id >= QUERY_DESC_IDN_MAX) 1226 return -EINVAL; 1227 1228 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC, 1229 desc_id, desc_index, 0, header, 1230 &header_len); 1231 1232 if (ret) { 1233 dev_err(hba->dev, "%s: Failed to get descriptor header id %d\n", 1234 __func__, desc_id); 1235 return ret; 1236 } else if (desc_id != header[QUERY_DESC_DESC_TYPE_OFFSET]) { 1237 dev_warn(hba->dev, "%s: descriptor header id %d and desc_id %d mismatch\n", 1238 __func__, header[QUERY_DESC_DESC_TYPE_OFFSET], 1239 desc_id); 1240 ret = -EINVAL; 1241 } 1242 1243 *desc_length = header[QUERY_DESC_LENGTH_OFFSET]; 1244 1245 return ret; 1246 } 1247 1248 static void ufshcd_init_desc_sizes(struct ufs_hba *hba) 1249 { 1250 int err; 1251 1252 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_DEVICE, 0, 1253 &hba->desc_size.dev_desc); 1254 if (err) 1255 hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE; 1256 1257 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_POWER, 0, 1258 &hba->desc_size.pwr_desc); 1259 if (err) 1260 hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE; 1261 1262 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_INTERCONNECT, 0, 1263 &hba->desc_size.interc_desc); 1264 if (err) 1265 hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE; 1266 1267 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_CONFIGURATION, 0, 1268 &hba->desc_size.conf_desc); 1269 if (err) 1270 hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE; 1271 1272 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_UNIT, 0, 1273 &hba->desc_size.unit_desc); 1274 if (err) 1275 hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE; 1276 1277 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_GEOMETRY, 0, 1278 &hba->desc_size.geom_desc); 1279 if (err) 1280 hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE; 1281 1282 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_HEALTH, 0, 1283 &hba->desc_size.hlth_desc); 1284 if (err) 1285 hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE; 1286 } 1287 1288 /** 1289 * ufshcd_map_desc_id_to_length - map descriptor IDN to its length 1290 * 1291 */ 1292 int ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id, 1293 int *desc_len) 1294 { 1295 switch (desc_id) { 1296 case QUERY_DESC_IDN_DEVICE: 1297 *desc_len = hba->desc_size.dev_desc; 1298 break; 1299 case QUERY_DESC_IDN_POWER: 1300 *desc_len = hba->desc_size.pwr_desc; 1301 break; 1302 case QUERY_DESC_IDN_GEOMETRY: 1303 *desc_len = hba->desc_size.geom_desc; 1304 break; 1305 case QUERY_DESC_IDN_CONFIGURATION: 1306 *desc_len = hba->desc_size.conf_desc; 1307 break; 1308 case QUERY_DESC_IDN_UNIT: 1309 *desc_len = hba->desc_size.unit_desc; 1310 break; 1311 case QUERY_DESC_IDN_INTERCONNECT: 1312 *desc_len = hba->desc_size.interc_desc; 1313 break; 1314 case QUERY_DESC_IDN_STRING: 1315 *desc_len = QUERY_DESC_MAX_SIZE; 1316 break; 1317 case QUERY_DESC_IDN_HEALTH: 1318 *desc_len = hba->desc_size.hlth_desc; 1319 break; 1320 case QUERY_DESC_IDN_RFU_0: 1321 case QUERY_DESC_IDN_RFU_1: 1322 *desc_len = 0; 1323 break; 1324 default: 1325 *desc_len = 0; 1326 return -EINVAL; 1327 } 1328 return 0; 1329 } 1330 EXPORT_SYMBOL(ufshcd_map_desc_id_to_length); 1331 1332 /** 1333 * ufshcd_read_desc_param - read the specified descriptor parameter 1334 * 1335 */ 1336 int ufshcd_read_desc_param(struct ufs_hba *hba, enum desc_idn desc_id, 1337 int desc_index, u8 param_offset, u8 *param_read_buf, 1338 u8 param_size) 1339 { 1340 int ret; 1341 u8 *desc_buf; 1342 int buff_len; 1343 bool is_kmalloc = true; 1344 1345 /* Safety check */ 1346 if (desc_id >= QUERY_DESC_IDN_MAX || !param_size) 1347 return -EINVAL; 1348 1349 /* Get the max length of descriptor from structure filled up at probe 1350 * time. 1351 */ 1352 ret = ufshcd_map_desc_id_to_length(hba, desc_id, &buff_len); 1353 1354 /* Sanity checks */ 1355 if (ret || !buff_len) { 1356 dev_err(hba->dev, "%s: Failed to get full descriptor length\n", 1357 __func__); 1358 return ret; 1359 } 1360 1361 /* Check whether we need temp memory */ 1362 if (param_offset != 0 || param_size < buff_len) { 1363 desc_buf = kmalloc(buff_len, GFP_KERNEL); 1364 if (!desc_buf) 1365 return -ENOMEM; 1366 } else { 1367 desc_buf = param_read_buf; 1368 is_kmalloc = false; 1369 } 1370 1371 /* Request for full descriptor */ 1372 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC, 1373 desc_id, desc_index, 0, desc_buf, 1374 &buff_len); 1375 1376 if (ret) { 1377 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d\n", 1378 __func__, desc_id, desc_index, param_offset, ret); 1379 goto out; 1380 } 1381 1382 /* Sanity check */ 1383 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) { 1384 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header\n", 1385 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]); 1386 ret = -EINVAL; 1387 goto out; 1388 } 1389 1390 /* Check wherher we will not copy more data, than available */ 1391 if (is_kmalloc && param_size > buff_len) 1392 param_size = buff_len; 1393 1394 if (is_kmalloc) 1395 memcpy(param_read_buf, &desc_buf[param_offset], param_size); 1396 out: 1397 if (is_kmalloc) 1398 kfree(desc_buf); 1399 return ret; 1400 } 1401 1402 /* replace non-printable or non-ASCII characters with spaces */ 1403 static inline void ufshcd_remove_non_printable(uint8_t *val) 1404 { 1405 if (!val) 1406 return; 1407 1408 if (*val < 0x20 || *val > 0x7e) 1409 *val = ' '; 1410 } 1411 1412 /** 1413 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power 1414 * state) and waits for it to take effect. 1415 * 1416 */ 1417 static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd) 1418 { 1419 unsigned long start = 0; 1420 u8 status; 1421 int ret; 1422 1423 ret = ufshcd_send_uic_cmd(hba, cmd); 1424 if (ret) { 1425 dev_err(hba->dev, 1426 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n", 1427 cmd->command, cmd->argument3, ret); 1428 1429 return ret; 1430 } 1431 1432 start = get_timer(0); 1433 do { 1434 status = ufshcd_get_upmcrs(hba); 1435 if (get_timer(start) > UFS_UIC_CMD_TIMEOUT) { 1436 dev_err(hba->dev, 1437 "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n", 1438 cmd->command, status); 1439 ret = (status != PWR_OK) ? status : -1; 1440 break; 1441 } 1442 } while (status != PWR_LOCAL); 1443 1444 return ret; 1445 } 1446 1447 /** 1448 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode change 1449 * using DME_SET primitives. 1450 */ 1451 static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode) 1452 { 1453 struct uic_command uic_cmd = {0}; 1454 int ret; 1455 1456 uic_cmd.command = UIC_CMD_DME_SET; 1457 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE); 1458 uic_cmd.argument3 = mode; 1459 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 1460 1461 return ret; 1462 } 1463 1464 static 1465 void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufs_hba *hba, 1466 struct scsi_cmd *pccb, u32 upiu_flags) 1467 { 1468 struct utp_upiu_req *ucd_req_ptr = hba->ucd_req_ptr; 1469 unsigned int cdb_len; 1470 1471 /* command descriptor fields */ 1472 ucd_req_ptr->header.dword_0 = 1473 UPIU_HEADER_DWORD(UPIU_TRANSACTION_COMMAND, upiu_flags, 1474 pccb->lun, TASK_TAG); 1475 ucd_req_ptr->header.dword_1 = 1476 UPIU_HEADER_DWORD(UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0); 1477 1478 /* Total EHS length and Data segment length will be zero */ 1479 ucd_req_ptr->header.dword_2 = 0; 1480 1481 ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(pccb->datalen); 1482 1483 cdb_len = min_t(unsigned short, pccb->cmdlen, UFS_CDB_SIZE); 1484 memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE); 1485 memcpy(ucd_req_ptr->sc.cdb, pccb->cmd, cdb_len); 1486 1487 memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 1488 ufshcd_cache_flush_and_invalidate(ucd_req_ptr, sizeof(*ucd_req_ptr)); 1489 ufshcd_cache_flush_and_invalidate(hba->ucd_rsp_ptr, sizeof(*hba->ucd_rsp_ptr)); 1490 } 1491 1492 static inline void prepare_prdt_desc(struct ufshcd_sg_entry *entry, 1493 unsigned char *buf, ulong len) 1494 { 1495 entry->size = cpu_to_le32(len) | GENMASK(1, 0); 1496 entry->base_addr = cpu_to_le32(lower_32_bits((unsigned long)buf)); 1497 entry->upper_addr = cpu_to_le32(upper_32_bits((unsigned long)buf)); 1498 } 1499 1500 static void prepare_prdt_table(struct ufs_hba *hba, struct scsi_cmd *pccb) 1501 { 1502 struct utp_transfer_req_desc *req_desc = hba->utrdl; 1503 struct ufshcd_sg_entry *prd_table = hba->ucd_prdt_ptr; 1504 uintptr_t aaddr = (uintptr_t)(pccb->pdata) & ~(ARCH_DMA_MINALIGN - 1); 1505 ulong datalen = pccb->datalen; 1506 int table_length; 1507 u8 *buf; 1508 int i; 1509 1510 if (!datalen) { 1511 req_desc->prd_table_length = 0; 1512 ufshcd_cache_flush_and_invalidate(req_desc, sizeof(*req_desc)); 1513 return; 1514 } 1515 1516 if (pccb->dma_dir == DMA_TO_DEVICE) { /* Write to device */ 1517 flush_dcache_range(aaddr, ALIGN(aaddr + datalen + ARCH_DMA_MINALIGN - 1, ARCH_DMA_MINALIGN)); 1518 } 1519 1520 /* In any case, invalidate cache to avoid stale data in it. */ 1521 invalidate_dcache_range(aaddr, ALIGN(aaddr + datalen + ARCH_DMA_MINALIGN - 1, ARCH_DMA_MINALIGN)); 1522 1523 table_length = DIV_ROUND_UP(pccb->datalen, MAX_PRDT_ENTRY); 1524 buf = pccb->pdata; 1525 i = table_length; 1526 while (--i) { 1527 prepare_prdt_desc(&prd_table[table_length - i - 1], buf, 1528 MAX_PRDT_ENTRY - 1); 1529 buf += MAX_PRDT_ENTRY; 1530 datalen -= MAX_PRDT_ENTRY; 1531 } 1532 1533 prepare_prdt_desc(&prd_table[table_length - i - 1], buf, datalen - 1); 1534 1535 req_desc->prd_table_length = table_length; 1536 ufshcd_cache_flush_and_invalidate(prd_table, sizeof(*prd_table) * table_length); 1537 ufshcd_cache_flush_and_invalidate(req_desc, sizeof(*req_desc)); 1538 } 1539 1540 static int ufs_scsi_exec(struct udevice *scsi_dev, struct scsi_cmd *pccb) 1541 { 1542 struct ufs_hba *hba = dev_get_uclass_priv(scsi_dev->parent); 1543 struct utp_transfer_req_desc *req_desc = hba->utrdl; 1544 u32 upiu_flags; 1545 int ocs, result = 0, retry_count = 3; 1546 u8 scsi_status; 1547 1548 /* cmd do not set lun for ufs 2.1 */ 1549 if (hba->dev_desc->w_spec_version == 0x1002) /* verison 0x210 in big end */ 1550 pccb->cmd[1] &= 0x1F; 1551 retry: 1552 ufshcd_prepare_req_desc_hdr(req_desc, &upiu_flags, pccb->dma_dir); 1553 ufshcd_prepare_utp_scsi_cmd_upiu(hba, pccb, upiu_flags); 1554 prepare_prdt_table(hba, pccb); 1555 1556 if (ufshcd_send_command(hba, TASK_TAG) == -ETIMEDOUT && retry_count) { 1557 retry_count--; 1558 goto retry; 1559 } 1560 1561 ocs = ufshcd_get_tr_ocs(hba); 1562 switch (ocs) { 1563 case OCS_SUCCESS: 1564 result = ufshcd_get_req_rsp(hba->ucd_rsp_ptr); 1565 switch (result) { 1566 case UPIU_TRANSACTION_RESPONSE: 1567 result = ufshcd_get_rsp_upiu_result(hba->ucd_rsp_ptr); 1568 1569 scsi_status = result & MASK_SCSI_STATUS; 1570 if (pccb->cmd[0] == SCSI_TST_U_RDY && scsi_status) { 1571 /* Test ready cmd will fail with Phison UFS, break to continue */ 1572 if (retry_count) { 1573 retry_count--; 1574 goto retry; 1575 } 1576 break; 1577 } 1578 if (scsi_status) 1579 return -EINVAL; 1580 1581 break; 1582 case UPIU_TRANSACTION_REJECT_UPIU: 1583 /* TODO: handle Reject UPIU Response */ 1584 dev_err(hba->dev, 1585 "Reject UPIU not fully implemented\n"); 1586 return -EINVAL; 1587 default: 1588 dev_err(hba->dev, 1589 "Unexpected request response code = %x\n", 1590 result); 1591 return -EINVAL; 1592 } 1593 break; 1594 default: 1595 dev_err(hba->dev, "OCS error from controller = %x\n", ocs); 1596 return -EINVAL; 1597 } 1598 1599 return 0; 1600 } 1601 1602 static inline int ufshcd_read_desc(struct ufs_hba *hba, enum desc_idn desc_id, 1603 int desc_index, u8 *buf, u32 size) 1604 { 1605 return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size); 1606 } 1607 1608 static int ufshcd_read_device_desc(struct ufs_hba *hba, u8 *buf, u32 size) 1609 { 1610 return ufshcd_read_desc(hba, QUERY_DESC_IDN_DEVICE, 0, buf, size); 1611 } 1612 1613 /** 1614 * ufshcd_read_string_desc - read string descriptor 1615 * 1616 */ 1617 int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index, 1618 u8 *buf, u32 size, bool ascii) 1619 { 1620 int err = 0; 1621 1622 err = ufshcd_read_desc(hba, QUERY_DESC_IDN_STRING, desc_index, buf, 1623 size); 1624 1625 if (err) { 1626 dev_err(hba->dev, "%s: reading String Desc failed after %d retries. err = %d\n", 1627 __func__, QUERY_REQ_RETRIES, err); 1628 goto out; 1629 } 1630 1631 if (ascii) { 1632 int desc_len; 1633 int ascii_len; 1634 int i; 1635 u8 *buff_ascii; 1636 1637 desc_len = buf[0]; 1638 /* remove header and divide by 2 to move from UTF16 to UTF8 */ 1639 ascii_len = (desc_len - QUERY_DESC_HDR_SIZE) / 2 + 1; 1640 if (size < ascii_len + QUERY_DESC_HDR_SIZE) { 1641 dev_err(hba->dev, "%s: buffer allocated size is too small\n", 1642 __func__); 1643 err = -ENOMEM; 1644 goto out; 1645 } 1646 1647 buff_ascii = kmalloc(ALIGN(ascii_len, ARCH_DMA_MINALIGN), GFP_KERNEL); 1648 if (!buff_ascii) { 1649 err = -ENOMEM; 1650 goto out; 1651 } 1652 1653 /* 1654 * the descriptor contains string in UTF16 format 1655 * we need to convert to utf-8 so it can be displayed 1656 */ 1657 utf16_to_utf8(buff_ascii, 1658 (uint16_t *)&buf[QUERY_DESC_HDR_SIZE], ascii_len); 1659 1660 /* replace non-printable or non-ASCII characters with spaces */ 1661 for (i = 0; i < ascii_len; i++) 1662 ufshcd_remove_non_printable(&buff_ascii[i]); 1663 1664 memset(buf + QUERY_DESC_HDR_SIZE, 0, 1665 size - QUERY_DESC_HDR_SIZE); 1666 memcpy(buf + QUERY_DESC_HDR_SIZE, buff_ascii, ascii_len); 1667 buf[QUERY_DESC_LENGTH_OFFSET] = ascii_len + QUERY_DESC_HDR_SIZE; 1668 kfree(buff_ascii); 1669 } 1670 out: 1671 return err; 1672 } 1673 1674 static int ufs_get_device_desc(struct ufs_hba *hba, struct ufs_device_descriptor *dev_desc) 1675 { 1676 int err; 1677 size_t buff_len; 1678 1679 buff_len = sizeof(*dev_desc); 1680 if (buff_len > hba->desc_size.dev_desc) 1681 buff_len = hba->desc_size.dev_desc; 1682 1683 err = ufshcd_read_device_desc(hba, (u8 *)dev_desc, buff_len); 1684 if (err) 1685 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n", 1686 __func__, err); 1687 1688 return err; 1689 } 1690 1691 /** 1692 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device 1693 */ 1694 static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba) 1695 { 1696 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info; 1697 1698 if (hba->max_pwr_info.is_valid) 1699 return 0; 1700 1701 pwr_info->pwr_tx = FAST_MODE; 1702 pwr_info->pwr_rx = FAST_MODE; 1703 pwr_info->hs_rate = PA_HS_MODE_B; 1704 1705 /* Get the connected lane count */ 1706 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES), 1707 &pwr_info->lane_rx); 1708 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 1709 &pwr_info->lane_tx); 1710 1711 if (!pwr_info->lane_rx || !pwr_info->lane_tx) { 1712 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n", 1713 __func__, pwr_info->lane_rx, pwr_info->lane_tx); 1714 return -EINVAL; 1715 } 1716 1717 /* 1718 * First, get the maximum gears of HS speed. 1719 * If a zero value, it means there is no HSGEAR capability. 1720 * Then, get the maximum gears of PWM speed. 1721 */ 1722 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx); 1723 if (!pwr_info->gear_rx) { 1724 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), 1725 &pwr_info->gear_rx); 1726 if (!pwr_info->gear_rx) { 1727 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n", 1728 __func__, pwr_info->gear_rx); 1729 return -EINVAL; 1730 } 1731 pwr_info->pwr_rx = SLOW_MODE; 1732 } 1733 1734 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), 1735 &pwr_info->gear_tx); 1736 if (!pwr_info->gear_tx) { 1737 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), 1738 &pwr_info->gear_tx); 1739 if (!pwr_info->gear_tx) { 1740 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n", 1741 __func__, pwr_info->gear_tx); 1742 return -EINVAL; 1743 } 1744 pwr_info->pwr_tx = SLOW_MODE; 1745 } 1746 1747 hba->max_pwr_info.is_valid = true; 1748 return 0; 1749 } 1750 1751 static int ufshcd_change_power_mode(struct ufs_hba *hba, 1752 struct ufs_pa_layer_attr *pwr_mode) 1753 { 1754 int ret; 1755 1756 /* if already configured to the requested pwr_mode */ 1757 if (pwr_mode->gear_rx == hba->pwr_info.gear_rx && 1758 pwr_mode->gear_tx == hba->pwr_info.gear_tx && 1759 pwr_mode->lane_rx == hba->pwr_info.lane_rx && 1760 pwr_mode->lane_tx == hba->pwr_info.lane_tx && 1761 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx && 1762 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx && 1763 pwr_mode->hs_rate == hba->pwr_info.hs_rate) { 1764 dev_dbg(hba->dev, "%s: power already configured\n", __func__); 1765 return 0; 1766 } 1767 1768 /* 1769 * Configure attributes for power mode change with below. 1770 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION, 1771 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION, 1772 * - PA_HSSERIES 1773 */ 1774 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx); 1775 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES), 1776 pwr_mode->lane_rx); 1777 if (pwr_mode->pwr_rx == FASTAUTO_MODE || pwr_mode->pwr_rx == FAST_MODE) 1778 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE); 1779 else 1780 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE); 1781 1782 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx); 1783 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES), 1784 pwr_mode->lane_tx); 1785 if (pwr_mode->pwr_tx == FASTAUTO_MODE || pwr_mode->pwr_tx == FAST_MODE) 1786 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE); 1787 else 1788 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE); 1789 1790 if (pwr_mode->pwr_rx == FASTAUTO_MODE || 1791 pwr_mode->pwr_tx == FASTAUTO_MODE || 1792 pwr_mode->pwr_rx == FAST_MODE || 1793 pwr_mode->pwr_tx == FAST_MODE) 1794 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES), 1795 pwr_mode->hs_rate); 1796 1797 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4 | 1798 pwr_mode->pwr_tx); 1799 1800 if (ret) { 1801 dev_err(hba->dev, 1802 "%s: power mode change failed %d\n", __func__, ret); 1803 1804 return ret; 1805 } 1806 1807 /* Copy new Power Mode to power info */ 1808 memcpy(&hba->pwr_info, pwr_mode, sizeof(struct ufs_pa_layer_attr)); 1809 1810 return ret; 1811 } 1812 1813 /** 1814 * ufshcd_verify_dev_init() - Verify device initialization 1815 * 1816 */ 1817 static int ufshcd_verify_dev_init(struct ufs_hba *hba) 1818 { 1819 int retries; 1820 int err; 1821 1822 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) { 1823 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP, 1824 NOP_OUT_TIMEOUT); 1825 if (!err || err == -ETIMEDOUT) 1826 break; 1827 1828 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err); 1829 } 1830 1831 if (err) 1832 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err); 1833 1834 return err; 1835 } 1836 1837 /** 1838 * ufshcd_complete_dev_init() - checks device readiness 1839 */ 1840 static int ufshcd_complete_dev_init(struct ufs_hba *hba) 1841 { 1842 unsigned long start = 0; 1843 int i; 1844 int err; 1845 bool flag_res = 1; 1846 1847 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG, 1848 QUERY_FLAG_IDN_FDEVICEINIT, NULL); 1849 if (err) { 1850 dev_err(hba->dev, 1851 "%s setting fDeviceInit flag failed with error %d\n", 1852 __func__, err); 1853 goto out; 1854 } 1855 1856 /* poll for max. 1500ms for fDeviceInit flag to clear */ 1857 start = get_timer(0); 1858 for (i = 0; i < 3000 && !err && flag_res; i++) { 1859 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG, 1860 QUERY_FLAG_IDN_FDEVICEINIT, 1861 &flag_res); 1862 if (get_timer(start) > FDEVICEINIT_COMPL_TIMEOUT) 1863 break; 1864 udelay(500); 1865 } 1866 1867 if (err) 1868 dev_err(hba->dev, 1869 "%s reading fDeviceInit flag failed with error %d\n", 1870 __func__, err); 1871 else if (flag_res) 1872 dev_err(hba->dev, 1873 "%s fDeviceInit was not cleared by the device\n", 1874 __func__); 1875 1876 out: 1877 return err; 1878 } 1879 1880 static void ufshcd_def_desc_sizes(struct ufs_hba *hba) 1881 { 1882 hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE; 1883 hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE; 1884 hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE; 1885 hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE; 1886 hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE; 1887 hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE; 1888 hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE; 1889 } 1890 1891 int _ufs_start(struct ufs_hba *hba) 1892 { 1893 int ret; 1894 1895 ret = ufshcd_link_startup(hba); 1896 if (ret) 1897 return ret; 1898 1899 ret = ufshcd_verify_dev_init(hba); 1900 if (ret) 1901 return ret; 1902 1903 ret = ufshcd_complete_dev_init(hba); 1904 if (ret) 1905 return ret; 1906 1907 /* Init check for device descriptor sizes */ 1908 ufshcd_init_desc_sizes(hba); 1909 1910 ret = ufs_get_device_desc(hba, hba->dev_desc); 1911 if (ret) { 1912 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n", 1913 __func__, ret); 1914 1915 return ret; 1916 } 1917 1918 return ret; 1919 } 1920 1921 int ufs_start(struct ufs_hba *hba) 1922 { 1923 int ret; 1924 1925 ret = _ufs_start(hba); 1926 if (ret) 1927 return ret; 1928 1929 #if defined(CONFIG_SUPPORT_USBPLUG) 1930 ret = ufs_create_partition_inventory(hba); 1931 if (ret) { 1932 dev_err(hba->dev, "%s: Failed to creat partition. err = %d\n", __func__, ret); 1933 return ret; 1934 } 1935 #endif 1936 if (ufshcd_get_max_pwr_mode(hba)) { 1937 dev_err(hba->dev, 1938 "%s: Failed getting max supported power mode\n", 1939 __func__); 1940 } else { 1941 ret = ufshcd_change_power_mode(hba, &hba->max_pwr_info.info); 1942 if (ret) { 1943 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n", 1944 __func__, ret); 1945 1946 return ret; 1947 } 1948 1949 printf("Device at %s up at:", hba->dev->name); 1950 ufshcd_print_pwr_info(hba); 1951 } 1952 1953 return 0; 1954 } 1955 1956 int ufshcd_probe(struct udevice *ufs_dev, struct ufs_hba_ops *hba_ops) 1957 { 1958 struct ufs_hba *hba = dev_get_uclass_priv(ufs_dev); 1959 struct scsi_platdata *scsi_plat; 1960 struct udevice *scsi_dev; 1961 int err; 1962 1963 device_find_first_child(ufs_dev, &scsi_dev); 1964 if (!scsi_dev) 1965 return -ENODEV; 1966 1967 scsi_plat = dev_get_uclass_platdata(scsi_dev); 1968 scsi_plat->max_id = UFSHCD_MAX_ID; 1969 scsi_plat->max_lun = UFS_MAX_LUNS; 1970 //scsi_plat->max_bytes_per_req = UFS_MAX_BYTES; 1971 1972 hba->dev = ufs_dev; 1973 hba->ops = hba_ops; 1974 hba->mmio_base = (void *)dev_read_addr(ufs_dev); 1975 1976 /* Set descriptor lengths to specification defaults */ 1977 ufshcd_def_desc_sizes(hba); 1978 1979 ufshcd_ops_init(hba); 1980 1981 /* Read capabilties registers */ 1982 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES); 1983 1984 /* Get UFS version supported by the controller */ 1985 hba->version = ufshcd_get_ufs_version(hba); 1986 if (hba->version != UFSHCI_VERSION_10 && 1987 hba->version != UFSHCI_VERSION_11 && 1988 hba->version != UFSHCI_VERSION_20 && 1989 hba->version != UFSHCI_VERSION_21) 1990 dev_err(hba->dev, "invalid UFS version 0x%x\n", 1991 hba->version); 1992 1993 /* Get Interrupt bit mask per version */ 1994 hba->intr_mask = ufshcd_get_intr_mask(hba); 1995 1996 /* Allocate memory for host memory space */ 1997 err = ufshcd_memory_alloc(hba); 1998 if (err) { 1999 dev_err(hba->dev, "Memory allocation failed\n"); 2000 return err; 2001 } 2002 2003 /* Configure Local data structures */ 2004 ufshcd_host_memory_configure(hba); 2005 2006 /* 2007 * In order to avoid any spurious interrupt immediately after 2008 * registering UFS controller interrupt handler, clear any pending UFS 2009 * interrupt status and disable all the UFS interrupts. 2010 */ 2011 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS), 2012 REG_INTERRUPT_STATUS); 2013 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE); 2014 2015 err = ufshcd_hba_enable(hba); 2016 if (err) { 2017 dev_err(hba->dev, "Host controller enable failed\n"); 2018 return err; 2019 } 2020 2021 err = ufs_start(hba); 2022 if (err) 2023 return err; 2024 2025 return 0; 2026 } 2027 2028 int ufs_scsi_bind(struct udevice *ufs_dev, struct udevice **scsi_devp) 2029 { 2030 int ret = device_bind_driver(ufs_dev, "ufs_scsi", "ufs_scsi", 2031 scsi_devp); 2032 2033 return ret; 2034 } 2035 2036 static struct scsi_ops ufs_ops = { 2037 .exec = ufs_scsi_exec, 2038 }; 2039 2040 int ufs_probe_dev(int index) 2041 { 2042 struct udevice *dev; 2043 2044 return uclass_get_device(UCLASS_UFS, index, &dev); 2045 } 2046 2047 int ufs_probe(void) 2048 { 2049 struct udevice *dev; 2050 int ret, i; 2051 2052 for (i = 0;; i++) { 2053 ret = uclass_get_device(UCLASS_UFS, i, &dev); 2054 if (ret == -ENODEV) 2055 break; 2056 } 2057 2058 return 0; 2059 } 2060 2061 U_BOOT_DRIVER(ufs_scsi) = { 2062 .id = UCLASS_SCSI, 2063 .name = "ufs_scsi", 2064 .ops = &ufs_ops, 2065 }; 2066