1 // SPDX-License-Identifier: GPL-2.0+ 2 /** 3 * ufs.c - Universal Flash Subsystem (UFS) driver 4 * 5 * Taken from Linux Kernel v5.2 (drivers/scsi/ufs/ufshcd.c) and ported 6 * to u-boot. 7 * 8 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com 9 */ 10 #include <charset.h> 11 #include <common.h> 12 #include <dm.h> 13 #include <log.h> 14 #include <dm/lists.h> 15 #include <dm/device-internal.h> 16 #include <malloc.h> 17 #include <hexdump.h> 18 #include <scsi.h> 19 #include <asm/io.h> 20 #include <asm/dma-mapping.h> 21 #include <linux/bitops.h> 22 #include <linux/delay.h> 23 24 #if defined(CONFIG_SUPPORT_USBPLUG) 25 #include "ufs-rockchip-usbplug.h" 26 #endif 27 28 #include "ufs.h" 29 30 #if defined(CONFIG_ROCKCHIP_UFS_RPMB) 31 #include "ufs-rockchip-rpmb.h" 32 #endif 33 34 #define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\ 35 UTP_TASK_REQ_COMPL |\ 36 UFSHCD_ERROR_MASK) 37 /* maximum number of link-startup retries */ 38 #define DME_LINKSTARTUP_RETRIES 3 39 40 /* maximum number of retries for a general UIC command */ 41 #define UFS_UIC_COMMAND_RETRIES 3 42 43 /* Query request retries */ 44 #define QUERY_REQ_RETRIES 3 45 /* Query request timeout */ 46 #define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */ 47 48 /* maximum timeout in ms for a general UIC command */ 49 #define UFS_UIC_CMD_TIMEOUT 1000 50 /* NOP OUT retries waiting for NOP IN response */ 51 /* Polling time to wait for fDeviceInit */ 52 #define FDEVICEINIT_COMPL_TIMEOUT 1500 /* millisecs */ 53 54 #define NOP_OUT_RETRIES 10 55 /* Timeout after 30 msecs if NOP OUT hangs without response */ 56 #define NOP_OUT_TIMEOUT 30 /* msecs */ 57 58 /* Only use one Task Tag for all requests */ 59 #define TASK_TAG 0 60 61 /* Expose the flag value from utp_upiu_query.value */ 62 #define MASK_QUERY_UPIU_FLAG_LOC 0xFF 63 64 #define MAX_PRDT_ENTRY 262144 65 66 /* maximum bytes per request */ 67 #define UFS_MAX_BYTES (128 * 256 * 1024) 68 69 static inline bool ufshcd_is_hba_active(struct ufs_hba *hba); 70 static inline void ufshcd_hba_stop(struct ufs_hba *hba); 71 static int ufshcd_hba_enable(struct ufs_hba *hba); 72 73 /* 74 * ufshcd_wait_for_register - wait for register value to change 75 */ 76 static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask, 77 u32 val, unsigned long timeout_ms) 78 { 79 int err = 0; 80 unsigned long start = get_timer(0); 81 82 /* ignore bits that we don't intend to wait on */ 83 val = val & mask; 84 85 while ((ufshcd_readl(hba, reg) & mask) != val) { 86 if (get_timer(start) > timeout_ms) { 87 if ((ufshcd_readl(hba, reg) & mask) != val) 88 err = -ETIMEDOUT; 89 break; 90 } 91 } 92 93 return err; 94 } 95 96 /** 97 * ufshcd_init_pwr_info - setting the POR (power on reset) 98 * values in hba power info 99 */ 100 static void ufshcd_init_pwr_info(struct ufs_hba *hba) 101 { 102 hba->pwr_info.gear_rx = UFS_PWM_G1; 103 hba->pwr_info.gear_tx = UFS_PWM_G1; 104 hba->pwr_info.lane_rx = 1; 105 hba->pwr_info.lane_tx = 1; 106 hba->pwr_info.pwr_rx = SLOWAUTO_MODE; 107 hba->pwr_info.pwr_tx = SLOWAUTO_MODE; 108 hba->pwr_info.hs_rate = 0; 109 } 110 111 /** 112 * ufshcd_print_pwr_info - print power params as saved in hba 113 * power info 114 */ 115 static void ufshcd_print_pwr_info(struct ufs_hba *hba) 116 { 117 static const char * const names[] = { 118 "INVALID MODE", 119 "FAST MODE", 120 "SLOW_MODE", 121 "INVALID MODE", 122 "FASTAUTO_MODE", 123 "SLOWAUTO_MODE", 124 "INVALID MODE", 125 }; 126 127 dev_err(hba->dev, "[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n", 128 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx, 129 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx, 130 names[hba->pwr_info.pwr_rx], 131 names[hba->pwr_info.pwr_tx], 132 hba->pwr_info.hs_rate); 133 } 134 135 /** 136 * ufshcd_ready_for_uic_cmd - Check if controller is ready 137 * to accept UIC commands 138 */ 139 static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba) 140 { 141 if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY) 142 return true; 143 else 144 return false; 145 } 146 147 /** 148 * ufshcd_get_uic_cmd_result - Get the UIC command result 149 */ 150 static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba) 151 { 152 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) & 153 MASK_UIC_COMMAND_RESULT; 154 } 155 156 /** 157 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command 158 */ 159 static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba) 160 { 161 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3); 162 } 163 164 /** 165 * ufshcd_is_device_present - Check if any device connected to 166 * the host controller 167 */ 168 static inline bool ufshcd_is_device_present(struct ufs_hba *hba) 169 { 170 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & 171 DEVICE_PRESENT) ? true : false; 172 } 173 174 /** 175 * ufshcd_send_uic_cmd - UFS Interconnect layer command API 176 * 177 */ 178 static int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 179 { 180 unsigned long start = 0; 181 u32 intr_status; 182 u32 enabled_intr_status; 183 184 if (!ufshcd_ready_for_uic_cmd(hba)) { 185 dev_err(hba->dev, 186 "Controller not ready to accept UIC commands\n"); 187 return -EIO; 188 } 189 190 debug("sending uic command:%d\n", uic_cmd->command); 191 192 /* Write Args */ 193 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1); 194 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2); 195 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3); 196 197 /* Write UIC Cmd */ 198 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK, 199 REG_UIC_COMMAND); 200 201 start = get_timer(0); 202 do { 203 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 204 enabled_intr_status = intr_status & hba->intr_mask; 205 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS); 206 207 if (get_timer(start) > UFS_UIC_CMD_TIMEOUT) { 208 dev_err(hba->dev, 209 "Timedout waiting for UIC response\n"); 210 211 return -ETIMEDOUT; 212 } 213 214 if (enabled_intr_status & UFSHCD_ERROR_MASK) { 215 dev_err(hba->dev, "Error in status:%08x\n", 216 enabled_intr_status); 217 218 return -1; 219 } 220 } while (!(enabled_intr_status & UFSHCD_UIC_MASK)); 221 222 uic_cmd->argument2 = ufshcd_get_uic_cmd_result(hba); 223 uic_cmd->argument3 = ufshcd_get_dme_attr_val(hba); 224 225 debug("Sent successfully\n"); 226 227 return 0; 228 } 229 230 /** 231 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET 232 * 233 */ 234 int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, u8 attr_set, 235 u32 mib_val, u8 peer) 236 { 237 struct uic_command uic_cmd = {0}; 238 static const char *const action[] = { 239 "dme-set", 240 "dme-peer-set" 241 }; 242 const char *set = action[!!peer]; 243 int ret; 244 int retries = UFS_UIC_COMMAND_RETRIES; 245 246 uic_cmd.command = peer ? 247 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET; 248 uic_cmd.argument1 = attr_sel; 249 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set); 250 uic_cmd.argument3 = mib_val; 251 252 do { 253 /* for peer attributes we retry upon failure */ 254 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 255 if (ret) 256 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n", 257 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret); 258 } while (ret && peer && --retries); 259 260 if (ret) 261 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n", 262 set, UIC_GET_ATTR_ID(attr_sel), mib_val, 263 UFS_UIC_COMMAND_RETRIES - retries); 264 265 return ret; 266 } 267 268 /** 269 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET 270 * 271 */ 272 int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, 273 u32 *mib_val, u8 peer) 274 { 275 struct uic_command uic_cmd = {0}; 276 static const char *const action[] = { 277 "dme-get", 278 "dme-peer-get" 279 }; 280 const char *get = action[!!peer]; 281 int ret; 282 int retries = UFS_UIC_COMMAND_RETRIES; 283 284 uic_cmd.command = peer ? 285 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET; 286 uic_cmd.argument1 = attr_sel; 287 288 do { 289 /* for peer attributes we retry upon failure */ 290 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 291 if (ret) 292 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n", 293 get, UIC_GET_ATTR_ID(attr_sel), ret); 294 } while (ret && peer && --retries); 295 296 if (ret) 297 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n", 298 get, UIC_GET_ATTR_ID(attr_sel), 299 UFS_UIC_COMMAND_RETRIES - retries); 300 301 if (mib_val && !ret) 302 *mib_val = uic_cmd.argument3; 303 304 return ret; 305 } 306 307 static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer) 308 { 309 u32 tx_lanes, i, err = 0; 310 311 if (!peer) 312 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 313 &tx_lanes); 314 else 315 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 316 &tx_lanes); 317 for (i = 0; i < tx_lanes; i++) { 318 if (!peer) 319 err = ufshcd_dme_set(hba, 320 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, 321 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), 322 0); 323 else 324 err = ufshcd_dme_peer_set(hba, 325 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, 326 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), 327 0); 328 if (err) { 329 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d\n", 330 __func__, peer, i, err); 331 break; 332 } 333 } 334 335 return err; 336 } 337 338 static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba) 339 { 340 return ufshcd_disable_tx_lcc(hba, true); 341 } 342 343 /** 344 * ufshcd_dme_link_startup - Notify Unipro to perform link startup 345 * 346 */ 347 static int ufshcd_dme_link_startup(struct ufs_hba *hba) 348 { 349 struct uic_command uic_cmd = {0}; 350 int ret; 351 352 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP; 353 354 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 355 if (ret) 356 dev_dbg(hba->dev, 357 "dme-link-startup: error code %d\n", ret); 358 return ret; 359 } 360 361 int ufshcd_dme_enable(struct ufs_hba *hba) 362 { 363 struct uic_command uic_cmd = {0}; 364 int ret; 365 366 uic_cmd.command = UIC_CMD_DME_ENABLE; 367 368 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 369 if (ret) 370 dev_err(hba->dev, 371 "dme-enable: error code %d\n", ret); 372 return ret; 373 } 374 375 int ufshcd_dme_reset(struct ufs_hba *hba) 376 { 377 struct uic_command uic_cmd = {0}; 378 int ret; 379 380 uic_cmd.command = UIC_CMD_DME_RESET; 381 382 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 383 if (ret) 384 dev_err(hba->dev, 385 "dme-reset: error code %d\n", ret); 386 return ret; 387 } 388 389 /** 390 * ufshcd_disable_intr_aggr - Disables interrupt aggregation. 391 * 392 */ 393 static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba) 394 { 395 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 396 } 397 398 /** 399 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY 400 */ 401 static inline int ufshcd_get_lists_status(u32 reg) 402 { 403 return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY); 404 } 405 406 /** 407 * ufshcd_enable_run_stop_reg - Enable run-stop registers, 408 * When run-stop registers are set to 1, it indicates the 409 * host controller that it can process the requests 410 */ 411 static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba) 412 { 413 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT, 414 REG_UTP_TASK_REQ_LIST_RUN_STOP); 415 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT, 416 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP); 417 } 418 419 /** 420 * ufshcd_enable_intr - enable interrupts 421 */ 422 static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs) 423 { 424 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 425 u32 rw; 426 427 if (hba->version == UFSHCI_VERSION_10) { 428 rw = set & INTERRUPT_MASK_RW_VER_10; 429 set = rw | ((set ^ intrs) & intrs); 430 } else { 431 set |= intrs; 432 } 433 434 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); 435 436 hba->intr_mask = set; 437 } 438 439 /** 440 * ufshcd_make_hba_operational - Make UFS controller operational 441 * 442 * To bring UFS host controller to operational state, 443 * 1. Enable required interrupts 444 * 2. Configure interrupt aggregation 445 * 3. Program UTRL and UTMRL base address 446 * 4. Configure run-stop-registers 447 * 448 */ 449 static int ufshcd_make_hba_operational(struct ufs_hba *hba) 450 { 451 int err = 0; 452 u32 reg; 453 454 /* Enable required interrupts */ 455 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS); 456 457 /* Disable interrupt aggregation */ 458 ufshcd_disable_intr_aggr(hba); 459 460 /* Configure UTRL and UTMRL base address registers */ 461 ufshcd_writel(hba, lower_32_bits((dma_addr_t)hba->utrdl), 462 REG_UTP_TRANSFER_REQ_LIST_BASE_L); 463 ufshcd_writel(hba, upper_32_bits((dma_addr_t)hba->utrdl), 464 REG_UTP_TRANSFER_REQ_LIST_BASE_H); 465 ufshcd_writel(hba, lower_32_bits((dma_addr_t)hba->utmrdl), 466 REG_UTP_TASK_REQ_LIST_BASE_L); 467 ufshcd_writel(hba, upper_32_bits((dma_addr_t)hba->utmrdl), 468 REG_UTP_TASK_REQ_LIST_BASE_H); 469 470 /* 471 * UCRDY, UTMRLDY and UTRLRDY bits must be 1 472 */ 473 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS); 474 if (!(ufshcd_get_lists_status(reg))) { 475 ufshcd_enable_run_stop_reg(hba); 476 } else { 477 dev_err(hba->dev, 478 "Host controller not ready to process requests\n"); 479 err = -EIO; 480 goto out; 481 } 482 483 out: 484 return err; 485 } 486 487 /** 488 * ufshcd_link_startup - Initialize unipro link startup 489 */ 490 static int ufshcd_link_startup(struct ufs_hba *hba) 491 { 492 int ret; 493 int retries = DME_LINKSTARTUP_RETRIES; 494 bool link_startup_again = true; 495 496 if (ufshcd_is_device_present(hba)) 497 goto device_present; 498 499 link_startup: 500 do { 501 ufshcd_ops_link_startup_notify(hba, PRE_CHANGE); 502 503 ret = ufshcd_dme_link_startup(hba); 504 505 /* check if device is detected by inter-connect layer */ 506 if (!ret && !ufshcd_is_device_present(hba)) { 507 dev_err(hba->dev, "%s: Device not present\n", __func__); 508 ret = -ENXIO; 509 goto out; 510 } 511 512 /* 513 * DME link lost indication is only received when link is up, 514 * but we can't be sure if the link is up until link startup 515 * succeeds. So reset the local Uni-Pro and try again. 516 */ 517 if (ret && ufshcd_hba_enable(hba)) 518 goto out; 519 } while (ret && retries--); 520 521 if (ret) 522 /* failed to get the link up... retire */ 523 goto out; 524 525 if (link_startup_again) { 526 link_startup_again = false; 527 retries = DME_LINKSTARTUP_RETRIES; 528 goto link_startup; 529 } 530 531 device_present: 532 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */ 533 ufshcd_init_pwr_info(hba); 534 535 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) { 536 ret = ufshcd_disable_device_tx_lcc(hba); 537 if (ret) 538 goto out; 539 } 540 541 /* Include any host controller configuration via UIC commands */ 542 ret = ufshcd_ops_link_startup_notify(hba, POST_CHANGE); 543 if (ret) 544 goto out; 545 546 ret = ufshcd_make_hba_operational(hba); 547 out: 548 if (ret) 549 dev_err(hba->dev, "link startup failed %d\n", ret); 550 551 return ret; 552 } 553 554 /** 555 * ufshcd_hba_stop - Send controller to reset state 556 */ 557 static inline void ufshcd_hba_stop(struct ufs_hba *hba) 558 { 559 int err; 560 561 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE); 562 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE, 563 CONTROLLER_ENABLE, CONTROLLER_DISABLE, 564 10); 565 if (err) 566 dev_err(hba->dev, "%s: Controller disable failed\n", __func__); 567 } 568 569 /** 570 * ufshcd_is_hba_active - Get controller state 571 */ 572 static inline bool ufshcd_is_hba_active(struct ufs_hba *hba) 573 { 574 return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE) 575 ? false : true; 576 } 577 578 /** 579 * ufshcd_hba_start - Start controller initialization sequence 580 */ 581 static inline void ufshcd_hba_start(struct ufs_hba *hba) 582 { 583 ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE); 584 } 585 586 /** 587 * ufshcd_hba_enable - initialize the controller 588 */ 589 static int ufshcd_hba_enable(struct ufs_hba *hba) 590 { 591 int retry; 592 593 if (!ufshcd_is_hba_active(hba)) 594 /* change controller state to "reset state" */ 595 ufshcd_hba_stop(hba); 596 597 ufshcd_ops_hce_enable_notify(hba, PRE_CHANGE); 598 599 /* start controller initialization sequence */ 600 ufshcd_hba_start(hba); 601 602 /* 603 * To initialize a UFS host controller HCE bit must be set to 1. 604 * During initialization the HCE bit value changes from 1->0->1. 605 * When the host controller completes initialization sequence 606 * it sets the value of HCE bit to 1. The same HCE bit is read back 607 * to check if the controller has completed initialization sequence. 608 * So without this delay the value HCE = 1, set in the previous 609 * instruction might be read back. 610 * This delay can be changed based on the controller. 611 */ 612 mdelay(1); 613 614 /* wait for the host controller to complete initialization */ 615 retry = 10; 616 while (ufshcd_is_hba_active(hba)) { 617 if (retry) { 618 retry--; 619 } else { 620 dev_err(hba->dev, "Controller enable failed\n"); 621 return -EIO; 622 } 623 mdelay(5); 624 } 625 626 /* enable UIC related interrupts */ 627 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK); 628 629 if (ufshcd_ops_hce_enable_notify(hba, POST_CHANGE)) 630 return -EIO; 631 632 return 0; 633 } 634 635 /** 636 * ufshcd_host_memory_configure - configure local reference block with 637 * memory offsets 638 */ 639 static void ufshcd_host_memory_configure(struct ufs_hba *hba) 640 { 641 struct utp_transfer_req_desc *utrdlp; 642 dma_addr_t cmd_desc_dma_addr; 643 u16 response_offset; 644 u16 prdt_offset; 645 646 utrdlp = hba->utrdl; 647 cmd_desc_dma_addr = (dma_addr_t)hba->ucdl; 648 649 utrdlp->command_desc_base_addr_lo = 650 cpu_to_le32(lower_32_bits(cmd_desc_dma_addr)); 651 utrdlp->command_desc_base_addr_hi = 652 cpu_to_le32(upper_32_bits(cmd_desc_dma_addr)); 653 654 response_offset = offsetof(struct utp_transfer_cmd_desc, response_upiu); 655 prdt_offset = offsetof(struct utp_transfer_cmd_desc, prd_table); 656 657 utrdlp->response_upiu_offset = cpu_to_le16(response_offset >> 2); 658 utrdlp->prd_table_offset = cpu_to_le16(prdt_offset >> 2); 659 utrdlp->response_upiu_length = cpu_to_le16(ALIGNED_UPIU_SIZE >> 2); 660 661 hba->ucd_req_ptr = (struct utp_upiu_req *)hba->ucdl; 662 hba->ucd_rsp_ptr = 663 (struct utp_upiu_rsp *)&hba->ucdl->response_upiu; 664 hba->ucd_prdt_ptr = 665 (struct ufshcd_sg_entry *)&hba->ucdl->prd_table; 666 } 667 668 /** 669 * ufshcd_memory_alloc - allocate memory for host memory space data structures 670 */ 671 static int ufshcd_memory_alloc(struct ufs_hba *hba) 672 { 673 /* Allocate one Transfer Request Descriptor 674 * Should be aligned to 1k boundary. 675 */ 676 hba->utrdl = memalign(1024, sizeof(struct utp_transfer_req_desc)); 677 if (!hba->utrdl) { 678 dev_err(hba->dev, "Transfer Descriptor memory allocation failed\n"); 679 return -ENOMEM; 680 } 681 682 /* Allocate one Command Descriptor 683 * Should be aligned to 1k boundary. 684 */ 685 hba->ucdl = memalign(1024, sizeof(struct utp_transfer_cmd_desc)); 686 if (!hba->ucdl) { 687 dev_err(hba->dev, "Command descriptor memory allocation failed\n"); 688 return -ENOMEM; 689 } 690 691 hba->dev_desc = memalign(ARCH_DMA_MINALIGN, sizeof(struct ufs_device_descriptor)); 692 if (!hba->dev_desc) { 693 dev_err(hba->dev, "memory allocation failed\n"); 694 return -ENOMEM; 695 } 696 697 #if defined(CONFIG_SUPPORT_USBPLUG) 698 hba->rc_desc = memalign(ARCH_DMA_MINALIGN, sizeof(struct ufs_configuration_descriptor)); 699 hba->wc_desc = memalign(ARCH_DMA_MINALIGN, sizeof(struct ufs_configuration_descriptor)); 700 hba->geo_desc = memalign(ARCH_DMA_MINALIGN, sizeof(struct ufs_geometry_descriptor)); 701 if (!hba->rc_desc || !hba->wc_desc || !hba->geo_desc) { 702 dev_err(hba->dev, "memory allocation failed\n"); 703 return -ENOMEM; 704 } 705 #endif 706 return 0; 707 } 708 709 /** 710 * ufshcd_get_intr_mask - Get the interrupt bit mask 711 */ 712 static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba) 713 { 714 u32 intr_mask = 0; 715 716 switch (hba->version) { 717 case UFSHCI_VERSION_10: 718 intr_mask = INTERRUPT_MASK_ALL_VER_10; 719 break; 720 case UFSHCI_VERSION_11: 721 case UFSHCI_VERSION_20: 722 intr_mask = INTERRUPT_MASK_ALL_VER_11; 723 break; 724 case UFSHCI_VERSION_21: 725 default: 726 intr_mask = INTERRUPT_MASK_ALL_VER_21; 727 break; 728 } 729 730 return intr_mask; 731 } 732 733 /** 734 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA 735 */ 736 static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba) 737 { 738 return ufshcd_readl(hba, REG_UFS_VERSION); 739 } 740 741 /** 742 * ufshcd_get_upmcrs - Get the power mode change request status 743 */ 744 static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba) 745 { 746 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7; 747 } 748 749 /** 750 * ufshcd_cache_flush_and_invalidate - Flush and invalidate cache 751 * 752 * Flush and invalidate cache in aligned address..address+size range. 753 * The invalidation is in place to avoid stale data in cache. 754 */ 755 static void ufshcd_cache_flush_and_invalidate(void *addr, unsigned long size) 756 { 757 uintptr_t aaddr = (uintptr_t)addr & ~(ARCH_DMA_MINALIGN - 1); 758 unsigned long asize = ALIGN(size, ARCH_DMA_MINALIGN); 759 760 flush_dcache_range(aaddr, aaddr + asize); 761 invalidate_dcache_range(aaddr, aaddr + asize); 762 } 763 764 /** 765 * ufshcd_prepare_req_desc_hdr() - Fills the requests header 766 * descriptor according to request 767 */ 768 static void ufshcd_prepare_req_desc_hdr(struct utp_transfer_req_desc *req_desc, 769 u32 *upiu_flags, 770 enum dma_data_direction cmd_dir) 771 { 772 u32 data_direction; 773 u32 dword_0; 774 775 if (cmd_dir == DMA_FROM_DEVICE) { 776 data_direction = UTP_DEVICE_TO_HOST; 777 *upiu_flags = UPIU_CMD_FLAGS_READ; 778 } else if (cmd_dir == DMA_TO_DEVICE) { 779 data_direction = UTP_HOST_TO_DEVICE; 780 *upiu_flags = UPIU_CMD_FLAGS_WRITE; 781 } else { 782 data_direction = UTP_NO_DATA_TRANSFER; 783 *upiu_flags = UPIU_CMD_FLAGS_NONE; 784 } 785 786 dword_0 = data_direction | (0x1 << UPIU_COMMAND_TYPE_OFFSET); 787 788 /* Enable Interrupt for command */ 789 dword_0 |= UTP_REQ_DESC_INT_CMD; 790 791 /* Transfer request descriptor header fields */ 792 req_desc->header.dword_0 = cpu_to_le32(dword_0); 793 /* dword_1 is reserved, hence it is set to 0 */ 794 req_desc->header.dword_1 = 0; 795 /* 796 * assigning invalid value for command status. Controller 797 * updates OCS on command completion, with the command 798 * status 799 */ 800 req_desc->header.dword_2 = 801 cpu_to_le32(OCS_INVALID_COMMAND_STATUS); 802 /* dword_3 is reserved, hence it is set to 0 */ 803 req_desc->header.dword_3 = 0; 804 805 req_desc->prd_table_length = 0; 806 807 ufshcd_cache_flush_and_invalidate(req_desc, sizeof(*req_desc)); 808 } 809 810 static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba, 811 u32 upiu_flags) 812 { 813 struct utp_upiu_req *ucd_req_ptr = hba->ucd_req_ptr; 814 struct ufs_query *query = &hba->dev_cmd.query; 815 u16 len = be16_to_cpu(query->request.upiu_req.length); 816 817 /* Query request header */ 818 ucd_req_ptr->header.dword_0 = 819 UPIU_HEADER_DWORD(UPIU_TRANSACTION_QUERY_REQ, 820 upiu_flags, 0, TASK_TAG); 821 ucd_req_ptr->header.dword_1 = 822 UPIU_HEADER_DWORD(0, query->request.query_func, 823 0, 0); 824 825 /* Data segment length only need for WRITE_DESC */ 826 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC) 827 ucd_req_ptr->header.dword_2 = 828 UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len); 829 else 830 ucd_req_ptr->header.dword_2 = 0; 831 832 /* Copy the Query Request buffer as is */ 833 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req, QUERY_OSF_SIZE); 834 835 /* Copy the Descriptor */ 836 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC) { 837 memcpy(ucd_req_ptr + 1, query->descriptor, len); 838 ufshcd_cache_flush_and_invalidate(ucd_req_ptr, 839 ALIGN(sizeof(*ucd_req_ptr) + len, ARCH_DMA_MINALIGN)); 840 } else { 841 ufshcd_cache_flush_and_invalidate(ucd_req_ptr, sizeof(*ucd_req_ptr)); 842 } 843 844 memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 845 ufshcd_cache_flush_and_invalidate(hba->ucd_rsp_ptr, sizeof(*hba->ucd_rsp_ptr)); 846 } 847 848 static inline void ufshcd_prepare_utp_nop_upiu(struct ufs_hba *hba) 849 { 850 struct utp_upiu_req *ucd_req_ptr = hba->ucd_req_ptr; 851 852 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req)); 853 854 /* command descriptor fields */ 855 ucd_req_ptr->header.dword_0 = 856 UPIU_HEADER_DWORD(UPIU_TRANSACTION_NOP_OUT, 0, 0, TASK_TAG); 857 /* clear rest of the fields of basic header */ 858 ucd_req_ptr->header.dword_1 = 0; 859 ucd_req_ptr->header.dword_2 = 0; 860 861 memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 862 863 ufshcd_cache_flush_and_invalidate(ucd_req_ptr, sizeof(*ucd_req_ptr)); 864 ufshcd_cache_flush_and_invalidate(hba->ucd_rsp_ptr, sizeof(*hba->ucd_rsp_ptr)); 865 } 866 867 /** 868 * ufshcd_comp_devman_upiu - UFS Protocol Information Unit(UPIU) 869 * for Device Management Purposes 870 */ 871 static int ufshcd_comp_devman_upiu(struct ufs_hba *hba, 872 enum dev_cmd_type cmd_type) 873 { 874 u32 upiu_flags; 875 int ret = 0; 876 struct utp_transfer_req_desc *req_desc = hba->utrdl; 877 878 hba->dev_cmd.type = cmd_type; 879 880 ufshcd_prepare_req_desc_hdr(req_desc, &upiu_flags, DMA_NONE); 881 switch (cmd_type) { 882 case DEV_CMD_TYPE_QUERY: 883 ufshcd_prepare_utp_query_req_upiu(hba, upiu_flags); 884 break; 885 case DEV_CMD_TYPE_NOP: 886 ufshcd_prepare_utp_nop_upiu(hba); 887 break; 888 default: 889 ret = -EINVAL; 890 } 891 892 return ret; 893 } 894 895 static int ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag) 896 { 897 unsigned long start; 898 u32 intr_status; 899 u32 enabled_intr_status; 900 901 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL); 902 903 start = get_timer(0); 904 do { 905 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 906 enabled_intr_status = intr_status & hba->intr_mask; 907 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS); 908 909 if (get_timer(start) > QUERY_REQ_TIMEOUT) { 910 dev_err(hba->dev, 911 "Timedout waiting for UTP response\n"); 912 913 return -ETIMEDOUT; 914 } 915 916 if (enabled_intr_status & UFSHCD_ERROR_MASK) { 917 dev_err(hba->dev, "Error in status:%08x\n", 918 enabled_intr_status); 919 920 return -1; 921 } 922 } while (!(enabled_intr_status & UTP_TRANSFER_REQ_COMPL)); 923 924 return 0; 925 } 926 927 /** 928 * ufshcd_get_req_rsp - returns the TR response transaction type 929 */ 930 static inline int ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr) 931 { 932 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24; 933 } 934 935 /** 936 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status 937 * 938 */ 939 static inline int ufshcd_get_tr_ocs(struct ufs_hba *hba) 940 { 941 return le32_to_cpu(hba->utrdl->header.dword_2) & MASK_OCS; 942 } 943 944 static inline int ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr) 945 { 946 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT; 947 } 948 949 static int ufshcd_check_query_response(struct ufs_hba *hba) 950 { 951 struct ufs_query_res *query_res = &hba->dev_cmd.query.response; 952 953 /* Get the UPIU response */ 954 query_res->response = ufshcd_get_rsp_upiu_result(hba->ucd_rsp_ptr) >> 955 UPIU_RSP_CODE_OFFSET; 956 return query_res->response; 957 } 958 959 /** 960 * ufshcd_copy_query_response() - Copy the Query Response and the data 961 * descriptor 962 */ 963 static int ufshcd_copy_query_response(struct ufs_hba *hba) 964 { 965 struct ufs_query_res *query_res = &hba->dev_cmd.query.response; 966 967 memcpy(&query_res->upiu_res, &hba->ucd_rsp_ptr->qr, QUERY_OSF_SIZE); 968 969 /* Get the descriptor */ 970 if (hba->dev_cmd.query.descriptor && 971 hba->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) { 972 u8 *descp = (u8 *)hba->ucd_rsp_ptr + 973 GENERAL_UPIU_REQUEST_SIZE; 974 u16 resp_len; 975 u16 buf_len; 976 977 /* data segment length */ 978 resp_len = be32_to_cpu(hba->ucd_rsp_ptr->header.dword_2) & 979 MASK_QUERY_DATA_SEG_LEN; 980 buf_len = 981 be16_to_cpu(hba->dev_cmd.query.request.upiu_req.length); 982 if (likely(buf_len >= resp_len)) { 983 int size = ALIGN(GENERAL_UPIU_REQUEST_SIZE + resp_len, ARCH_DMA_MINALIGN); 984 985 invalidate_dcache_range((uintptr_t)hba->ucd_rsp_ptr, (uintptr_t)hba->ucd_rsp_ptr + size); 986 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len); 987 } else { 988 dev_warn(hba->dev, 989 "%s: Response size is bigger than buffer", 990 __func__); 991 return -EINVAL; 992 } 993 } 994 995 return 0; 996 } 997 998 /** 999 * ufshcd_exec_dev_cmd - API for sending device management requests 1000 */ 1001 int ufshcd_exec_dev_cmd(struct ufs_hba *hba, enum dev_cmd_type cmd_type, int timeout) 1002 { 1003 int err; 1004 int resp; 1005 1006 err = ufshcd_comp_devman_upiu(hba, cmd_type); 1007 if (err) 1008 return err; 1009 1010 err = ufshcd_send_command(hba, TASK_TAG); 1011 if (err) 1012 return err; 1013 1014 err = ufshcd_get_tr_ocs(hba); 1015 if (err) { 1016 dev_err(hba->dev, "Error in OCS:%d\n", err); 1017 return -EINVAL; 1018 } 1019 1020 resp = ufshcd_get_req_rsp(hba->ucd_rsp_ptr); 1021 switch (resp) { 1022 case UPIU_TRANSACTION_NOP_IN: 1023 break; 1024 case UPIU_TRANSACTION_QUERY_RSP: 1025 err = ufshcd_check_query_response(hba); 1026 if (!err) 1027 err = ufshcd_copy_query_response(hba); 1028 break; 1029 case UPIU_TRANSACTION_REJECT_UPIU: 1030 /* TODO: handle Reject UPIU Response */ 1031 err = -EPERM; 1032 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n", 1033 __func__); 1034 break; 1035 default: 1036 err = -EINVAL; 1037 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n", 1038 __func__, resp); 1039 } 1040 1041 return err; 1042 } 1043 1044 /** 1045 * ufshcd_init_query() - init the query response and request parameters 1046 */ 1047 static inline void ufshcd_init_query(struct ufs_hba *hba, 1048 struct ufs_query_req **request, 1049 struct ufs_query_res **response, 1050 enum query_opcode opcode, 1051 u8 idn, u8 index, u8 selector) 1052 { 1053 *request = &hba->dev_cmd.query.request; 1054 *response = &hba->dev_cmd.query.response; 1055 memset(*request, 0, sizeof(struct ufs_query_req)); 1056 memset(*response, 0, sizeof(struct ufs_query_res)); 1057 (*request)->upiu_req.opcode = opcode; 1058 (*request)->upiu_req.idn = idn; 1059 (*request)->upiu_req.index = index; 1060 (*request)->upiu_req.selector = selector; 1061 } 1062 1063 /** 1064 * ufshcd_query_flag() - API function for sending flag query requests 1065 */ 1066 int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode, 1067 enum flag_idn idn, bool *flag_res) 1068 { 1069 struct ufs_query_req *request = NULL; 1070 struct ufs_query_res *response = NULL; 1071 int err, index = 0, selector = 0; 1072 int timeout = QUERY_REQ_TIMEOUT; 1073 1074 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 1075 selector); 1076 1077 switch (opcode) { 1078 case UPIU_QUERY_OPCODE_SET_FLAG: 1079 case UPIU_QUERY_OPCODE_CLEAR_FLAG: 1080 case UPIU_QUERY_OPCODE_TOGGLE_FLAG: 1081 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 1082 break; 1083 case UPIU_QUERY_OPCODE_READ_FLAG: 1084 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 1085 if (!flag_res) { 1086 /* No dummy reads */ 1087 dev_err(hba->dev, "%s: Invalid argument for read request\n", 1088 __func__); 1089 err = -EINVAL; 1090 goto out; 1091 } 1092 break; 1093 default: 1094 dev_err(hba->dev, 1095 "%s: Expected query flag opcode but got = %d\n", 1096 __func__, opcode); 1097 err = -EINVAL; 1098 goto out; 1099 } 1100 1101 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout); 1102 1103 if (err) { 1104 dev_err(hba->dev, 1105 "%s: Sending flag query for idn %d failed, err = %d\n", 1106 __func__, idn, err); 1107 goto out; 1108 } 1109 1110 if (flag_res) 1111 *flag_res = (be32_to_cpu(response->upiu_res.value) & 1112 MASK_QUERY_UPIU_FLAG_LOC) & 0x1; 1113 1114 out: 1115 return err; 1116 } 1117 1118 static int ufshcd_query_flag_retry(struct ufs_hba *hba, 1119 enum query_opcode opcode, 1120 enum flag_idn idn, bool *flag_res) 1121 { 1122 int ret; 1123 int retries; 1124 1125 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) { 1126 ret = ufshcd_query_flag(hba, opcode, idn, flag_res); 1127 if (ret) 1128 dev_dbg(hba->dev, 1129 "%s: failed with error %d, retries %d\n", 1130 __func__, ret, retries); 1131 else 1132 break; 1133 } 1134 1135 if (ret) 1136 dev_err(hba->dev, 1137 "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n", 1138 __func__, opcode, idn, ret, retries); 1139 return ret; 1140 } 1141 1142 static int __ufshcd_query_descriptor(struct ufs_hba *hba, 1143 enum query_opcode opcode, 1144 enum desc_idn idn, u8 index, u8 selector, 1145 u8 *desc_buf, int *buf_len) 1146 { 1147 struct ufs_query_req *request = NULL; 1148 struct ufs_query_res *response = NULL; 1149 int err; 1150 1151 if (!desc_buf) { 1152 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n", 1153 __func__, opcode); 1154 err = -EINVAL; 1155 goto out; 1156 } 1157 1158 if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) { 1159 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n", 1160 __func__, *buf_len); 1161 err = -EINVAL; 1162 goto out; 1163 } 1164 1165 ufshcd_init_query(hba, &request, &response, opcode, idn, index, selector); 1166 hba->dev_cmd.query.descriptor = desc_buf; 1167 request->upiu_req.length = cpu_to_be16(*buf_len); 1168 1169 switch (opcode) { 1170 case UPIU_QUERY_OPCODE_WRITE_DESC: 1171 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 1172 break; 1173 case UPIU_QUERY_OPCODE_READ_DESC: 1174 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 1175 break; 1176 default: 1177 dev_err(hba->dev, "%s: Expected query descriptor opcode but got = 0x%.2x\n", 1178 __func__, opcode); 1179 err = -EINVAL; 1180 goto out; 1181 } 1182 1183 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 1184 1185 if (err) { 1186 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n", 1187 __func__, opcode, idn, index, err); 1188 goto out; 1189 } 1190 1191 hba->dev_cmd.query.descriptor = NULL; 1192 *buf_len = be16_to_cpu(response->upiu_res.length); 1193 1194 out: 1195 return err; 1196 } 1197 1198 /** 1199 * ufshcd_query_descriptor_retry - API function for sending descriptor requests 1200 */ 1201 int ufshcd_query_descriptor_retry(struct ufs_hba *hba, enum query_opcode opcode, 1202 enum desc_idn idn, u8 index, u8 selector, 1203 u8 *desc_buf, int *buf_len) 1204 { 1205 int err; 1206 int retries; 1207 1208 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) { 1209 err = __ufshcd_query_descriptor(hba, opcode, idn, index, 1210 selector, desc_buf, buf_len); 1211 if (!err || err == -EINVAL) 1212 break; 1213 } 1214 1215 return err; 1216 } 1217 1218 /** 1219 * ufshcd_read_desc_length - read the specified descriptor length from header 1220 */ 1221 int ufshcd_read_desc_length(struct ufs_hba *hba, enum desc_idn desc_id, 1222 int desc_index, int *desc_length) 1223 { 1224 int ret; 1225 u8 header[QUERY_DESC_HDR_SIZE]; 1226 int header_len = QUERY_DESC_HDR_SIZE; 1227 1228 if (desc_id >= QUERY_DESC_IDN_MAX) 1229 return -EINVAL; 1230 1231 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC, 1232 desc_id, desc_index, 0, header, 1233 &header_len); 1234 1235 if (ret) { 1236 dev_err(hba->dev, "%s: Failed to get descriptor header id %d\n", 1237 __func__, desc_id); 1238 return ret; 1239 } else if (desc_id != header[QUERY_DESC_DESC_TYPE_OFFSET]) { 1240 dev_warn(hba->dev, "%s: descriptor header id %d and desc_id %d mismatch\n", 1241 __func__, header[QUERY_DESC_DESC_TYPE_OFFSET], 1242 desc_id); 1243 ret = -EINVAL; 1244 } 1245 1246 *desc_length = header[QUERY_DESC_LENGTH_OFFSET]; 1247 1248 return ret; 1249 } 1250 1251 static void ufshcd_init_desc_sizes(struct ufs_hba *hba) 1252 { 1253 int err; 1254 1255 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_DEVICE, 0, 1256 &hba->desc_size.dev_desc); 1257 if (err) 1258 hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE; 1259 1260 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_POWER, 0, 1261 &hba->desc_size.pwr_desc); 1262 if (err) 1263 hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE; 1264 1265 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_INTERCONNECT, 0, 1266 &hba->desc_size.interc_desc); 1267 if (err) 1268 hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE; 1269 1270 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_CONFIGURATION, 0, 1271 &hba->desc_size.conf_desc); 1272 if (err) 1273 hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE; 1274 1275 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_UNIT, 0, 1276 &hba->desc_size.unit_desc); 1277 if (err) 1278 hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE; 1279 1280 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_GEOMETRY, 0, 1281 &hba->desc_size.geom_desc); 1282 if (err) 1283 hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE; 1284 1285 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_HEALTH, 0, 1286 &hba->desc_size.hlth_desc); 1287 if (err) 1288 hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE; 1289 } 1290 1291 /** 1292 * ufshcd_map_desc_id_to_length - map descriptor IDN to its length 1293 * 1294 */ 1295 int ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id, 1296 int *desc_len) 1297 { 1298 switch (desc_id) { 1299 case QUERY_DESC_IDN_DEVICE: 1300 *desc_len = hba->desc_size.dev_desc; 1301 break; 1302 case QUERY_DESC_IDN_POWER: 1303 *desc_len = hba->desc_size.pwr_desc; 1304 break; 1305 case QUERY_DESC_IDN_GEOMETRY: 1306 *desc_len = hba->desc_size.geom_desc; 1307 break; 1308 case QUERY_DESC_IDN_CONFIGURATION: 1309 *desc_len = hba->desc_size.conf_desc; 1310 break; 1311 case QUERY_DESC_IDN_UNIT: 1312 *desc_len = hba->desc_size.unit_desc; 1313 break; 1314 case QUERY_DESC_IDN_INTERCONNECT: 1315 *desc_len = hba->desc_size.interc_desc; 1316 break; 1317 case QUERY_DESC_IDN_STRING: 1318 *desc_len = QUERY_DESC_MAX_SIZE; 1319 break; 1320 case QUERY_DESC_IDN_HEALTH: 1321 *desc_len = hba->desc_size.hlth_desc; 1322 break; 1323 case QUERY_DESC_IDN_RFU_0: 1324 case QUERY_DESC_IDN_RFU_1: 1325 *desc_len = 0; 1326 break; 1327 default: 1328 *desc_len = 0; 1329 return -EINVAL; 1330 } 1331 return 0; 1332 } 1333 EXPORT_SYMBOL(ufshcd_map_desc_id_to_length); 1334 1335 /** 1336 * ufshcd_read_desc_param - read the specified descriptor parameter 1337 * 1338 */ 1339 int ufshcd_read_desc_param(struct ufs_hba *hba, enum desc_idn desc_id, 1340 int desc_index, u8 param_offset, u8 *param_read_buf, 1341 u8 param_size) 1342 { 1343 int ret; 1344 u8 *desc_buf; 1345 int buff_len; 1346 bool is_kmalloc = true; 1347 1348 /* Safety check */ 1349 if (desc_id >= QUERY_DESC_IDN_MAX || !param_size) 1350 return -EINVAL; 1351 1352 /* Get the max length of descriptor from structure filled up at probe 1353 * time. 1354 */ 1355 ret = ufshcd_map_desc_id_to_length(hba, desc_id, &buff_len); 1356 1357 /* Sanity checks */ 1358 if (ret || !buff_len) { 1359 dev_err(hba->dev, "%s: Failed to get full descriptor length\n", 1360 __func__); 1361 return ret; 1362 } 1363 1364 /* Check whether we need temp memory */ 1365 if (param_offset != 0 || param_size < buff_len) { 1366 desc_buf = kmalloc(buff_len, GFP_KERNEL); 1367 if (!desc_buf) 1368 return -ENOMEM; 1369 } else { 1370 desc_buf = param_read_buf; 1371 is_kmalloc = false; 1372 } 1373 1374 /* Request for full descriptor */ 1375 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC, 1376 desc_id, desc_index, 0, desc_buf, 1377 &buff_len); 1378 1379 if (ret) { 1380 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d\n", 1381 __func__, desc_id, desc_index, param_offset, ret); 1382 goto out; 1383 } 1384 1385 /* Sanity check */ 1386 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) { 1387 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header\n", 1388 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]); 1389 ret = -EINVAL; 1390 goto out; 1391 } 1392 1393 /* Check wherher we will not copy more data, than available */ 1394 if (is_kmalloc && param_size > buff_len) 1395 param_size = buff_len; 1396 1397 if (is_kmalloc) 1398 memcpy(param_read_buf, &desc_buf[param_offset], param_size); 1399 out: 1400 if (is_kmalloc) 1401 kfree(desc_buf); 1402 return ret; 1403 } 1404 1405 /* replace non-printable or non-ASCII characters with spaces */ 1406 static inline void ufshcd_remove_non_printable(uint8_t *val) 1407 { 1408 if (!val) 1409 return; 1410 1411 if (*val < 0x20 || *val > 0x7e) 1412 *val = ' '; 1413 } 1414 1415 /** 1416 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power 1417 * state) and waits for it to take effect. 1418 * 1419 */ 1420 static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd) 1421 { 1422 unsigned long start = 0; 1423 u8 status; 1424 int ret; 1425 1426 ret = ufshcd_send_uic_cmd(hba, cmd); 1427 if (ret) { 1428 dev_err(hba->dev, 1429 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n", 1430 cmd->command, cmd->argument3, ret); 1431 1432 return ret; 1433 } 1434 1435 start = get_timer(0); 1436 do { 1437 status = ufshcd_get_upmcrs(hba); 1438 if (get_timer(start) > UFS_UIC_CMD_TIMEOUT) { 1439 dev_err(hba->dev, 1440 "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n", 1441 cmd->command, status); 1442 ret = (status != PWR_OK) ? status : -1; 1443 break; 1444 } 1445 } while (status != PWR_LOCAL); 1446 1447 return ret; 1448 } 1449 1450 /** 1451 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode change 1452 * using DME_SET primitives. 1453 */ 1454 static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode) 1455 { 1456 struct uic_command uic_cmd = {0}; 1457 int ret; 1458 1459 uic_cmd.command = UIC_CMD_DME_SET; 1460 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE); 1461 uic_cmd.argument3 = mode; 1462 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 1463 1464 return ret; 1465 } 1466 1467 static 1468 void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufs_hba *hba, 1469 struct scsi_cmd *pccb, u32 upiu_flags) 1470 { 1471 struct utp_upiu_req *ucd_req_ptr = hba->ucd_req_ptr; 1472 unsigned int cdb_len; 1473 1474 /* command descriptor fields */ 1475 ucd_req_ptr->header.dword_0 = 1476 UPIU_HEADER_DWORD(UPIU_TRANSACTION_COMMAND, upiu_flags, 1477 pccb->lun, TASK_TAG); 1478 ucd_req_ptr->header.dword_1 = 1479 UPIU_HEADER_DWORD(UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0); 1480 1481 /* Total EHS length and Data segment length will be zero */ 1482 ucd_req_ptr->header.dword_2 = 0; 1483 1484 ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(pccb->datalen); 1485 1486 cdb_len = min_t(unsigned short, pccb->cmdlen, UFS_CDB_SIZE); 1487 memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE); 1488 memcpy(ucd_req_ptr->sc.cdb, pccb->cmd, cdb_len); 1489 1490 memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 1491 ufshcd_cache_flush_and_invalidate(ucd_req_ptr, sizeof(*ucd_req_ptr)); 1492 ufshcd_cache_flush_and_invalidate(hba->ucd_rsp_ptr, sizeof(*hba->ucd_rsp_ptr)); 1493 } 1494 1495 static inline void prepare_prdt_desc(struct ufshcd_sg_entry *entry, 1496 unsigned char *buf, ulong len) 1497 { 1498 entry->size = cpu_to_le32(len) | GENMASK(1, 0); 1499 entry->base_addr = cpu_to_le32(lower_32_bits((unsigned long)buf)); 1500 entry->upper_addr = cpu_to_le32(upper_32_bits((unsigned long)buf)); 1501 } 1502 1503 static void prepare_prdt_table(struct ufs_hba *hba, struct scsi_cmd *pccb) 1504 { 1505 struct utp_transfer_req_desc *req_desc = hba->utrdl; 1506 struct ufshcd_sg_entry *prd_table = hba->ucd_prdt_ptr; 1507 uintptr_t aaddr = (uintptr_t)(pccb->pdata) & ~(ARCH_DMA_MINALIGN - 1); 1508 ulong datalen = pccb->datalen; 1509 int table_length; 1510 u8 *buf; 1511 int i; 1512 1513 if (!datalen) { 1514 req_desc->prd_table_length = 0; 1515 ufshcd_cache_flush_and_invalidate(req_desc, sizeof(*req_desc)); 1516 return; 1517 } 1518 1519 if (pccb->dma_dir == DMA_TO_DEVICE) { /* Write to device */ 1520 flush_dcache_range(aaddr, ALIGN(aaddr + datalen + ARCH_DMA_MINALIGN - 1, ARCH_DMA_MINALIGN)); 1521 } 1522 1523 /* In any case, invalidate cache to avoid stale data in it. */ 1524 invalidate_dcache_range(aaddr, ALIGN(aaddr + datalen + ARCH_DMA_MINALIGN - 1, ARCH_DMA_MINALIGN)); 1525 1526 table_length = DIV_ROUND_UP(pccb->datalen, MAX_PRDT_ENTRY); 1527 buf = pccb->pdata; 1528 i = table_length; 1529 while (--i) { 1530 prepare_prdt_desc(&prd_table[table_length - i - 1], buf, 1531 MAX_PRDT_ENTRY - 1); 1532 buf += MAX_PRDT_ENTRY; 1533 datalen -= MAX_PRDT_ENTRY; 1534 } 1535 1536 prepare_prdt_desc(&prd_table[table_length - i - 1], buf, datalen - 1); 1537 1538 req_desc->prd_table_length = table_length; 1539 ufshcd_cache_flush_and_invalidate(prd_table, sizeof(*prd_table) * table_length); 1540 ufshcd_cache_flush_and_invalidate(req_desc, sizeof(*req_desc)); 1541 } 1542 1543 int ufs_send_scsi_cmd(struct ufs_hba *hba, struct scsi_cmd *pccb) 1544 { 1545 struct utp_transfer_req_desc *req_desc = hba->utrdl; 1546 u32 upiu_flags; 1547 int ocs, result = 0, retry_count = 3; 1548 u8 scsi_status; 1549 1550 if (hba->quirks & UFSDEV_QUIRK_LUN_IN_SCSI_COMMANDS) 1551 pccb->cmd[1] &= 0x1F; 1552 1553 retry: 1554 ufshcd_prepare_req_desc_hdr(req_desc, &upiu_flags, pccb->dma_dir); 1555 ufshcd_prepare_utp_scsi_cmd_upiu(hba, pccb, upiu_flags); 1556 prepare_prdt_table(hba, pccb); 1557 1558 if (ufshcd_send_command(hba, TASK_TAG) == -ETIMEDOUT && retry_count) { 1559 retry_count--; 1560 goto retry; 1561 } 1562 1563 ocs = ufshcd_get_tr_ocs(hba); 1564 switch (ocs) { 1565 case OCS_SUCCESS: 1566 result = ufshcd_get_req_rsp(hba->ucd_rsp_ptr); 1567 switch (result) { 1568 case UPIU_TRANSACTION_RESPONSE: 1569 result = ufshcd_get_rsp_upiu_result(hba->ucd_rsp_ptr); 1570 1571 scsi_status = result & MASK_SCSI_STATUS; 1572 if (pccb->cmd[0] == SCSI_TST_U_RDY && scsi_status) { 1573 /* Test ready cmd will fail with Phison UFS, break to continue */ 1574 if (retry_count) { 1575 retry_count--; 1576 goto retry; 1577 } 1578 break; 1579 } 1580 if (scsi_status) 1581 return -EINVAL; 1582 1583 break; 1584 case UPIU_TRANSACTION_REJECT_UPIU: 1585 /* TODO: handle Reject UPIU Response */ 1586 dev_err(hba->dev, 1587 "Reject UPIU not fully implemented\n"); 1588 return -EINVAL; 1589 default: 1590 dev_err(hba->dev, 1591 "Unexpected request response code = %x\n", 1592 result); 1593 return -EINVAL; 1594 } 1595 break; 1596 default: 1597 dev_err(hba->dev, "OCS error from controller = %x\n", ocs); 1598 return -EINVAL; 1599 } 1600 1601 return 0; 1602 } 1603 1604 static int ufs_scsi_exec(struct udevice *scsi_dev, struct scsi_cmd *pccb) 1605 { 1606 struct ufs_hba *hba = dev_get_uclass_priv(scsi_dev->parent); 1607 1608 return ufs_send_scsi_cmd(hba, pccb); 1609 } 1610 1611 static inline int ufshcd_read_desc(struct ufs_hba *hba, enum desc_idn desc_id, 1612 int desc_index, u8 *buf, u32 size) 1613 { 1614 return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size); 1615 } 1616 1617 static int ufshcd_read_device_desc(struct ufs_hba *hba, u8 *buf, u32 size) 1618 { 1619 return ufshcd_read_desc(hba, QUERY_DESC_IDN_DEVICE, 0, buf, size); 1620 } 1621 1622 /** 1623 * ufshcd_read_string_desc - read string descriptor 1624 * 1625 */ 1626 int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index, 1627 u8 *buf, u32 size, bool ascii) 1628 { 1629 int err = 0; 1630 1631 err = ufshcd_read_desc(hba, QUERY_DESC_IDN_STRING, desc_index, buf, 1632 size); 1633 1634 if (err) { 1635 dev_err(hba->dev, "%s: reading String Desc failed after %d retries. err = %d\n", 1636 __func__, QUERY_REQ_RETRIES, err); 1637 goto out; 1638 } 1639 1640 if (ascii) { 1641 int desc_len; 1642 int ascii_len; 1643 int i; 1644 u8 *buff_ascii; 1645 1646 desc_len = buf[0]; 1647 /* remove header and divide by 2 to move from UTF16 to UTF8 */ 1648 ascii_len = (desc_len - QUERY_DESC_HDR_SIZE) / 2 + 1; 1649 if (size < ascii_len + QUERY_DESC_HDR_SIZE) { 1650 dev_err(hba->dev, "%s: buffer allocated size is too small\n", 1651 __func__); 1652 err = -ENOMEM; 1653 goto out; 1654 } 1655 1656 buff_ascii = kmalloc(ALIGN(ascii_len, ARCH_DMA_MINALIGN), GFP_KERNEL); 1657 if (!buff_ascii) { 1658 err = -ENOMEM; 1659 goto out; 1660 } 1661 1662 /* 1663 * the descriptor contains string in UTF16 format 1664 * we need to convert to utf-8 so it can be displayed 1665 */ 1666 utf16_to_utf8(buff_ascii, 1667 (uint16_t *)&buf[QUERY_DESC_HDR_SIZE], ascii_len); 1668 1669 /* replace non-printable or non-ASCII characters with spaces */ 1670 for (i = 0; i < ascii_len; i++) 1671 ufshcd_remove_non_printable(&buff_ascii[i]); 1672 1673 memset(buf + QUERY_DESC_HDR_SIZE, 0, 1674 size - QUERY_DESC_HDR_SIZE); 1675 memcpy(buf + QUERY_DESC_HDR_SIZE, buff_ascii, ascii_len); 1676 buf[QUERY_DESC_LENGTH_OFFSET] = ascii_len + QUERY_DESC_HDR_SIZE; 1677 kfree(buff_ascii); 1678 } 1679 out: 1680 return err; 1681 } 1682 1683 static int ufs_get_device_desc(struct ufs_hba *hba, struct ufs_device_descriptor *dev_desc) 1684 { 1685 int err; 1686 size_t buff_len; 1687 1688 buff_len = sizeof(*dev_desc); 1689 if (buff_len > hba->desc_size.dev_desc) 1690 buff_len = hba->desc_size.dev_desc; 1691 1692 err = ufshcd_read_device_desc(hba, (u8 *)dev_desc, buff_len); 1693 if (err) 1694 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n", 1695 __func__, err); 1696 1697 return err; 1698 } 1699 1700 /** 1701 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device 1702 */ 1703 static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba) 1704 { 1705 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info; 1706 1707 if (hba->max_pwr_info.is_valid) 1708 return 0; 1709 1710 pwr_info->pwr_tx = FAST_MODE; 1711 pwr_info->pwr_rx = FAST_MODE; 1712 pwr_info->hs_rate = PA_HS_MODE_B; 1713 1714 /* Get the connected lane count */ 1715 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES), 1716 &pwr_info->lane_rx); 1717 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 1718 &pwr_info->lane_tx); 1719 1720 if (!pwr_info->lane_rx || !pwr_info->lane_tx) { 1721 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n", 1722 __func__, pwr_info->lane_rx, pwr_info->lane_tx); 1723 return -EINVAL; 1724 } 1725 1726 /* 1727 * First, get the maximum gears of HS speed. 1728 * If a zero value, it means there is no HSGEAR capability. 1729 * Then, get the maximum gears of PWM speed. 1730 */ 1731 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx); 1732 if (!pwr_info->gear_rx) { 1733 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), 1734 &pwr_info->gear_rx); 1735 if (!pwr_info->gear_rx) { 1736 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n", 1737 __func__, pwr_info->gear_rx); 1738 return -EINVAL; 1739 } 1740 pwr_info->pwr_rx = SLOW_MODE; 1741 } 1742 1743 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), 1744 &pwr_info->gear_tx); 1745 if (!pwr_info->gear_tx) { 1746 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), 1747 &pwr_info->gear_tx); 1748 if (!pwr_info->gear_tx) { 1749 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n", 1750 __func__, pwr_info->gear_tx); 1751 return -EINVAL; 1752 } 1753 pwr_info->pwr_tx = SLOW_MODE; 1754 } 1755 1756 hba->max_pwr_info.is_valid = true; 1757 return 0; 1758 } 1759 1760 static int ufshcd_change_power_mode(struct ufs_hba *hba, 1761 struct ufs_pa_layer_attr *pwr_mode) 1762 { 1763 int ret; 1764 1765 /* if already configured to the requested pwr_mode */ 1766 if (pwr_mode->gear_rx == hba->pwr_info.gear_rx && 1767 pwr_mode->gear_tx == hba->pwr_info.gear_tx && 1768 pwr_mode->lane_rx == hba->pwr_info.lane_rx && 1769 pwr_mode->lane_tx == hba->pwr_info.lane_tx && 1770 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx && 1771 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx && 1772 pwr_mode->hs_rate == hba->pwr_info.hs_rate) { 1773 dev_dbg(hba->dev, "%s: power already configured\n", __func__); 1774 return 0; 1775 } 1776 1777 /* 1778 * Configure attributes for power mode change with below. 1779 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION, 1780 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION, 1781 * - PA_HSSERIES 1782 */ 1783 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx); 1784 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES), 1785 pwr_mode->lane_rx); 1786 if (pwr_mode->pwr_rx == FASTAUTO_MODE || pwr_mode->pwr_rx == FAST_MODE) 1787 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE); 1788 else 1789 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE); 1790 1791 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx); 1792 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES), 1793 pwr_mode->lane_tx); 1794 if (pwr_mode->pwr_tx == FASTAUTO_MODE || pwr_mode->pwr_tx == FAST_MODE) 1795 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE); 1796 else 1797 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE); 1798 1799 if (pwr_mode->pwr_rx == FASTAUTO_MODE || 1800 pwr_mode->pwr_tx == FASTAUTO_MODE || 1801 pwr_mode->pwr_rx == FAST_MODE || 1802 pwr_mode->pwr_tx == FAST_MODE) 1803 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES), 1804 pwr_mode->hs_rate); 1805 1806 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4 | 1807 pwr_mode->pwr_tx); 1808 1809 if (ret) { 1810 dev_err(hba->dev, 1811 "%s: power mode change failed %d\n", __func__, ret); 1812 1813 return ret; 1814 } 1815 1816 /* Copy new Power Mode to power info */ 1817 memcpy(&hba->pwr_info, pwr_mode, sizeof(struct ufs_pa_layer_attr)); 1818 1819 return ret; 1820 } 1821 1822 /** 1823 * ufshcd_verify_dev_init() - Verify device initialization 1824 * 1825 */ 1826 static int ufshcd_verify_dev_init(struct ufs_hba *hba) 1827 { 1828 int retries; 1829 int err; 1830 1831 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) { 1832 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP, 1833 NOP_OUT_TIMEOUT); 1834 if (!err || err == -ETIMEDOUT) 1835 break; 1836 1837 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err); 1838 } 1839 1840 if (err) 1841 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err); 1842 1843 return err; 1844 } 1845 1846 /** 1847 * ufshcd_complete_dev_init() - checks device readiness 1848 */ 1849 static int ufshcd_complete_dev_init(struct ufs_hba *hba) 1850 { 1851 unsigned long start = 0; 1852 int i; 1853 int err; 1854 bool flag_res = 1; 1855 1856 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG, 1857 QUERY_FLAG_IDN_FDEVICEINIT, NULL); 1858 if (err) { 1859 dev_err(hba->dev, 1860 "%s setting fDeviceInit flag failed with error %d\n", 1861 __func__, err); 1862 goto out; 1863 } 1864 1865 /* poll for max. 1500ms for fDeviceInit flag to clear */ 1866 start = get_timer(0); 1867 for (i = 0; i < 3000 && !err && flag_res; i++) { 1868 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG, 1869 QUERY_FLAG_IDN_FDEVICEINIT, 1870 &flag_res); 1871 if (get_timer(start) > FDEVICEINIT_COMPL_TIMEOUT) 1872 break; 1873 udelay(500); 1874 } 1875 1876 if (err) 1877 dev_err(hba->dev, 1878 "%s reading fDeviceInit flag failed with error %d\n", 1879 __func__, err); 1880 else if (flag_res) 1881 dev_err(hba->dev, 1882 "%s fDeviceInit was not cleared by the device\n", 1883 __func__); 1884 1885 out: 1886 return err; 1887 } 1888 1889 static void ufshcd_def_desc_sizes(struct ufs_hba *hba) 1890 { 1891 hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE; 1892 hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE; 1893 hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE; 1894 hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE; 1895 hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE; 1896 hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE; 1897 hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE; 1898 } 1899 1900 int _ufs_start(struct ufs_hba *hba) 1901 { 1902 int ret; 1903 1904 ret = ufshcd_link_startup(hba); 1905 if (ret) 1906 return ret; 1907 1908 ret = ufshcd_verify_dev_init(hba); 1909 if (ret) 1910 return ret; 1911 1912 ret = ufshcd_complete_dev_init(hba); 1913 if (ret) 1914 return ret; 1915 1916 /* Init check for device descriptor sizes */ 1917 ufshcd_init_desc_sizes(hba); 1918 1919 ret = ufs_get_device_desc(hba, hba->dev_desc); 1920 if (ret) { 1921 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n", 1922 __func__, ret); 1923 1924 return ret; 1925 } 1926 1927 if (hba->dev_desc->w_spec_version == 0x1002) 1928 hba->quirks |= UFSDEV_QUIRK_LUN_IN_SCSI_COMMANDS; 1929 1930 if (hba->dev_desc->w_spec_version == 0x2002) 1931 if (hba->dev_desc->w_manufacturer_id == 0x250A || 1932 hba->dev_desc->w_manufacturer_id == 0x9802) 1933 hba->quirks |= UFSDEV_QUIRK_LUN_IN_SCSI_COMMANDS; 1934 1935 return ret; 1936 } 1937 1938 int ufs_start(struct ufs_hba *hba) 1939 { 1940 int ret; 1941 1942 ret = _ufs_start(hba); 1943 if (ret) 1944 return ret; 1945 1946 #if defined(CONFIG_SUPPORT_USBPLUG) 1947 ret = ufs_create_partition_inventory(hba); 1948 if (ret) { 1949 dev_err(hba->dev, "%s: Failed to creat partition. err = %d\n", __func__, ret); 1950 return ret; 1951 } 1952 #endif 1953 if (ufshcd_get_max_pwr_mode(hba)) { 1954 dev_err(hba->dev, 1955 "%s: Failed getting max supported power mode\n", 1956 __func__); 1957 } else { 1958 ret = ufshcd_change_power_mode(hba, &hba->max_pwr_info.info); 1959 if (ret) { 1960 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n", 1961 __func__, ret); 1962 1963 return ret; 1964 } 1965 1966 printf("Device at %s up at:", hba->dev->name); 1967 ufshcd_print_pwr_info(hba); 1968 } 1969 1970 #if defined(CONFIG_ROCKCHIP_UFS_RPMB) 1971 ufs_rpmb_init(hba); 1972 #endif 1973 1974 return 0; 1975 } 1976 1977 int ufshcd_probe(struct udevice *ufs_dev, struct ufs_hba_ops *hba_ops) 1978 { 1979 struct ufs_hba *hba = dev_get_uclass_priv(ufs_dev); 1980 struct scsi_platdata *scsi_plat; 1981 struct udevice *scsi_dev; 1982 int err; 1983 1984 device_find_first_child(ufs_dev, &scsi_dev); 1985 if (!scsi_dev) 1986 return -ENODEV; 1987 1988 scsi_plat = dev_get_uclass_platdata(scsi_dev); 1989 scsi_plat->max_id = UFSHCD_MAX_ID; 1990 scsi_plat->max_lun = UFS_MAX_LUNS; 1991 //scsi_plat->max_bytes_per_req = UFS_MAX_BYTES; 1992 1993 hba->dev = ufs_dev; 1994 hba->ops = hba_ops; 1995 hba->mmio_base = (void *)dev_read_addr(ufs_dev); 1996 1997 /* Set descriptor lengths to specification defaults */ 1998 ufshcd_def_desc_sizes(hba); 1999 2000 ufshcd_ops_init(hba); 2001 2002 /* Read capabilties registers */ 2003 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES); 2004 2005 /* Get UFS version supported by the controller */ 2006 hba->version = ufshcd_get_ufs_version(hba); 2007 if (hba->version != UFSHCI_VERSION_10 && 2008 hba->version != UFSHCI_VERSION_11 && 2009 hba->version != UFSHCI_VERSION_20 && 2010 hba->version != UFSHCI_VERSION_21) 2011 dev_err(hba->dev, "invalid UFS version 0x%x\n", 2012 hba->version); 2013 2014 /* Get Interrupt bit mask per version */ 2015 hba->intr_mask = ufshcd_get_intr_mask(hba); 2016 2017 /* Allocate memory for host memory space */ 2018 err = ufshcd_memory_alloc(hba); 2019 if (err) { 2020 dev_err(hba->dev, "Memory allocation failed\n"); 2021 return err; 2022 } 2023 2024 /* Configure Local data structures */ 2025 ufshcd_host_memory_configure(hba); 2026 2027 /* 2028 * In order to avoid any spurious interrupt immediately after 2029 * registering UFS controller interrupt handler, clear any pending UFS 2030 * interrupt status and disable all the UFS interrupts. 2031 */ 2032 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS), 2033 REG_INTERRUPT_STATUS); 2034 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE); 2035 2036 err = ufshcd_hba_enable(hba); 2037 if (err) { 2038 dev_err(hba->dev, "Host controller enable failed\n"); 2039 return err; 2040 } 2041 2042 err = ufs_start(hba); 2043 if (err) 2044 return err; 2045 2046 return 0; 2047 } 2048 2049 int ufs_scsi_bind(struct udevice *ufs_dev, struct udevice **scsi_devp) 2050 { 2051 int ret = device_bind_driver(ufs_dev, "ufs_scsi", "ufs_scsi", 2052 scsi_devp); 2053 2054 return ret; 2055 } 2056 2057 static struct scsi_ops ufs_ops = { 2058 .exec = ufs_scsi_exec, 2059 }; 2060 2061 int ufs_probe_dev(int index) 2062 { 2063 struct udevice *dev; 2064 2065 return uclass_get_device(UCLASS_UFS, index, &dev); 2066 } 2067 2068 int ufs_probe(void) 2069 { 2070 struct udevice *dev; 2071 int ret, i; 2072 2073 for (i = 0;; i++) { 2074 ret = uclass_get_device(UCLASS_UFS, i, &dev); 2075 if (ret == -ENODEV) 2076 break; 2077 } 2078 2079 return 0; 2080 } 2081 2082 U_BOOT_DRIVER(ufs_scsi) = { 2083 .id = UCLASS_SCSI, 2084 .name = "ufs_scsi", 2085 .ops = &ufs_ops, 2086 }; 2087