1 // SPDX-License-Identifier: GPL-2.0+ 2 /** 3 * ufs.c - Universal Flash Subsystem (UFS) driver 4 * 5 * Taken from Linux Kernel v5.2 (drivers/scsi/ufs/ufshcd.c) and ported 6 * to u-boot. 7 * 8 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com 9 */ 10 #include <charset.h> 11 #include <common.h> 12 #include <dm.h> 13 #include <log.h> 14 #include <dm/lists.h> 15 #include <dm/device-internal.h> 16 #include <malloc.h> 17 #include <hexdump.h> 18 #include <scsi.h> 19 #include <asm/io.h> 20 #include <asm/dma-mapping.h> 21 #include <linux/bitops.h> 22 #include <linux/delay.h> 23 24 #include "ufs.h" 25 26 #define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\ 27 UTP_TASK_REQ_COMPL |\ 28 UFSHCD_ERROR_MASK) 29 /* maximum number of link-startup retries */ 30 #define DME_LINKSTARTUP_RETRIES 3 31 32 /* maximum number of retries for a general UIC command */ 33 #define UFS_UIC_COMMAND_RETRIES 3 34 35 /* Query request retries */ 36 #define QUERY_REQ_RETRIES 3 37 /* Query request timeout */ 38 #define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */ 39 40 /* maximum timeout in ms for a general UIC command */ 41 #define UFS_UIC_CMD_TIMEOUT 1000 42 /* NOP OUT retries waiting for NOP IN response */ 43 #define NOP_OUT_RETRIES 10 44 /* Timeout after 30 msecs if NOP OUT hangs without response */ 45 #define NOP_OUT_TIMEOUT 30 /* msecs */ 46 47 /* Only use one Task Tag for all requests */ 48 #define TASK_TAG 0 49 50 /* Expose the flag value from utp_upiu_query.value */ 51 #define MASK_QUERY_UPIU_FLAG_LOC 0xFF 52 53 #define MAX_PRDT_ENTRY 262144 54 55 /* maximum bytes per request */ 56 #define UFS_MAX_BYTES (128 * 256 * 1024) 57 58 static inline bool ufshcd_is_hba_active(struct ufs_hba *hba); 59 static inline void ufshcd_hba_stop(struct ufs_hba *hba); 60 static int ufshcd_hba_enable(struct ufs_hba *hba); 61 62 /* 63 * ufshcd_wait_for_register - wait for register value to change 64 */ 65 static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask, 66 u32 val, unsigned long timeout_ms) 67 { 68 int err = 0; 69 unsigned long start = get_timer(0); 70 71 /* ignore bits that we don't intend to wait on */ 72 val = val & mask; 73 74 while ((ufshcd_readl(hba, reg) & mask) != val) { 75 if (get_timer(start) > timeout_ms) { 76 if ((ufshcd_readl(hba, reg) & mask) != val) 77 err = -ETIMEDOUT; 78 break; 79 } 80 } 81 82 return err; 83 } 84 85 /** 86 * ufshcd_init_pwr_info - setting the POR (power on reset) 87 * values in hba power info 88 */ 89 static void ufshcd_init_pwr_info(struct ufs_hba *hba) 90 { 91 hba->pwr_info.gear_rx = UFS_PWM_G1; 92 hba->pwr_info.gear_tx = UFS_PWM_G1; 93 hba->pwr_info.lane_rx = 1; 94 hba->pwr_info.lane_tx = 1; 95 hba->pwr_info.pwr_rx = SLOWAUTO_MODE; 96 hba->pwr_info.pwr_tx = SLOWAUTO_MODE; 97 hba->pwr_info.hs_rate = 0; 98 } 99 100 /** 101 * ufshcd_print_pwr_info - print power params as saved in hba 102 * power info 103 */ 104 static void ufshcd_print_pwr_info(struct ufs_hba *hba) 105 { 106 static const char * const names[] = { 107 "INVALID MODE", 108 "FAST MODE", 109 "SLOW_MODE", 110 "INVALID MODE", 111 "FASTAUTO_MODE", 112 "SLOWAUTO_MODE", 113 "INVALID MODE", 114 }; 115 116 dev_err(hba->dev, "[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n", 117 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx, 118 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx, 119 names[hba->pwr_info.pwr_rx], 120 names[hba->pwr_info.pwr_tx], 121 hba->pwr_info.hs_rate); 122 } 123 124 /** 125 * ufshcd_ready_for_uic_cmd - Check if controller is ready 126 * to accept UIC commands 127 */ 128 static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba) 129 { 130 if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY) 131 return true; 132 else 133 return false; 134 } 135 136 /** 137 * ufshcd_get_uic_cmd_result - Get the UIC command result 138 */ 139 static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba) 140 { 141 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) & 142 MASK_UIC_COMMAND_RESULT; 143 } 144 145 /** 146 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command 147 */ 148 static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba) 149 { 150 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3); 151 } 152 153 /** 154 * ufshcd_is_device_present - Check if any device connected to 155 * the host controller 156 */ 157 static inline bool ufshcd_is_device_present(struct ufs_hba *hba) 158 { 159 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & 160 DEVICE_PRESENT) ? true : false; 161 } 162 163 /** 164 * ufshcd_send_uic_cmd - UFS Interconnect layer command API 165 * 166 */ 167 static int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 168 { 169 unsigned long start = 0; 170 u32 intr_status; 171 u32 enabled_intr_status; 172 173 if (!ufshcd_ready_for_uic_cmd(hba)) { 174 dev_err(hba->dev, 175 "Controller not ready to accept UIC commands\n"); 176 return -EIO; 177 } 178 179 debug("sending uic command:%d\n", uic_cmd->command); 180 181 /* Write Args */ 182 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1); 183 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2); 184 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3); 185 186 /* Write UIC Cmd */ 187 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK, 188 REG_UIC_COMMAND); 189 190 start = get_timer(0); 191 do { 192 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 193 enabled_intr_status = intr_status & hba->intr_mask; 194 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS); 195 196 if (get_timer(start) > UFS_UIC_CMD_TIMEOUT) { 197 dev_err(hba->dev, 198 "Timedout waiting for UIC response\n"); 199 200 return -ETIMEDOUT; 201 } 202 203 if (enabled_intr_status & UFSHCD_ERROR_MASK) { 204 dev_err(hba->dev, "Error in status:%08x\n", 205 enabled_intr_status); 206 207 return -1; 208 } 209 } while (!(enabled_intr_status & UFSHCD_UIC_MASK)); 210 211 uic_cmd->argument2 = ufshcd_get_uic_cmd_result(hba); 212 uic_cmd->argument3 = ufshcd_get_dme_attr_val(hba); 213 214 debug("Sent successfully\n"); 215 216 return 0; 217 } 218 219 /** 220 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET 221 * 222 */ 223 int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, u8 attr_set, 224 u32 mib_val, u8 peer) 225 { 226 struct uic_command uic_cmd = {0}; 227 static const char *const action[] = { 228 "dme-set", 229 "dme-peer-set" 230 }; 231 const char *set = action[!!peer]; 232 int ret; 233 int retries = UFS_UIC_COMMAND_RETRIES; 234 235 uic_cmd.command = peer ? 236 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET; 237 uic_cmd.argument1 = attr_sel; 238 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set); 239 uic_cmd.argument3 = mib_val; 240 241 do { 242 /* for peer attributes we retry upon failure */ 243 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 244 if (ret) 245 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n", 246 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret); 247 } while (ret && peer && --retries); 248 249 if (ret) 250 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n", 251 set, UIC_GET_ATTR_ID(attr_sel), mib_val, 252 UFS_UIC_COMMAND_RETRIES - retries); 253 254 return ret; 255 } 256 257 /** 258 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET 259 * 260 */ 261 int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, 262 u32 *mib_val, u8 peer) 263 { 264 struct uic_command uic_cmd = {0}; 265 static const char *const action[] = { 266 "dme-get", 267 "dme-peer-get" 268 }; 269 const char *get = action[!!peer]; 270 int ret; 271 int retries = UFS_UIC_COMMAND_RETRIES; 272 273 uic_cmd.command = peer ? 274 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET; 275 uic_cmd.argument1 = attr_sel; 276 277 do { 278 /* for peer attributes we retry upon failure */ 279 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 280 if (ret) 281 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n", 282 get, UIC_GET_ATTR_ID(attr_sel), ret); 283 } while (ret && peer && --retries); 284 285 if (ret) 286 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n", 287 get, UIC_GET_ATTR_ID(attr_sel), 288 UFS_UIC_COMMAND_RETRIES - retries); 289 290 if (mib_val && !ret) 291 *mib_val = uic_cmd.argument3; 292 293 return ret; 294 } 295 296 static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer) 297 { 298 u32 tx_lanes, i, err = 0; 299 300 if (!peer) 301 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 302 &tx_lanes); 303 else 304 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 305 &tx_lanes); 306 for (i = 0; i < tx_lanes; i++) { 307 if (!peer) 308 err = ufshcd_dme_set(hba, 309 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, 310 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), 311 0); 312 else 313 err = ufshcd_dme_peer_set(hba, 314 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, 315 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), 316 0); 317 if (err) { 318 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d\n", 319 __func__, peer, i, err); 320 break; 321 } 322 } 323 324 return err; 325 } 326 327 static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba) 328 { 329 return ufshcd_disable_tx_lcc(hba, true); 330 } 331 332 /** 333 * ufshcd_dme_link_startup - Notify Unipro to perform link startup 334 * 335 */ 336 static int ufshcd_dme_link_startup(struct ufs_hba *hba) 337 { 338 struct uic_command uic_cmd = {0}; 339 int ret; 340 341 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP; 342 343 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 344 if (ret) 345 dev_dbg(hba->dev, 346 "dme-link-startup: error code %d\n", ret); 347 return ret; 348 } 349 350 int ufshcd_dme_enable(struct ufs_hba *hba) 351 { 352 struct uic_command uic_cmd = {0}; 353 int ret; 354 355 uic_cmd.command = UIC_CMD_DME_ENABLE; 356 357 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 358 if (ret) 359 dev_err(hba->dev, 360 "dme-enable: error code %d\n", ret); 361 return ret; 362 } 363 364 int ufshcd_dme_reset(struct ufs_hba *hba) 365 { 366 struct uic_command uic_cmd = {0}; 367 int ret; 368 369 uic_cmd.command = UIC_CMD_DME_RESET; 370 371 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 372 if (ret) 373 dev_err(hba->dev, 374 "dme-reset: error code %d\n", ret); 375 return ret; 376 } 377 378 /** 379 * ufshcd_disable_intr_aggr - Disables interrupt aggregation. 380 * 381 */ 382 static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba) 383 { 384 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 385 } 386 387 /** 388 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY 389 */ 390 static inline int ufshcd_get_lists_status(u32 reg) 391 { 392 return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY); 393 } 394 395 /** 396 * ufshcd_enable_run_stop_reg - Enable run-stop registers, 397 * When run-stop registers are set to 1, it indicates the 398 * host controller that it can process the requests 399 */ 400 static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba) 401 { 402 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT, 403 REG_UTP_TASK_REQ_LIST_RUN_STOP); 404 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT, 405 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP); 406 } 407 408 /** 409 * ufshcd_enable_intr - enable interrupts 410 */ 411 static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs) 412 { 413 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 414 u32 rw; 415 416 if (hba->version == UFSHCI_VERSION_10) { 417 rw = set & INTERRUPT_MASK_RW_VER_10; 418 set = rw | ((set ^ intrs) & intrs); 419 } else { 420 set |= intrs; 421 } 422 423 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); 424 425 hba->intr_mask = set; 426 } 427 428 /** 429 * ufshcd_make_hba_operational - Make UFS controller operational 430 * 431 * To bring UFS host controller to operational state, 432 * 1. Enable required interrupts 433 * 2. Configure interrupt aggregation 434 * 3. Program UTRL and UTMRL base address 435 * 4. Configure run-stop-registers 436 * 437 */ 438 static int ufshcd_make_hba_operational(struct ufs_hba *hba) 439 { 440 int err = 0; 441 u32 reg; 442 443 /* Enable required interrupts */ 444 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS); 445 446 /* Disable interrupt aggregation */ 447 ufshcd_disable_intr_aggr(hba); 448 449 /* Configure UTRL and UTMRL base address registers */ 450 ufshcd_writel(hba, lower_32_bits((dma_addr_t)hba->utrdl), 451 REG_UTP_TRANSFER_REQ_LIST_BASE_L); 452 ufshcd_writel(hba, upper_32_bits((dma_addr_t)hba->utrdl), 453 REG_UTP_TRANSFER_REQ_LIST_BASE_H); 454 ufshcd_writel(hba, lower_32_bits((dma_addr_t)hba->utmrdl), 455 REG_UTP_TASK_REQ_LIST_BASE_L); 456 ufshcd_writel(hba, upper_32_bits((dma_addr_t)hba->utmrdl), 457 REG_UTP_TASK_REQ_LIST_BASE_H); 458 459 /* 460 * UCRDY, UTMRLDY and UTRLRDY bits must be 1 461 */ 462 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS); 463 if (!(ufshcd_get_lists_status(reg))) { 464 ufshcd_enable_run_stop_reg(hba); 465 } else { 466 dev_err(hba->dev, 467 "Host controller not ready to process requests\n"); 468 err = -EIO; 469 goto out; 470 } 471 472 out: 473 return err; 474 } 475 476 /** 477 * ufshcd_link_startup - Initialize unipro link startup 478 */ 479 static int ufshcd_link_startup(struct ufs_hba *hba) 480 { 481 int ret; 482 int retries = DME_LINKSTARTUP_RETRIES; 483 bool link_startup_again = true; 484 485 link_startup: 486 do { 487 ufshcd_ops_link_startup_notify(hba, PRE_CHANGE); 488 489 ret = ufshcd_dme_link_startup(hba); 490 491 /* check if device is detected by inter-connect layer */ 492 if (!ret && !ufshcd_is_device_present(hba)) { 493 dev_err(hba->dev, "%s: Device not present\n", __func__); 494 ret = -ENXIO; 495 goto out; 496 } 497 498 /* 499 * DME link lost indication is only received when link is up, 500 * but we can't be sure if the link is up until link startup 501 * succeeds. So reset the local Uni-Pro and try again. 502 */ 503 if (ret && ufshcd_hba_enable(hba)) 504 goto out; 505 } while (ret && retries--); 506 507 if (ret) 508 /* failed to get the link up... retire */ 509 goto out; 510 511 if (link_startup_again) { 512 link_startup_again = false; 513 retries = DME_LINKSTARTUP_RETRIES; 514 goto link_startup; 515 } 516 517 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */ 518 ufshcd_init_pwr_info(hba); 519 520 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) { 521 ret = ufshcd_disable_device_tx_lcc(hba); 522 if (ret) 523 goto out; 524 } 525 526 /* Include any host controller configuration via UIC commands */ 527 ret = ufshcd_ops_link_startup_notify(hba, POST_CHANGE); 528 if (ret) 529 goto out; 530 531 ret = ufshcd_make_hba_operational(hba); 532 out: 533 if (ret) 534 dev_err(hba->dev, "link startup failed %d\n", ret); 535 536 return ret; 537 } 538 539 /** 540 * ufshcd_hba_stop - Send controller to reset state 541 */ 542 static inline void ufshcd_hba_stop(struct ufs_hba *hba) 543 { 544 int err; 545 546 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE); 547 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE, 548 CONTROLLER_ENABLE, CONTROLLER_DISABLE, 549 10); 550 if (err) 551 dev_err(hba->dev, "%s: Controller disable failed\n", __func__); 552 } 553 554 /** 555 * ufshcd_is_hba_active - Get controller state 556 */ 557 static inline bool ufshcd_is_hba_active(struct ufs_hba *hba) 558 { 559 return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE) 560 ? false : true; 561 } 562 563 /** 564 * ufshcd_hba_start - Start controller initialization sequence 565 */ 566 static inline void ufshcd_hba_start(struct ufs_hba *hba) 567 { 568 ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE); 569 } 570 571 /** 572 * ufshcd_hba_enable - initialize the controller 573 */ 574 static int ufshcd_hba_enable(struct ufs_hba *hba) 575 { 576 int retry; 577 578 if (!ufshcd_is_hba_active(hba)) 579 /* change controller state to "reset state" */ 580 ufshcd_hba_stop(hba); 581 582 ufshcd_ops_hce_enable_notify(hba, PRE_CHANGE); 583 584 /* start controller initialization sequence */ 585 ufshcd_hba_start(hba); 586 587 /* 588 * To initialize a UFS host controller HCE bit must be set to 1. 589 * During initialization the HCE bit value changes from 1->0->1. 590 * When the host controller completes initialization sequence 591 * it sets the value of HCE bit to 1. The same HCE bit is read back 592 * to check if the controller has completed initialization sequence. 593 * So without this delay the value HCE = 1, set in the previous 594 * instruction might be read back. 595 * This delay can be changed based on the controller. 596 */ 597 mdelay(1); 598 599 /* wait for the host controller to complete initialization */ 600 retry = 10; 601 while (ufshcd_is_hba_active(hba)) { 602 if (retry) { 603 retry--; 604 } else { 605 dev_err(hba->dev, "Controller enable failed\n"); 606 return -EIO; 607 } 608 mdelay(5); 609 } 610 611 /* enable UIC related interrupts */ 612 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK); 613 614 ufshcd_ops_hce_enable_notify(hba, POST_CHANGE); 615 616 return 0; 617 } 618 619 /** 620 * ufshcd_host_memory_configure - configure local reference block with 621 * memory offsets 622 */ 623 static void ufshcd_host_memory_configure(struct ufs_hba *hba) 624 { 625 struct utp_transfer_req_desc *utrdlp; 626 dma_addr_t cmd_desc_dma_addr; 627 u16 response_offset; 628 u16 prdt_offset; 629 630 utrdlp = hba->utrdl; 631 cmd_desc_dma_addr = (dma_addr_t)hba->ucdl; 632 633 utrdlp->command_desc_base_addr_lo = 634 cpu_to_le32(lower_32_bits(cmd_desc_dma_addr)); 635 utrdlp->command_desc_base_addr_hi = 636 cpu_to_le32(upper_32_bits(cmd_desc_dma_addr)); 637 638 response_offset = offsetof(struct utp_transfer_cmd_desc, response_upiu); 639 prdt_offset = offsetof(struct utp_transfer_cmd_desc, prd_table); 640 641 utrdlp->response_upiu_offset = cpu_to_le16(response_offset >> 2); 642 utrdlp->prd_table_offset = cpu_to_le16(prdt_offset >> 2); 643 utrdlp->response_upiu_length = cpu_to_le16(ALIGNED_UPIU_SIZE >> 2); 644 645 hba->ucd_req_ptr = (struct utp_upiu_req *)hba->ucdl; 646 hba->ucd_rsp_ptr = 647 (struct utp_upiu_rsp *)&hba->ucdl->response_upiu; 648 hba->ucd_prdt_ptr = 649 (struct ufshcd_sg_entry *)&hba->ucdl->prd_table; 650 } 651 652 /** 653 * ufshcd_memory_alloc - allocate memory for host memory space data structures 654 */ 655 static int ufshcd_memory_alloc(struct ufs_hba *hba) 656 { 657 /* Allocate one Transfer Request Descriptor 658 * Should be aligned to 1k boundary. 659 */ 660 hba->utrdl = memalign(1024, sizeof(struct utp_transfer_req_desc)); 661 if (!hba->utrdl) { 662 dev_err(hba->dev, "Transfer Descriptor memory allocation failed\n"); 663 return -ENOMEM; 664 } 665 666 /* Allocate one Command Descriptor 667 * Should be aligned to 1k boundary. 668 */ 669 hba->ucdl = memalign(1024, sizeof(struct utp_transfer_cmd_desc)); 670 if (!hba->ucdl) { 671 dev_err(hba->dev, "Command descriptor memory allocation failed\n"); 672 return -ENOMEM; 673 } 674 675 hba->dev_desc = memalign(ARCH_DMA_MINALIGN, sizeof(struct ufs_device_descriptor)); 676 if (!hba->dev_desc) { 677 dev_err(hba->dev, "memory allocation failed\n"); 678 return -ENOMEM; 679 } 680 681 return 0; 682 } 683 684 /** 685 * ufshcd_get_intr_mask - Get the interrupt bit mask 686 */ 687 static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba) 688 { 689 u32 intr_mask = 0; 690 691 switch (hba->version) { 692 case UFSHCI_VERSION_10: 693 intr_mask = INTERRUPT_MASK_ALL_VER_10; 694 break; 695 case UFSHCI_VERSION_11: 696 case UFSHCI_VERSION_20: 697 intr_mask = INTERRUPT_MASK_ALL_VER_11; 698 break; 699 case UFSHCI_VERSION_21: 700 default: 701 intr_mask = INTERRUPT_MASK_ALL_VER_21; 702 break; 703 } 704 705 return intr_mask; 706 } 707 708 /** 709 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA 710 */ 711 static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba) 712 { 713 return ufshcd_readl(hba, REG_UFS_VERSION); 714 } 715 716 /** 717 * ufshcd_get_upmcrs - Get the power mode change request status 718 */ 719 static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba) 720 { 721 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7; 722 } 723 724 /** 725 * ufshcd_cache_flush_and_invalidate - Flush and invalidate cache 726 * 727 * Flush and invalidate cache in aligned address..address+size range. 728 * The invalidation is in place to avoid stale data in cache. 729 */ 730 static void ufshcd_cache_flush_and_invalidate(void *addr, unsigned long size) 731 { 732 uintptr_t aaddr = (uintptr_t)addr & ~(ARCH_DMA_MINALIGN - 1); 733 unsigned long asize = ALIGN(size, ARCH_DMA_MINALIGN); 734 735 flush_dcache_range(aaddr, aaddr + asize); 736 invalidate_dcache_range(aaddr, aaddr + asize); 737 } 738 739 /** 740 * ufshcd_prepare_req_desc_hdr() - Fills the requests header 741 * descriptor according to request 742 */ 743 static void ufshcd_prepare_req_desc_hdr(struct utp_transfer_req_desc *req_desc, 744 u32 *upiu_flags, 745 enum dma_data_direction cmd_dir) 746 { 747 u32 data_direction; 748 u32 dword_0; 749 750 if (cmd_dir == DMA_FROM_DEVICE) { 751 data_direction = UTP_DEVICE_TO_HOST; 752 *upiu_flags = UPIU_CMD_FLAGS_READ; 753 } else if (cmd_dir == DMA_TO_DEVICE) { 754 data_direction = UTP_HOST_TO_DEVICE; 755 *upiu_flags = UPIU_CMD_FLAGS_WRITE; 756 } else { 757 data_direction = UTP_NO_DATA_TRANSFER; 758 *upiu_flags = UPIU_CMD_FLAGS_NONE; 759 } 760 761 dword_0 = data_direction | (0x1 << UPIU_COMMAND_TYPE_OFFSET); 762 763 /* Enable Interrupt for command */ 764 dword_0 |= UTP_REQ_DESC_INT_CMD; 765 766 /* Transfer request descriptor header fields */ 767 req_desc->header.dword_0 = cpu_to_le32(dword_0); 768 /* dword_1 is reserved, hence it is set to 0 */ 769 req_desc->header.dword_1 = 0; 770 /* 771 * assigning invalid value for command status. Controller 772 * updates OCS on command completion, with the command 773 * status 774 */ 775 req_desc->header.dword_2 = 776 cpu_to_le32(OCS_INVALID_COMMAND_STATUS); 777 /* dword_3 is reserved, hence it is set to 0 */ 778 req_desc->header.dword_3 = 0; 779 780 req_desc->prd_table_length = 0; 781 782 ufshcd_cache_flush_and_invalidate(req_desc, sizeof(*req_desc)); 783 } 784 785 static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba, 786 u32 upiu_flags) 787 { 788 struct utp_upiu_req *ucd_req_ptr = hba->ucd_req_ptr; 789 struct ufs_query *query = &hba->dev_cmd.query; 790 u16 len = be16_to_cpu(query->request.upiu_req.length); 791 792 /* Query request header */ 793 ucd_req_ptr->header.dword_0 = 794 UPIU_HEADER_DWORD(UPIU_TRANSACTION_QUERY_REQ, 795 upiu_flags, 0, TASK_TAG); 796 ucd_req_ptr->header.dword_1 = 797 UPIU_HEADER_DWORD(0, query->request.query_func, 798 0, 0); 799 800 /* Data segment length only need for WRITE_DESC */ 801 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC) 802 ucd_req_ptr->header.dword_2 = 803 UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len); 804 else 805 ucd_req_ptr->header.dword_2 = 0; 806 807 /* Copy the Query Request buffer as is */ 808 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req, QUERY_OSF_SIZE); 809 810 /* Copy the Descriptor */ 811 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC) { 812 memcpy(ucd_req_ptr + 1, query->descriptor, len); 813 ufshcd_cache_flush_and_invalidate(ucd_req_ptr, 814 ALIGN(sizeof(*ucd_req_ptr) + len, ARCH_DMA_MINALIGN)); 815 } else { 816 ufshcd_cache_flush_and_invalidate(ucd_req_ptr, sizeof(*ucd_req_ptr)); 817 } 818 819 memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 820 ufshcd_cache_flush_and_invalidate(hba->ucd_rsp_ptr, sizeof(*hba->ucd_rsp_ptr)); 821 } 822 823 static inline void ufshcd_prepare_utp_nop_upiu(struct ufs_hba *hba) 824 { 825 struct utp_upiu_req *ucd_req_ptr = hba->ucd_req_ptr; 826 827 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req)); 828 829 /* command descriptor fields */ 830 ucd_req_ptr->header.dword_0 = 831 UPIU_HEADER_DWORD(UPIU_TRANSACTION_NOP_OUT, 0, 0, TASK_TAG); 832 /* clear rest of the fields of basic header */ 833 ucd_req_ptr->header.dword_1 = 0; 834 ucd_req_ptr->header.dword_2 = 0; 835 836 memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 837 838 ufshcd_cache_flush_and_invalidate(ucd_req_ptr, sizeof(*ucd_req_ptr)); 839 ufshcd_cache_flush_and_invalidate(hba->ucd_rsp_ptr, sizeof(*hba->ucd_rsp_ptr)); 840 } 841 842 /** 843 * ufshcd_comp_devman_upiu - UFS Protocol Information Unit(UPIU) 844 * for Device Management Purposes 845 */ 846 static int ufshcd_comp_devman_upiu(struct ufs_hba *hba, 847 enum dev_cmd_type cmd_type) 848 { 849 u32 upiu_flags; 850 int ret = 0; 851 struct utp_transfer_req_desc *req_desc = hba->utrdl; 852 853 hba->dev_cmd.type = cmd_type; 854 855 ufshcd_prepare_req_desc_hdr(req_desc, &upiu_flags, DMA_NONE); 856 switch (cmd_type) { 857 case DEV_CMD_TYPE_QUERY: 858 ufshcd_prepare_utp_query_req_upiu(hba, upiu_flags); 859 break; 860 case DEV_CMD_TYPE_NOP: 861 ufshcd_prepare_utp_nop_upiu(hba); 862 break; 863 default: 864 ret = -EINVAL; 865 } 866 867 return ret; 868 } 869 870 static int ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag) 871 { 872 unsigned long start; 873 u32 intr_status; 874 u32 enabled_intr_status; 875 876 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL); 877 878 start = get_timer(0); 879 do { 880 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 881 enabled_intr_status = intr_status & hba->intr_mask; 882 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS); 883 884 if (get_timer(start) > QUERY_REQ_TIMEOUT) { 885 dev_err(hba->dev, 886 "Timedout waiting for UTP response\n"); 887 888 return -ETIMEDOUT; 889 } 890 891 if (enabled_intr_status & UFSHCD_ERROR_MASK) { 892 dev_err(hba->dev, "Error in status:%08x\n", 893 enabled_intr_status); 894 895 return -1; 896 } 897 } while (!(enabled_intr_status & UTP_TRANSFER_REQ_COMPL)); 898 899 return 0; 900 } 901 902 /** 903 * ufshcd_get_req_rsp - returns the TR response transaction type 904 */ 905 static inline int ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr) 906 { 907 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24; 908 } 909 910 /** 911 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status 912 * 913 */ 914 static inline int ufshcd_get_tr_ocs(struct ufs_hba *hba) 915 { 916 return le32_to_cpu(hba->utrdl->header.dword_2) & MASK_OCS; 917 } 918 919 static inline int ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr) 920 { 921 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT; 922 } 923 924 static int ufshcd_check_query_response(struct ufs_hba *hba) 925 { 926 struct ufs_query_res *query_res = &hba->dev_cmd.query.response; 927 928 /* Get the UPIU response */ 929 query_res->response = ufshcd_get_rsp_upiu_result(hba->ucd_rsp_ptr) >> 930 UPIU_RSP_CODE_OFFSET; 931 return query_res->response; 932 } 933 934 /** 935 * ufshcd_copy_query_response() - Copy the Query Response and the data 936 * descriptor 937 */ 938 static int ufshcd_copy_query_response(struct ufs_hba *hba) 939 { 940 struct ufs_query_res *query_res = &hba->dev_cmd.query.response; 941 942 memcpy(&query_res->upiu_res, &hba->ucd_rsp_ptr->qr, QUERY_OSF_SIZE); 943 944 /* Get the descriptor */ 945 if (hba->dev_cmd.query.descriptor && 946 hba->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) { 947 u8 *descp = (u8 *)hba->ucd_rsp_ptr + 948 GENERAL_UPIU_REQUEST_SIZE; 949 u16 resp_len; 950 u16 buf_len; 951 952 /* data segment length */ 953 resp_len = be32_to_cpu(hba->ucd_rsp_ptr->header.dword_2) & 954 MASK_QUERY_DATA_SEG_LEN; 955 buf_len = 956 be16_to_cpu(hba->dev_cmd.query.request.upiu_req.length); 957 if (likely(buf_len >= resp_len)) { 958 int size = ALIGN(GENERAL_UPIU_REQUEST_SIZE + resp_len, ARCH_DMA_MINALIGN); 959 960 invalidate_dcache_range((uintptr_t)hba->ucd_rsp_ptr, (uintptr_t)hba->ucd_rsp_ptr + size); 961 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len); 962 } else { 963 dev_warn(hba->dev, 964 "%s: Response size is bigger than buffer", 965 __func__); 966 return -EINVAL; 967 } 968 } else if (hba->dev_cmd.query.descriptor && hba->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_ATTR) { 969 u8 *value = (u8 *)&query_res->upiu_res.value; 970 hba->dev_cmd.query.descriptor[0] = value[11]; 971 hba->dev_cmd.query.descriptor[1] = value[10]; 972 hba->dev_cmd.query.descriptor[2] = value[9]; 973 hba->dev_cmd.query.descriptor[3] = value[8]; 974 } 975 976 return 0; 977 } 978 979 /** 980 * ufshcd_exec_dev_cmd - API for sending device management requests 981 */ 982 static int ufshcd_exec_dev_cmd(struct ufs_hba *hba, enum dev_cmd_type cmd_type, 983 int timeout) 984 { 985 int err; 986 int resp; 987 988 err = ufshcd_comp_devman_upiu(hba, cmd_type); 989 if (err) 990 return err; 991 992 err = ufshcd_send_command(hba, TASK_TAG); 993 if (err) 994 return err; 995 996 err = ufshcd_get_tr_ocs(hba); 997 if (err) { 998 dev_err(hba->dev, "Error in OCS:%d\n", err); 999 return -EINVAL; 1000 } 1001 1002 resp = ufshcd_get_req_rsp(hba->ucd_rsp_ptr); 1003 switch (resp) { 1004 case UPIU_TRANSACTION_NOP_IN: 1005 break; 1006 case UPIU_TRANSACTION_QUERY_RSP: 1007 err = ufshcd_check_query_response(hba); 1008 if (!err) 1009 err = ufshcd_copy_query_response(hba); 1010 break; 1011 case UPIU_TRANSACTION_REJECT_UPIU: 1012 /* TODO: handle Reject UPIU Response */ 1013 err = -EPERM; 1014 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n", 1015 __func__); 1016 break; 1017 default: 1018 err = -EINVAL; 1019 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n", 1020 __func__, resp); 1021 } 1022 1023 return err; 1024 } 1025 1026 /** 1027 * ufshcd_init_query() - init the query response and request parameters 1028 */ 1029 static inline void ufshcd_init_query(struct ufs_hba *hba, 1030 struct ufs_query_req **request, 1031 struct ufs_query_res **response, 1032 enum query_opcode opcode, 1033 u8 idn, u8 index, u8 selector) 1034 { 1035 *request = &hba->dev_cmd.query.request; 1036 *response = &hba->dev_cmd.query.response; 1037 memset(*request, 0, sizeof(struct ufs_query_req)); 1038 memset(*response, 0, sizeof(struct ufs_query_res)); 1039 (*request)->upiu_req.opcode = opcode; 1040 (*request)->upiu_req.idn = idn; 1041 (*request)->upiu_req.index = index; 1042 (*request)->upiu_req.selector = selector; 1043 } 1044 1045 /** 1046 * ufshcd_query_flag() - API function for sending flag query requests 1047 */ 1048 int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode, 1049 enum flag_idn idn, bool *flag_res) 1050 { 1051 struct ufs_query_req *request = NULL; 1052 struct ufs_query_res *response = NULL; 1053 int err, index = 0, selector = 0; 1054 int timeout = QUERY_REQ_TIMEOUT; 1055 1056 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 1057 selector); 1058 1059 switch (opcode) { 1060 case UPIU_QUERY_OPCODE_SET_FLAG: 1061 case UPIU_QUERY_OPCODE_CLEAR_FLAG: 1062 case UPIU_QUERY_OPCODE_TOGGLE_FLAG: 1063 case UPIU_QUERY_OPCODE_WRITE_ATTR: 1064 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 1065 break; 1066 case UPIU_QUERY_OPCODE_READ_ATTR: 1067 case UPIU_QUERY_OPCODE_READ_FLAG: 1068 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 1069 if (!flag_res) { 1070 /* No dummy reads */ 1071 dev_err(hba->dev, "%s: Invalid argument for read request\n", 1072 __func__); 1073 err = -EINVAL; 1074 goto out; 1075 } 1076 break; 1077 default: 1078 dev_err(hba->dev, 1079 "%s: Expected query flag opcode but got = %d\n", 1080 __func__, opcode); 1081 err = -EINVAL; 1082 goto out; 1083 } 1084 1085 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout); 1086 1087 if (err) { 1088 dev_err(hba->dev, 1089 "%s: Sending flag query for idn %d failed, err = %d\n", 1090 __func__, idn, err); 1091 goto out; 1092 } 1093 1094 if (flag_res) 1095 *flag_res = (be32_to_cpu(response->upiu_res.value) & 1096 MASK_QUERY_UPIU_FLAG_LOC) & 0x1; 1097 1098 out: 1099 return err; 1100 } 1101 1102 static int ufshcd_query_flag_retry(struct ufs_hba *hba, 1103 enum query_opcode opcode, 1104 enum flag_idn idn, bool *flag_res) 1105 { 1106 int ret; 1107 int retries; 1108 1109 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) { 1110 ret = ufshcd_query_flag(hba, opcode, idn, flag_res); 1111 if (ret) 1112 dev_dbg(hba->dev, 1113 "%s: failed with error %d, retries %d\n", 1114 __func__, ret, retries); 1115 else 1116 break; 1117 } 1118 1119 if (ret) 1120 dev_err(hba->dev, 1121 "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n", 1122 __func__, opcode, idn, ret, retries); 1123 return ret; 1124 } 1125 1126 static int __ufshcd_query_descriptor(struct ufs_hba *hba, 1127 enum query_opcode opcode, 1128 enum desc_idn idn, u8 index, u8 selector, 1129 u8 *desc_buf, int *buf_len) 1130 { 1131 struct ufs_query_req *request = NULL; 1132 struct ufs_query_res *response = NULL; 1133 int err; 1134 1135 if (!desc_buf) { 1136 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n", 1137 __func__, opcode); 1138 err = -EINVAL; 1139 goto out; 1140 } 1141 1142 if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) { 1143 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n", 1144 __func__, *buf_len); 1145 err = -EINVAL; 1146 goto out; 1147 } 1148 1149 ufshcd_init_query(hba, &request, &response, opcode, idn, index, selector); 1150 hba->dev_cmd.query.descriptor = desc_buf; 1151 request->upiu_req.length = cpu_to_be16(*buf_len); 1152 1153 switch (opcode) { 1154 case UPIU_QUERY_OPCODE_WRITE_ATTR: 1155 request->upiu_req.value = (desc_buf[0] << 24 | desc_buf[1] << 16 | desc_buf[2] << 8 | desc_buf[3]); 1156 case UPIU_QUERY_OPCODE_WRITE_DESC: 1157 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 1158 break; 1159 case UPIU_QUERY_OPCODE_READ_ATTR: 1160 case UPIU_QUERY_OPCODE_READ_DESC: 1161 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 1162 break; 1163 default: 1164 dev_err(hba->dev, "%s: Expected query descriptor opcode but got = 0x%.2x\n", 1165 __func__, opcode); 1166 err = -EINVAL; 1167 goto out; 1168 } 1169 1170 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 1171 1172 if (err) { 1173 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n", 1174 __func__, opcode, idn, index, err); 1175 goto out; 1176 } 1177 1178 hba->dev_cmd.query.descriptor = NULL; 1179 *buf_len = be16_to_cpu(response->upiu_res.length); 1180 1181 out: 1182 return err; 1183 } 1184 1185 /** 1186 * ufshcd_query_descriptor_retry - API function for sending descriptor requests 1187 */ 1188 int ufshcd_query_descriptor_retry(struct ufs_hba *hba, enum query_opcode opcode, 1189 enum desc_idn idn, u8 index, u8 selector, 1190 u8 *desc_buf, int *buf_len) 1191 { 1192 int err; 1193 int retries; 1194 1195 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) { 1196 err = __ufshcd_query_descriptor(hba, opcode, idn, index, 1197 selector, desc_buf, buf_len); 1198 if (!err || err == -EINVAL) 1199 break; 1200 } 1201 1202 return err; 1203 } 1204 1205 /** 1206 * ufshcd_read_desc_length - read the specified descriptor length from header 1207 */ 1208 int ufshcd_read_desc_length(struct ufs_hba *hba, enum desc_idn desc_id, 1209 int desc_index, int *desc_length) 1210 { 1211 int ret; 1212 u8 header[QUERY_DESC_HDR_SIZE]; 1213 int header_len = QUERY_DESC_HDR_SIZE; 1214 1215 if (desc_id >= QUERY_DESC_IDN_MAX) 1216 return -EINVAL; 1217 1218 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC, 1219 desc_id, desc_index, 0, header, 1220 &header_len); 1221 1222 if (ret) { 1223 dev_err(hba->dev, "%s: Failed to get descriptor header id %d\n", 1224 __func__, desc_id); 1225 return ret; 1226 } else if (desc_id != header[QUERY_DESC_DESC_TYPE_OFFSET]) { 1227 dev_warn(hba->dev, "%s: descriptor header id %d and desc_id %d mismatch\n", 1228 __func__, header[QUERY_DESC_DESC_TYPE_OFFSET], 1229 desc_id); 1230 ret = -EINVAL; 1231 } 1232 1233 *desc_length = header[QUERY_DESC_LENGTH_OFFSET]; 1234 1235 return ret; 1236 } 1237 1238 static void ufshcd_init_desc_sizes(struct ufs_hba *hba) 1239 { 1240 int err; 1241 1242 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_DEVICE, 0, 1243 &hba->desc_size.dev_desc); 1244 if (err) 1245 hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE; 1246 1247 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_POWER, 0, 1248 &hba->desc_size.pwr_desc); 1249 if (err) 1250 hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE; 1251 1252 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_INTERCONNECT, 0, 1253 &hba->desc_size.interc_desc); 1254 if (err) 1255 hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE; 1256 1257 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_CONFIGURATION, 0, 1258 &hba->desc_size.conf_desc); 1259 if (err) 1260 hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE; 1261 1262 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_UNIT, 0, 1263 &hba->desc_size.unit_desc); 1264 if (err) 1265 hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE; 1266 1267 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_GEOMETRY, 0, 1268 &hba->desc_size.geom_desc); 1269 if (err) 1270 hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE; 1271 1272 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_HEALTH, 0, 1273 &hba->desc_size.hlth_desc); 1274 if (err) 1275 hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE; 1276 } 1277 1278 /** 1279 * ufshcd_map_desc_id_to_length - map descriptor IDN to its length 1280 * 1281 */ 1282 int ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id, 1283 int *desc_len) 1284 { 1285 switch (desc_id) { 1286 case QUERY_DESC_IDN_DEVICE: 1287 *desc_len = hba->desc_size.dev_desc; 1288 break; 1289 case QUERY_DESC_IDN_POWER: 1290 *desc_len = hba->desc_size.pwr_desc; 1291 break; 1292 case QUERY_DESC_IDN_GEOMETRY: 1293 *desc_len = hba->desc_size.geom_desc; 1294 break; 1295 case QUERY_DESC_IDN_CONFIGURATION: 1296 *desc_len = hba->desc_size.conf_desc; 1297 break; 1298 case QUERY_DESC_IDN_UNIT: 1299 *desc_len = hba->desc_size.unit_desc; 1300 break; 1301 case QUERY_DESC_IDN_INTERCONNECT: 1302 *desc_len = hba->desc_size.interc_desc; 1303 break; 1304 case QUERY_DESC_IDN_STRING: 1305 *desc_len = QUERY_DESC_MAX_SIZE; 1306 break; 1307 case QUERY_DESC_IDN_HEALTH: 1308 *desc_len = hba->desc_size.hlth_desc; 1309 break; 1310 case QUERY_DESC_IDN_RFU_0: 1311 case QUERY_DESC_IDN_RFU_1: 1312 *desc_len = 0; 1313 break; 1314 default: 1315 *desc_len = 0; 1316 return -EINVAL; 1317 } 1318 return 0; 1319 } 1320 EXPORT_SYMBOL(ufshcd_map_desc_id_to_length); 1321 1322 /** 1323 * ufshcd_read_desc_param - read the specified descriptor parameter 1324 * 1325 */ 1326 int ufshcd_read_desc_param(struct ufs_hba *hba, enum desc_idn desc_id, 1327 int desc_index, u8 param_offset, u8 *param_read_buf, 1328 u8 param_size) 1329 { 1330 int ret; 1331 u8 *desc_buf; 1332 int buff_len; 1333 bool is_kmalloc = true; 1334 1335 /* Safety check */ 1336 if (desc_id >= QUERY_DESC_IDN_MAX || !param_size) 1337 return -EINVAL; 1338 1339 /* Get the max length of descriptor from structure filled up at probe 1340 * time. 1341 */ 1342 ret = ufshcd_map_desc_id_to_length(hba, desc_id, &buff_len); 1343 1344 /* Sanity checks */ 1345 if (ret || !buff_len) { 1346 dev_err(hba->dev, "%s: Failed to get full descriptor length\n", 1347 __func__); 1348 return ret; 1349 } 1350 1351 /* Check whether we need temp memory */ 1352 if (param_offset != 0 || param_size < buff_len) { 1353 desc_buf = kmalloc(buff_len, GFP_KERNEL); 1354 if (!desc_buf) 1355 return -ENOMEM; 1356 } else { 1357 desc_buf = param_read_buf; 1358 is_kmalloc = false; 1359 } 1360 1361 /* Request for full descriptor */ 1362 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC, 1363 desc_id, desc_index, 0, desc_buf, 1364 &buff_len); 1365 1366 if (ret) { 1367 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d\n", 1368 __func__, desc_id, desc_index, param_offset, ret); 1369 goto out; 1370 } 1371 1372 /* Sanity check */ 1373 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) { 1374 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header\n", 1375 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]); 1376 ret = -EINVAL; 1377 goto out; 1378 } 1379 1380 /* Check wherher we will not copy more data, than available */ 1381 if (is_kmalloc && param_size > buff_len) 1382 param_size = buff_len; 1383 1384 if (is_kmalloc) 1385 memcpy(param_read_buf, &desc_buf[param_offset], param_size); 1386 out: 1387 if (is_kmalloc) 1388 kfree(desc_buf); 1389 return ret; 1390 } 1391 1392 /* replace non-printable or non-ASCII characters with spaces */ 1393 static inline void ufshcd_remove_non_printable(uint8_t *val) 1394 { 1395 if (!val) 1396 return; 1397 1398 if (*val < 0x20 || *val > 0x7e) 1399 *val = ' '; 1400 } 1401 1402 /** 1403 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power 1404 * state) and waits for it to take effect. 1405 * 1406 */ 1407 static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd) 1408 { 1409 unsigned long start = 0; 1410 u8 status; 1411 int ret; 1412 1413 ret = ufshcd_send_uic_cmd(hba, cmd); 1414 if (ret) { 1415 dev_err(hba->dev, 1416 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n", 1417 cmd->command, cmd->argument3, ret); 1418 1419 return ret; 1420 } 1421 1422 start = get_timer(0); 1423 do { 1424 status = ufshcd_get_upmcrs(hba); 1425 if (get_timer(start) > UFS_UIC_CMD_TIMEOUT) { 1426 dev_err(hba->dev, 1427 "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n", 1428 cmd->command, status); 1429 ret = (status != PWR_OK) ? status : -1; 1430 break; 1431 } 1432 } while (status != PWR_LOCAL); 1433 1434 return ret; 1435 } 1436 1437 /** 1438 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode change 1439 * using DME_SET primitives. 1440 */ 1441 static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode) 1442 { 1443 struct uic_command uic_cmd = {0}; 1444 int ret; 1445 1446 uic_cmd.command = UIC_CMD_DME_SET; 1447 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE); 1448 uic_cmd.argument3 = mode; 1449 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 1450 1451 return ret; 1452 } 1453 1454 static 1455 void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufs_hba *hba, 1456 struct scsi_cmd *pccb, u32 upiu_flags) 1457 { 1458 struct utp_upiu_req *ucd_req_ptr = hba->ucd_req_ptr; 1459 unsigned int cdb_len; 1460 1461 /* command descriptor fields */ 1462 ucd_req_ptr->header.dword_0 = 1463 UPIU_HEADER_DWORD(UPIU_TRANSACTION_COMMAND, upiu_flags, 1464 pccb->lun, TASK_TAG); 1465 ucd_req_ptr->header.dword_1 = 1466 UPIU_HEADER_DWORD(UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0); 1467 1468 /* Total EHS length and Data segment length will be zero */ 1469 ucd_req_ptr->header.dword_2 = 0; 1470 1471 ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(pccb->datalen); 1472 1473 cdb_len = min_t(unsigned short, pccb->cmdlen, UFS_CDB_SIZE); 1474 memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE); 1475 memcpy(ucd_req_ptr->sc.cdb, pccb->cmd, cdb_len); 1476 1477 memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 1478 ufshcd_cache_flush_and_invalidate(ucd_req_ptr, sizeof(*ucd_req_ptr)); 1479 ufshcd_cache_flush_and_invalidate(hba->ucd_rsp_ptr, sizeof(*hba->ucd_rsp_ptr)); 1480 } 1481 1482 static inline void prepare_prdt_desc(struct ufshcd_sg_entry *entry, 1483 unsigned char *buf, ulong len) 1484 { 1485 entry->size = cpu_to_le32(len) | GENMASK(1, 0); 1486 entry->base_addr = cpu_to_le32(lower_32_bits((unsigned long)buf)); 1487 entry->upper_addr = cpu_to_le32(upper_32_bits((unsigned long)buf)); 1488 } 1489 1490 static void prepare_prdt_table(struct ufs_hba *hba, struct scsi_cmd *pccb) 1491 { 1492 struct utp_transfer_req_desc *req_desc = hba->utrdl; 1493 struct ufshcd_sg_entry *prd_table = hba->ucd_prdt_ptr; 1494 uintptr_t aaddr = (uintptr_t)(pccb->pdata) & ~(ARCH_DMA_MINALIGN - 1); 1495 ulong datalen = pccb->datalen; 1496 int table_length; 1497 u8 *buf; 1498 int i; 1499 1500 if (!datalen) { 1501 req_desc->prd_table_length = 0; 1502 ufshcd_cache_flush_and_invalidate(req_desc, sizeof(*req_desc)); 1503 return; 1504 } 1505 1506 if (pccb->dma_dir == DMA_TO_DEVICE) { /* Write to device */ 1507 flush_dcache_range(aaddr, ALIGN(aaddr + datalen + ARCH_DMA_MINALIGN - 1, ARCH_DMA_MINALIGN)); 1508 } 1509 1510 /* In any case, invalidate cache to avoid stale data in it. */ 1511 invalidate_dcache_range(aaddr, ALIGN(aaddr + datalen + ARCH_DMA_MINALIGN - 1, ARCH_DMA_MINALIGN)); 1512 1513 table_length = DIV_ROUND_UP(pccb->datalen, MAX_PRDT_ENTRY); 1514 buf = pccb->pdata; 1515 i = table_length; 1516 while (--i) { 1517 prepare_prdt_desc(&prd_table[table_length - i - 1], buf, 1518 MAX_PRDT_ENTRY - 1); 1519 buf += MAX_PRDT_ENTRY; 1520 datalen -= MAX_PRDT_ENTRY; 1521 } 1522 1523 prepare_prdt_desc(&prd_table[table_length - i - 1], buf, datalen - 1); 1524 1525 req_desc->prd_table_length = table_length; 1526 ufshcd_cache_flush_and_invalidate(prd_table, sizeof(*prd_table) * table_length); 1527 ufshcd_cache_flush_and_invalidate(req_desc, sizeof(*req_desc)); 1528 } 1529 1530 static int ufs_scsi_exec(struct udevice *scsi_dev, struct scsi_cmd *pccb) 1531 { 1532 struct ufs_hba *hba = dev_get_uclass_priv(scsi_dev->parent); 1533 struct utp_transfer_req_desc *req_desc = hba->utrdl; 1534 u32 upiu_flags; 1535 int ocs, result = 0; 1536 u8 scsi_status; 1537 1538 ufshcd_prepare_req_desc_hdr(req_desc, &upiu_flags, pccb->dma_dir); 1539 ufshcd_prepare_utp_scsi_cmd_upiu(hba, pccb, upiu_flags); 1540 prepare_prdt_table(hba, pccb); 1541 1542 ufshcd_send_command(hba, TASK_TAG); 1543 1544 ocs = ufshcd_get_tr_ocs(hba); 1545 switch (ocs) { 1546 case OCS_SUCCESS: 1547 result = ufshcd_get_req_rsp(hba->ucd_rsp_ptr); 1548 switch (result) { 1549 case UPIU_TRANSACTION_RESPONSE: 1550 result = ufshcd_get_rsp_upiu_result(hba->ucd_rsp_ptr); 1551 1552 scsi_status = result & MASK_SCSI_STATUS; 1553 if (scsi_status) 1554 return -EINVAL; 1555 1556 break; 1557 case UPIU_TRANSACTION_REJECT_UPIU: 1558 /* TODO: handle Reject UPIU Response */ 1559 dev_err(hba->dev, 1560 "Reject UPIU not fully implemented\n"); 1561 return -EINVAL; 1562 default: 1563 dev_err(hba->dev, 1564 "Unexpected request response code = %x\n", 1565 result); 1566 return -EINVAL; 1567 } 1568 break; 1569 default: 1570 dev_err(hba->dev, "OCS error from controller = %x\n", ocs); 1571 return -EINVAL; 1572 } 1573 1574 return 0; 1575 } 1576 1577 static inline int ufshcd_read_desc(struct ufs_hba *hba, enum desc_idn desc_id, 1578 int desc_index, u8 *buf, u32 size) 1579 { 1580 return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size); 1581 } 1582 1583 static int ufshcd_read_device_desc(struct ufs_hba *hba, u8 *buf, u32 size) 1584 { 1585 return ufshcd_read_desc(hba, QUERY_DESC_IDN_DEVICE, 0, buf, size); 1586 } 1587 1588 /** 1589 * ufshcd_read_string_desc - read string descriptor 1590 * 1591 */ 1592 int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index, 1593 u8 *buf, u32 size, bool ascii) 1594 { 1595 int err = 0; 1596 1597 err = ufshcd_read_desc(hba, QUERY_DESC_IDN_STRING, desc_index, buf, 1598 size); 1599 1600 if (err) { 1601 dev_err(hba->dev, "%s: reading String Desc failed after %d retries. err = %d\n", 1602 __func__, QUERY_REQ_RETRIES, err); 1603 goto out; 1604 } 1605 1606 if (ascii) { 1607 int desc_len; 1608 int ascii_len; 1609 int i; 1610 u8 *buff_ascii; 1611 1612 desc_len = buf[0]; 1613 /* remove header and divide by 2 to move from UTF16 to UTF8 */ 1614 ascii_len = (desc_len - QUERY_DESC_HDR_SIZE) / 2 + 1; 1615 if (size < ascii_len + QUERY_DESC_HDR_SIZE) { 1616 dev_err(hba->dev, "%s: buffer allocated size is too small\n", 1617 __func__); 1618 err = -ENOMEM; 1619 goto out; 1620 } 1621 1622 buff_ascii = kmalloc(ALIGN(ascii_len, ARCH_DMA_MINALIGN), GFP_KERNEL); 1623 if (!buff_ascii) { 1624 err = -ENOMEM; 1625 goto out; 1626 } 1627 1628 /* 1629 * the descriptor contains string in UTF16 format 1630 * we need to convert to utf-8 so it can be displayed 1631 */ 1632 utf16_to_utf8(buff_ascii, 1633 (uint16_t *)&buf[QUERY_DESC_HDR_SIZE], ascii_len); 1634 1635 /* replace non-printable or non-ASCII characters with spaces */ 1636 for (i = 0; i < ascii_len; i++) 1637 ufshcd_remove_non_printable(&buff_ascii[i]); 1638 1639 memset(buf + QUERY_DESC_HDR_SIZE, 0, 1640 size - QUERY_DESC_HDR_SIZE); 1641 memcpy(buf + QUERY_DESC_HDR_SIZE, buff_ascii, ascii_len); 1642 buf[QUERY_DESC_LENGTH_OFFSET] = ascii_len + QUERY_DESC_HDR_SIZE; 1643 kfree(buff_ascii); 1644 } 1645 out: 1646 return err; 1647 } 1648 1649 static int ufs_get_device_desc(struct ufs_hba *hba, struct ufs_device_descriptor *dev_desc) 1650 { 1651 int err; 1652 size_t buff_len; 1653 1654 buff_len = sizeof(*dev_desc); 1655 if (buff_len > hba->desc_size.dev_desc) 1656 buff_len = hba->desc_size.dev_desc; 1657 1658 err = ufshcd_read_device_desc(hba, (u8 *)dev_desc, buff_len); 1659 if (err) 1660 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n", 1661 __func__, err); 1662 1663 return err; 1664 } 1665 1666 /** 1667 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device 1668 */ 1669 static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba) 1670 { 1671 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info; 1672 1673 if (hba->max_pwr_info.is_valid) 1674 return 0; 1675 1676 pwr_info->pwr_tx = FAST_MODE; 1677 pwr_info->pwr_rx = FAST_MODE; 1678 pwr_info->hs_rate = PA_HS_MODE_B; 1679 1680 /* Get the connected lane count */ 1681 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES), 1682 &pwr_info->lane_rx); 1683 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 1684 &pwr_info->lane_tx); 1685 1686 if (!pwr_info->lane_rx || !pwr_info->lane_tx) { 1687 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n", 1688 __func__, pwr_info->lane_rx, pwr_info->lane_tx); 1689 return -EINVAL; 1690 } 1691 1692 /* 1693 * First, get the maximum gears of HS speed. 1694 * If a zero value, it means there is no HSGEAR capability. 1695 * Then, get the maximum gears of PWM speed. 1696 */ 1697 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx); 1698 if (!pwr_info->gear_rx) { 1699 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), 1700 &pwr_info->gear_rx); 1701 if (!pwr_info->gear_rx) { 1702 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n", 1703 __func__, pwr_info->gear_rx); 1704 return -EINVAL; 1705 } 1706 pwr_info->pwr_rx = SLOW_MODE; 1707 } 1708 1709 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), 1710 &pwr_info->gear_tx); 1711 if (!pwr_info->gear_tx) { 1712 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), 1713 &pwr_info->gear_tx); 1714 if (!pwr_info->gear_tx) { 1715 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n", 1716 __func__, pwr_info->gear_tx); 1717 return -EINVAL; 1718 } 1719 pwr_info->pwr_tx = SLOW_MODE; 1720 } 1721 1722 hba->max_pwr_info.is_valid = true; 1723 return 0; 1724 } 1725 1726 static int ufshcd_change_power_mode(struct ufs_hba *hba, 1727 struct ufs_pa_layer_attr *pwr_mode) 1728 { 1729 int ret; 1730 1731 /* if already configured to the requested pwr_mode */ 1732 if (pwr_mode->gear_rx == hba->pwr_info.gear_rx && 1733 pwr_mode->gear_tx == hba->pwr_info.gear_tx && 1734 pwr_mode->lane_rx == hba->pwr_info.lane_rx && 1735 pwr_mode->lane_tx == hba->pwr_info.lane_tx && 1736 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx && 1737 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx && 1738 pwr_mode->hs_rate == hba->pwr_info.hs_rate) { 1739 dev_dbg(hba->dev, "%s: power already configured\n", __func__); 1740 return 0; 1741 } 1742 1743 /* 1744 * Configure attributes for power mode change with below. 1745 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION, 1746 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION, 1747 * - PA_HSSERIES 1748 */ 1749 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx); 1750 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES), 1751 pwr_mode->lane_rx); 1752 if (pwr_mode->pwr_rx == FASTAUTO_MODE || pwr_mode->pwr_rx == FAST_MODE) 1753 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE); 1754 else 1755 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE); 1756 1757 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx); 1758 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES), 1759 pwr_mode->lane_tx); 1760 if (pwr_mode->pwr_tx == FASTAUTO_MODE || pwr_mode->pwr_tx == FAST_MODE) 1761 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE); 1762 else 1763 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE); 1764 1765 if (pwr_mode->pwr_rx == FASTAUTO_MODE || 1766 pwr_mode->pwr_tx == FASTAUTO_MODE || 1767 pwr_mode->pwr_rx == FAST_MODE || 1768 pwr_mode->pwr_tx == FAST_MODE) 1769 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES), 1770 pwr_mode->hs_rate); 1771 1772 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4 | 1773 pwr_mode->pwr_tx); 1774 1775 if (ret) { 1776 dev_err(hba->dev, 1777 "%s: power mode change failed %d\n", __func__, ret); 1778 1779 return ret; 1780 } 1781 1782 /* Copy new Power Mode to power info */ 1783 memcpy(&hba->pwr_info, pwr_mode, sizeof(struct ufs_pa_layer_attr)); 1784 1785 return ret; 1786 } 1787 1788 /** 1789 * ufshcd_verify_dev_init() - Verify device initialization 1790 * 1791 */ 1792 static int ufshcd_verify_dev_init(struct ufs_hba *hba) 1793 { 1794 int retries; 1795 int err; 1796 1797 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) { 1798 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP, 1799 NOP_OUT_TIMEOUT); 1800 if (!err || err == -ETIMEDOUT) 1801 break; 1802 1803 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err); 1804 } 1805 1806 if (err) 1807 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err); 1808 1809 return err; 1810 } 1811 1812 /** 1813 * ufshcd_complete_dev_init() - checks device readiness 1814 */ 1815 static int ufshcd_complete_dev_init(struct ufs_hba *hba) 1816 { 1817 int i; 1818 int err; 1819 bool flag_res = 1; 1820 1821 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG, 1822 QUERY_FLAG_IDN_FDEVICEINIT, NULL); 1823 if (err) { 1824 dev_err(hba->dev, 1825 "%s setting fDeviceInit flag failed with error %d\n", 1826 __func__, err); 1827 goto out; 1828 } 1829 1830 /* poll for max. 1000 iterations for fDeviceInit flag to clear */ 1831 for (i = 0; i < 1000 && !err && flag_res; i++) 1832 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG, 1833 QUERY_FLAG_IDN_FDEVICEINIT, 1834 &flag_res); 1835 1836 if (err) 1837 dev_err(hba->dev, 1838 "%s reading fDeviceInit flag failed with error %d\n", 1839 __func__, err); 1840 else if (flag_res) 1841 dev_err(hba->dev, 1842 "%s fDeviceInit was not cleared by the device\n", 1843 __func__); 1844 1845 out: 1846 return err; 1847 } 1848 1849 static void ufshcd_def_desc_sizes(struct ufs_hba *hba) 1850 { 1851 hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE; 1852 hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE; 1853 hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE; 1854 hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE; 1855 hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE; 1856 hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE; 1857 hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE; 1858 } 1859 1860 int _ufs_start(struct ufs_hba *hba) 1861 { 1862 int ret; 1863 1864 ret = ufshcd_link_startup(hba); 1865 if (ret) 1866 return ret; 1867 1868 ret = ufshcd_verify_dev_init(hba); 1869 if (ret) 1870 return ret; 1871 1872 ret = ufshcd_complete_dev_init(hba); 1873 if (ret) 1874 return ret; 1875 1876 /* Init check for device descriptor sizes */ 1877 ufshcd_init_desc_sizes(hba); 1878 1879 ret = ufs_get_device_desc(hba, hba->dev_desc); 1880 if (ret) { 1881 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n", 1882 __func__, ret); 1883 1884 return ret; 1885 } 1886 1887 return ret; 1888 } 1889 1890 int ufs_start(struct ufs_hba *hba) 1891 { 1892 int ret; 1893 1894 ret = _ufs_start(hba); 1895 if (ret) 1896 return ret; 1897 1898 if (ufshcd_get_max_pwr_mode(hba)) { 1899 dev_err(hba->dev, 1900 "%s: Failed getting max supported power mode\n", 1901 __func__); 1902 } else { 1903 ret = ufshcd_change_power_mode(hba, &hba->max_pwr_info.info); 1904 if (ret) { 1905 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n", 1906 __func__, ret); 1907 1908 return ret; 1909 } 1910 1911 printf("Device at %s up at:", hba->dev->name); 1912 ufshcd_print_pwr_info(hba); 1913 } 1914 1915 return 0; 1916 } 1917 1918 int ufshcd_probe(struct udevice *ufs_dev, struct ufs_hba_ops *hba_ops) 1919 { 1920 struct ufs_hba *hba = dev_get_uclass_priv(ufs_dev); 1921 struct scsi_platdata *scsi_plat; 1922 struct udevice *scsi_dev; 1923 int err; 1924 1925 device_find_first_child(ufs_dev, &scsi_dev); 1926 if (!scsi_dev) 1927 return -ENODEV; 1928 1929 scsi_plat = dev_get_uclass_platdata(scsi_dev); 1930 scsi_plat->max_id = UFSHCD_MAX_ID; 1931 scsi_plat->max_lun = UFS_MAX_LUNS; 1932 //scsi_plat->max_bytes_per_req = UFS_MAX_BYTES; 1933 1934 hba->dev = ufs_dev; 1935 hba->ops = hba_ops; 1936 hba->mmio_base = (void *)dev_read_addr(ufs_dev); 1937 1938 /* Set descriptor lengths to specification defaults */ 1939 ufshcd_def_desc_sizes(hba); 1940 1941 ufshcd_ops_init(hba); 1942 1943 /* Read capabilties registers */ 1944 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES); 1945 1946 /* Get UFS version supported by the controller */ 1947 hba->version = ufshcd_get_ufs_version(hba); 1948 if (hba->version != UFSHCI_VERSION_10 && 1949 hba->version != UFSHCI_VERSION_11 && 1950 hba->version != UFSHCI_VERSION_20 && 1951 hba->version != UFSHCI_VERSION_21) 1952 dev_err(hba->dev, "invalid UFS version 0x%x\n", 1953 hba->version); 1954 1955 /* Get Interrupt bit mask per version */ 1956 hba->intr_mask = ufshcd_get_intr_mask(hba); 1957 1958 /* Allocate memory for host memory space */ 1959 err = ufshcd_memory_alloc(hba); 1960 if (err) { 1961 dev_err(hba->dev, "Memory allocation failed\n"); 1962 return err; 1963 } 1964 1965 /* Configure Local data structures */ 1966 ufshcd_host_memory_configure(hba); 1967 1968 /* 1969 * In order to avoid any spurious interrupt immediately after 1970 * registering UFS controller interrupt handler, clear any pending UFS 1971 * interrupt status and disable all the UFS interrupts. 1972 */ 1973 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS), 1974 REG_INTERRUPT_STATUS); 1975 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE); 1976 1977 err = ufshcd_hba_enable(hba); 1978 if (err) { 1979 dev_err(hba->dev, "Host controller enable failed\n"); 1980 return err; 1981 } 1982 1983 err = ufs_start(hba); 1984 if (err) 1985 return err; 1986 1987 return 0; 1988 } 1989 1990 int ufs_scsi_bind(struct udevice *ufs_dev, struct udevice **scsi_devp) 1991 { 1992 int ret = device_bind_driver(ufs_dev, "ufs_scsi", "ufs_scsi", 1993 scsi_devp); 1994 1995 return ret; 1996 } 1997 1998 static struct scsi_ops ufs_ops = { 1999 .exec = ufs_scsi_exec, 2000 }; 2001 2002 int ufs_probe_dev(int index) 2003 { 2004 struct udevice *dev; 2005 2006 return uclass_get_device(UCLASS_UFS, index, &dev); 2007 } 2008 2009 int ufs_probe(void) 2010 { 2011 struct udevice *dev; 2012 int ret, i; 2013 2014 for (i = 0;; i++) { 2015 ret = uclass_get_device(UCLASS_UFS, i, &dev); 2016 if (ret == -ENODEV) 2017 break; 2018 } 2019 2020 return 0; 2021 } 2022 2023 U_BOOT_DRIVER(ufs_scsi) = { 2024 .id = UCLASS_SCSI, 2025 .name = "ufs_scsi", 2026 .ops = &ufs_ops, 2027 }; 2028