1 // SPDX-License-Identifier: GPL-2.0+ 2 /** 3 * ufs.c - Universal Flash Subsystem (UFS) driver 4 * 5 * Taken from Linux Kernel v5.2 (drivers/scsi/ufs/ufshcd.c) and ported 6 * to u-boot. 7 * 8 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com 9 */ 10 #include <charset.h> 11 #include <common.h> 12 #include <dm.h> 13 #include <log.h> 14 #include <dm/lists.h> 15 #include <dm/device-internal.h> 16 #include <malloc.h> 17 #include <hexdump.h> 18 #include <scsi.h> 19 #include <asm/io.h> 20 #include <asm/dma-mapping.h> 21 #include <linux/bitops.h> 22 #include <linux/delay.h> 23 24 #include "ufs.h" 25 26 #define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\ 27 UTP_TASK_REQ_COMPL |\ 28 UFSHCD_ERROR_MASK) 29 /* maximum number of link-startup retries */ 30 #define DME_LINKSTARTUP_RETRIES 3 31 32 /* maximum number of retries for a general UIC command */ 33 #define UFS_UIC_COMMAND_RETRIES 3 34 35 /* Query request retries */ 36 #define QUERY_REQ_RETRIES 3 37 /* Query request timeout */ 38 #define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */ 39 40 /* maximum timeout in ms for a general UIC command */ 41 #define UFS_UIC_CMD_TIMEOUT 1000 42 /* NOP OUT retries waiting for NOP IN response */ 43 #define NOP_OUT_RETRIES 10 44 /* Timeout after 30 msecs if NOP OUT hangs without response */ 45 #define NOP_OUT_TIMEOUT 30 /* msecs */ 46 47 /* Only use one Task Tag for all requests */ 48 #define TASK_TAG 0 49 50 /* Expose the flag value from utp_upiu_query.value */ 51 #define MASK_QUERY_UPIU_FLAG_LOC 0xFF 52 53 #define MAX_PRDT_ENTRY 262144 54 55 /* maximum bytes per request */ 56 #define UFS_MAX_BYTES (128 * 256 * 1024) 57 58 static inline bool ufshcd_is_hba_active(struct ufs_hba *hba); 59 static inline void ufshcd_hba_stop(struct ufs_hba *hba); 60 static int ufshcd_hba_enable(struct ufs_hba *hba); 61 62 /* 63 * ufshcd_wait_for_register - wait for register value to change 64 */ 65 static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask, 66 u32 val, unsigned long timeout_ms) 67 { 68 int err = 0; 69 unsigned long start = get_timer(0); 70 71 /* ignore bits that we don't intend to wait on */ 72 val = val & mask; 73 74 while ((ufshcd_readl(hba, reg) & mask) != val) { 75 if (get_timer(start) > timeout_ms) { 76 if ((ufshcd_readl(hba, reg) & mask) != val) 77 err = -ETIMEDOUT; 78 break; 79 } 80 } 81 82 return err; 83 } 84 85 /** 86 * ufshcd_init_pwr_info - setting the POR (power on reset) 87 * values in hba power info 88 */ 89 static void ufshcd_init_pwr_info(struct ufs_hba *hba) 90 { 91 hba->pwr_info.gear_rx = UFS_PWM_G1; 92 hba->pwr_info.gear_tx = UFS_PWM_G1; 93 hba->pwr_info.lane_rx = 1; 94 hba->pwr_info.lane_tx = 1; 95 hba->pwr_info.pwr_rx = SLOWAUTO_MODE; 96 hba->pwr_info.pwr_tx = SLOWAUTO_MODE; 97 hba->pwr_info.hs_rate = 0; 98 } 99 100 /** 101 * ufshcd_print_pwr_info - print power params as saved in hba 102 * power info 103 */ 104 static void ufshcd_print_pwr_info(struct ufs_hba *hba) 105 { 106 static const char * const names[] = { 107 "INVALID MODE", 108 "FAST MODE", 109 "SLOW_MODE", 110 "INVALID MODE", 111 "FASTAUTO_MODE", 112 "SLOWAUTO_MODE", 113 "INVALID MODE", 114 }; 115 116 dev_err(hba->dev, "[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n", 117 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx, 118 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx, 119 names[hba->pwr_info.pwr_rx], 120 names[hba->pwr_info.pwr_tx], 121 hba->pwr_info.hs_rate); 122 } 123 124 /** 125 * ufshcd_ready_for_uic_cmd - Check if controller is ready 126 * to accept UIC commands 127 */ 128 static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba) 129 { 130 if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY) 131 return true; 132 else 133 return false; 134 } 135 136 /** 137 * ufshcd_get_uic_cmd_result - Get the UIC command result 138 */ 139 static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba) 140 { 141 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) & 142 MASK_UIC_COMMAND_RESULT; 143 } 144 145 /** 146 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command 147 */ 148 static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba) 149 { 150 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3); 151 } 152 153 /** 154 * ufshcd_is_device_present - Check if any device connected to 155 * the host controller 156 */ 157 static inline bool ufshcd_is_device_present(struct ufs_hba *hba) 158 { 159 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & 160 DEVICE_PRESENT) ? true : false; 161 } 162 163 /** 164 * ufshcd_send_uic_cmd - UFS Interconnect layer command API 165 * 166 */ 167 static int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 168 { 169 unsigned long start = 0; 170 u32 intr_status; 171 u32 enabled_intr_status; 172 173 if (!ufshcd_ready_for_uic_cmd(hba)) { 174 dev_err(hba->dev, 175 "Controller not ready to accept UIC commands\n"); 176 return -EIO; 177 } 178 179 debug("sending uic command:%d\n", uic_cmd->command); 180 181 /* Write Args */ 182 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1); 183 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2); 184 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3); 185 186 /* Write UIC Cmd */ 187 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK, 188 REG_UIC_COMMAND); 189 190 start = get_timer(0); 191 do { 192 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 193 enabled_intr_status = intr_status & hba->intr_mask; 194 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS); 195 196 if (get_timer(start) > UFS_UIC_CMD_TIMEOUT) { 197 dev_err(hba->dev, 198 "Timedout waiting for UIC response\n"); 199 200 return -ETIMEDOUT; 201 } 202 203 if (enabled_intr_status & UFSHCD_ERROR_MASK) { 204 dev_err(hba->dev, "Error in status:%08x\n", 205 enabled_intr_status); 206 207 return -1; 208 } 209 } while (!(enabled_intr_status & UFSHCD_UIC_MASK)); 210 211 uic_cmd->argument2 = ufshcd_get_uic_cmd_result(hba); 212 uic_cmd->argument3 = ufshcd_get_dme_attr_val(hba); 213 214 debug("Sent successfully\n"); 215 216 return 0; 217 } 218 219 /** 220 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET 221 * 222 */ 223 int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, u8 attr_set, 224 u32 mib_val, u8 peer) 225 { 226 struct uic_command uic_cmd = {0}; 227 static const char *const action[] = { 228 "dme-set", 229 "dme-peer-set" 230 }; 231 const char *set = action[!!peer]; 232 int ret; 233 int retries = UFS_UIC_COMMAND_RETRIES; 234 235 uic_cmd.command = peer ? 236 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET; 237 uic_cmd.argument1 = attr_sel; 238 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set); 239 uic_cmd.argument3 = mib_val; 240 241 do { 242 /* for peer attributes we retry upon failure */ 243 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 244 if (ret) 245 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n", 246 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret); 247 } while (ret && peer && --retries); 248 249 if (ret) 250 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n", 251 set, UIC_GET_ATTR_ID(attr_sel), mib_val, 252 UFS_UIC_COMMAND_RETRIES - retries); 253 254 return ret; 255 } 256 257 /** 258 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET 259 * 260 */ 261 int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, 262 u32 *mib_val, u8 peer) 263 { 264 struct uic_command uic_cmd = {0}; 265 static const char *const action[] = { 266 "dme-get", 267 "dme-peer-get" 268 }; 269 const char *get = action[!!peer]; 270 int ret; 271 int retries = UFS_UIC_COMMAND_RETRIES; 272 273 uic_cmd.command = peer ? 274 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET; 275 uic_cmd.argument1 = attr_sel; 276 277 do { 278 /* for peer attributes we retry upon failure */ 279 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 280 if (ret) 281 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n", 282 get, UIC_GET_ATTR_ID(attr_sel), ret); 283 } while (ret && peer && --retries); 284 285 if (ret) 286 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n", 287 get, UIC_GET_ATTR_ID(attr_sel), 288 UFS_UIC_COMMAND_RETRIES - retries); 289 290 if (mib_val && !ret) 291 *mib_val = uic_cmd.argument3; 292 293 return ret; 294 } 295 296 static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer) 297 { 298 u32 tx_lanes, i, err = 0; 299 300 if (!peer) 301 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 302 &tx_lanes); 303 else 304 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 305 &tx_lanes); 306 for (i = 0; i < tx_lanes; i++) { 307 if (!peer) 308 err = ufshcd_dme_set(hba, 309 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, 310 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), 311 0); 312 else 313 err = ufshcd_dme_peer_set(hba, 314 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, 315 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), 316 0); 317 if (err) { 318 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d", 319 __func__, peer, i, err); 320 break; 321 } 322 } 323 324 return err; 325 } 326 327 static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba) 328 { 329 return ufshcd_disable_tx_lcc(hba, true); 330 } 331 332 /** 333 * ufshcd_dme_link_startup - Notify Unipro to perform link startup 334 * 335 */ 336 static int ufshcd_dme_link_startup(struct ufs_hba *hba) 337 { 338 struct uic_command uic_cmd = {0}; 339 int ret; 340 341 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP; 342 343 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 344 if (ret) 345 dev_dbg(hba->dev, 346 "dme-link-startup: error code %d\n", ret); 347 return ret; 348 } 349 350 /** 351 * ufshcd_disable_intr_aggr - Disables interrupt aggregation. 352 * 353 */ 354 static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba) 355 { 356 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 357 } 358 359 /** 360 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY 361 */ 362 static inline int ufshcd_get_lists_status(u32 reg) 363 { 364 return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY); 365 } 366 367 /** 368 * ufshcd_enable_run_stop_reg - Enable run-stop registers, 369 * When run-stop registers are set to 1, it indicates the 370 * host controller that it can process the requests 371 */ 372 static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba) 373 { 374 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT, 375 REG_UTP_TASK_REQ_LIST_RUN_STOP); 376 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT, 377 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP); 378 } 379 380 /** 381 * ufshcd_enable_intr - enable interrupts 382 */ 383 static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs) 384 { 385 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 386 u32 rw; 387 388 if (hba->version == UFSHCI_VERSION_10) { 389 rw = set & INTERRUPT_MASK_RW_VER_10; 390 set = rw | ((set ^ intrs) & intrs); 391 } else { 392 set |= intrs; 393 } 394 395 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); 396 397 hba->intr_mask = set; 398 } 399 400 /** 401 * ufshcd_make_hba_operational - Make UFS controller operational 402 * 403 * To bring UFS host controller to operational state, 404 * 1. Enable required interrupts 405 * 2. Configure interrupt aggregation 406 * 3. Program UTRL and UTMRL base address 407 * 4. Configure run-stop-registers 408 * 409 */ 410 static int ufshcd_make_hba_operational(struct ufs_hba *hba) 411 { 412 int err = 0; 413 u32 reg; 414 415 /* Enable required interrupts */ 416 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS); 417 418 /* Disable interrupt aggregation */ 419 ufshcd_disable_intr_aggr(hba); 420 421 /* Configure UTRL and UTMRL base address registers */ 422 ufshcd_writel(hba, lower_32_bits((dma_addr_t)hba->utrdl), 423 REG_UTP_TRANSFER_REQ_LIST_BASE_L); 424 ufshcd_writel(hba, upper_32_bits((dma_addr_t)hba->utrdl), 425 REG_UTP_TRANSFER_REQ_LIST_BASE_H); 426 ufshcd_writel(hba, lower_32_bits((dma_addr_t)hba->utmrdl), 427 REG_UTP_TASK_REQ_LIST_BASE_L); 428 ufshcd_writel(hba, upper_32_bits((dma_addr_t)hba->utmrdl), 429 REG_UTP_TASK_REQ_LIST_BASE_H); 430 431 /* 432 * UCRDY, UTMRLDY and UTRLRDY bits must be 1 433 */ 434 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS); 435 if (!(ufshcd_get_lists_status(reg))) { 436 ufshcd_enable_run_stop_reg(hba); 437 } else { 438 dev_err(hba->dev, 439 "Host controller not ready to process requests"); 440 err = -EIO; 441 goto out; 442 } 443 444 out: 445 return err; 446 } 447 448 /** 449 * ufshcd_link_startup - Initialize unipro link startup 450 */ 451 static int ufshcd_link_startup(struct ufs_hba *hba) 452 { 453 int ret; 454 int retries = DME_LINKSTARTUP_RETRIES; 455 bool link_startup_again = true; 456 457 link_startup: 458 do { 459 ufshcd_ops_link_startup_notify(hba, PRE_CHANGE); 460 461 ret = ufshcd_dme_link_startup(hba); 462 463 /* check if device is detected by inter-connect layer */ 464 if (!ret && !ufshcd_is_device_present(hba)) { 465 dev_err(hba->dev, "%s: Device not present\n", __func__); 466 ret = -ENXIO; 467 goto out; 468 } 469 470 /* 471 * DME link lost indication is only received when link is up, 472 * but we can't be sure if the link is up until link startup 473 * succeeds. So reset the local Uni-Pro and try again. 474 */ 475 if (ret && ufshcd_hba_enable(hba)) 476 goto out; 477 } while (ret && retries--); 478 479 if (ret) 480 /* failed to get the link up... retire */ 481 goto out; 482 483 if (link_startup_again) { 484 link_startup_again = false; 485 retries = DME_LINKSTARTUP_RETRIES; 486 goto link_startup; 487 } 488 489 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */ 490 ufshcd_init_pwr_info(hba); 491 492 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) { 493 ret = ufshcd_disable_device_tx_lcc(hba); 494 if (ret) 495 goto out; 496 } 497 498 /* Include any host controller configuration via UIC commands */ 499 ret = ufshcd_ops_link_startup_notify(hba, POST_CHANGE); 500 if (ret) 501 goto out; 502 503 ret = ufshcd_make_hba_operational(hba); 504 out: 505 if (ret) 506 dev_err(hba->dev, "link startup failed %d\n", ret); 507 508 return ret; 509 } 510 511 /** 512 * ufshcd_hba_stop - Send controller to reset state 513 */ 514 static inline void ufshcd_hba_stop(struct ufs_hba *hba) 515 { 516 int err; 517 518 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE); 519 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE, 520 CONTROLLER_ENABLE, CONTROLLER_DISABLE, 521 10); 522 if (err) 523 dev_err(hba->dev, "%s: Controller disable failed\n", __func__); 524 } 525 526 /** 527 * ufshcd_is_hba_active - Get controller state 528 */ 529 static inline bool ufshcd_is_hba_active(struct ufs_hba *hba) 530 { 531 return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE) 532 ? false : true; 533 } 534 535 /** 536 * ufshcd_hba_start - Start controller initialization sequence 537 */ 538 static inline void ufshcd_hba_start(struct ufs_hba *hba) 539 { 540 ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE); 541 } 542 543 /** 544 * ufshcd_hba_enable - initialize the controller 545 */ 546 static int ufshcd_hba_enable(struct ufs_hba *hba) 547 { 548 int retry; 549 550 if (!ufshcd_is_hba_active(hba)) 551 /* change controller state to "reset state" */ 552 ufshcd_hba_stop(hba); 553 554 ufshcd_ops_hce_enable_notify(hba, PRE_CHANGE); 555 556 /* start controller initialization sequence */ 557 ufshcd_hba_start(hba); 558 559 /* 560 * To initialize a UFS host controller HCE bit must be set to 1. 561 * During initialization the HCE bit value changes from 1->0->1. 562 * When the host controller completes initialization sequence 563 * it sets the value of HCE bit to 1. The same HCE bit is read back 564 * to check if the controller has completed initialization sequence. 565 * So without this delay the value HCE = 1, set in the previous 566 * instruction might be read back. 567 * This delay can be changed based on the controller. 568 */ 569 mdelay(1); 570 571 /* wait for the host controller to complete initialization */ 572 retry = 10; 573 while (ufshcd_is_hba_active(hba)) { 574 if (retry) { 575 retry--; 576 } else { 577 dev_err(hba->dev, "Controller enable failed\n"); 578 return -EIO; 579 } 580 mdelay(5); 581 } 582 583 /* enable UIC related interrupts */ 584 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK); 585 586 ufshcd_ops_hce_enable_notify(hba, POST_CHANGE); 587 588 return 0; 589 } 590 591 /** 592 * ufshcd_host_memory_configure - configure local reference block with 593 * memory offsets 594 */ 595 static void ufshcd_host_memory_configure(struct ufs_hba *hba) 596 { 597 struct utp_transfer_req_desc *utrdlp; 598 dma_addr_t cmd_desc_dma_addr; 599 u16 response_offset; 600 u16 prdt_offset; 601 602 utrdlp = hba->utrdl; 603 cmd_desc_dma_addr = (dma_addr_t)hba->ucdl; 604 605 utrdlp->command_desc_base_addr_lo = 606 cpu_to_le32(lower_32_bits(cmd_desc_dma_addr)); 607 utrdlp->command_desc_base_addr_hi = 608 cpu_to_le32(upper_32_bits(cmd_desc_dma_addr)); 609 610 response_offset = offsetof(struct utp_transfer_cmd_desc, response_upiu); 611 prdt_offset = offsetof(struct utp_transfer_cmd_desc, prd_table); 612 613 utrdlp->response_upiu_offset = cpu_to_le16(response_offset >> 2); 614 utrdlp->prd_table_offset = cpu_to_le16(prdt_offset >> 2); 615 utrdlp->response_upiu_length = cpu_to_le16(ALIGNED_UPIU_SIZE >> 2); 616 617 hba->ucd_req_ptr = (struct utp_upiu_req *)hba->ucdl; 618 hba->ucd_rsp_ptr = 619 (struct utp_upiu_rsp *)&hba->ucdl->response_upiu; 620 hba->ucd_prdt_ptr = 621 (struct ufshcd_sg_entry *)&hba->ucdl->prd_table; 622 } 623 624 /** 625 * ufshcd_memory_alloc - allocate memory for host memory space data structures 626 */ 627 static int ufshcd_memory_alloc(struct ufs_hba *hba) 628 { 629 /* Allocate one Transfer Request Descriptor 630 * Should be aligned to 1k boundary. 631 */ 632 hba->utrdl = memalign(1024, sizeof(struct utp_transfer_req_desc)); 633 if (!hba->utrdl) { 634 dev_err(hba->dev, "Transfer Descriptor memory allocation failed\n"); 635 return -ENOMEM; 636 } 637 638 /* Allocate one Command Descriptor 639 * Should be aligned to 1k boundary. 640 */ 641 hba->ucdl = memalign(1024, sizeof(struct utp_transfer_cmd_desc)); 642 if (!hba->ucdl) { 643 dev_err(hba->dev, "Command descriptor memory allocation failed\n"); 644 return -ENOMEM; 645 } 646 647 return 0; 648 } 649 650 /** 651 * ufshcd_get_intr_mask - Get the interrupt bit mask 652 */ 653 static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba) 654 { 655 u32 intr_mask = 0; 656 657 switch (hba->version) { 658 case UFSHCI_VERSION_10: 659 intr_mask = INTERRUPT_MASK_ALL_VER_10; 660 break; 661 case UFSHCI_VERSION_11: 662 case UFSHCI_VERSION_20: 663 intr_mask = INTERRUPT_MASK_ALL_VER_11; 664 break; 665 case UFSHCI_VERSION_21: 666 default: 667 intr_mask = INTERRUPT_MASK_ALL_VER_21; 668 break; 669 } 670 671 return intr_mask; 672 } 673 674 /** 675 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA 676 */ 677 static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba) 678 { 679 return ufshcd_readl(hba, REG_UFS_VERSION); 680 } 681 682 /** 683 * ufshcd_get_upmcrs - Get the power mode change request status 684 */ 685 static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba) 686 { 687 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7; 688 } 689 690 /** 691 * ufshcd_cache_flush_and_invalidate - Flush and invalidate cache 692 * 693 * Flush and invalidate cache in aligned address..address+size range. 694 * The invalidation is in place to avoid stale data in cache. 695 */ 696 static void ufshcd_cache_flush_and_invalidate(void *addr, unsigned long size) 697 { 698 uintptr_t aaddr = (uintptr_t)addr & ~(ARCH_DMA_MINALIGN - 1); 699 unsigned long asize = ALIGN(size, ARCH_DMA_MINALIGN); 700 701 flush_dcache_range(aaddr, aaddr + asize); 702 invalidate_dcache_range(aaddr, aaddr + asize); 703 } 704 705 /** 706 * ufshcd_prepare_req_desc_hdr() - Fills the requests header 707 * descriptor according to request 708 */ 709 static void ufshcd_prepare_req_desc_hdr(struct utp_transfer_req_desc *req_desc, 710 u32 *upiu_flags, 711 enum dma_data_direction cmd_dir) 712 { 713 u32 data_direction; 714 u32 dword_0; 715 716 if (cmd_dir == DMA_FROM_DEVICE) { 717 data_direction = UTP_DEVICE_TO_HOST; 718 *upiu_flags = UPIU_CMD_FLAGS_READ; 719 } else if (cmd_dir == DMA_TO_DEVICE) { 720 data_direction = UTP_HOST_TO_DEVICE; 721 *upiu_flags = UPIU_CMD_FLAGS_WRITE; 722 } else { 723 data_direction = UTP_NO_DATA_TRANSFER; 724 *upiu_flags = UPIU_CMD_FLAGS_NONE; 725 } 726 727 dword_0 = data_direction | (0x1 << UPIU_COMMAND_TYPE_OFFSET); 728 729 /* Enable Interrupt for command */ 730 dword_0 |= UTP_REQ_DESC_INT_CMD; 731 732 /* Transfer request descriptor header fields */ 733 req_desc->header.dword_0 = cpu_to_le32(dword_0); 734 /* dword_1 is reserved, hence it is set to 0 */ 735 req_desc->header.dword_1 = 0; 736 /* 737 * assigning invalid value for command status. Controller 738 * updates OCS on command completion, with the command 739 * status 740 */ 741 req_desc->header.dword_2 = 742 cpu_to_le32(OCS_INVALID_COMMAND_STATUS); 743 /* dword_3 is reserved, hence it is set to 0 */ 744 req_desc->header.dword_3 = 0; 745 746 req_desc->prd_table_length = 0; 747 748 ufshcd_cache_flush_and_invalidate(req_desc, sizeof(*req_desc)); 749 } 750 751 static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba, 752 u32 upiu_flags) 753 { 754 struct utp_upiu_req *ucd_req_ptr = hba->ucd_req_ptr; 755 struct ufs_query *query = &hba->dev_cmd.query; 756 u16 len = be16_to_cpu(query->request.upiu_req.length); 757 758 /* Query request header */ 759 ucd_req_ptr->header.dword_0 = 760 UPIU_HEADER_DWORD(UPIU_TRANSACTION_QUERY_REQ, 761 upiu_flags, 0, TASK_TAG); 762 ucd_req_ptr->header.dword_1 = 763 UPIU_HEADER_DWORD(0, query->request.query_func, 764 0, 0); 765 766 /* Data segment length only need for WRITE_DESC */ 767 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC) 768 ucd_req_ptr->header.dword_2 = 769 UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len); 770 else 771 ucd_req_ptr->header.dword_2 = 0; 772 773 /* Copy the Query Request buffer as is */ 774 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req, QUERY_OSF_SIZE); 775 776 /* Copy the Descriptor */ 777 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC) { 778 memcpy(ucd_req_ptr + 1, query->descriptor, len); 779 ufshcd_cache_flush_and_invalidate(ucd_req_ptr, 2 * sizeof(*ucd_req_ptr)); 780 } else { 781 ufshcd_cache_flush_and_invalidate(ucd_req_ptr, sizeof(*ucd_req_ptr)); 782 } 783 784 memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 785 ufshcd_cache_flush_and_invalidate(hba->ucd_rsp_ptr, sizeof(*hba->ucd_rsp_ptr)); 786 } 787 788 static inline void ufshcd_prepare_utp_nop_upiu(struct ufs_hba *hba) 789 { 790 struct utp_upiu_req *ucd_req_ptr = hba->ucd_req_ptr; 791 792 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req)); 793 794 /* command descriptor fields */ 795 ucd_req_ptr->header.dword_0 = 796 UPIU_HEADER_DWORD(UPIU_TRANSACTION_NOP_OUT, 0, 0, TASK_TAG); 797 /* clear rest of the fields of basic header */ 798 ucd_req_ptr->header.dword_1 = 0; 799 ucd_req_ptr->header.dword_2 = 0; 800 801 memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 802 803 ufshcd_cache_flush_and_invalidate(ucd_req_ptr, sizeof(*ucd_req_ptr)); 804 ufshcd_cache_flush_and_invalidate(hba->ucd_rsp_ptr, sizeof(*hba->ucd_rsp_ptr)); 805 } 806 807 /** 808 * ufshcd_comp_devman_upiu - UFS Protocol Information Unit(UPIU) 809 * for Device Management Purposes 810 */ 811 static int ufshcd_comp_devman_upiu(struct ufs_hba *hba, 812 enum dev_cmd_type cmd_type) 813 { 814 u32 upiu_flags; 815 int ret = 0; 816 struct utp_transfer_req_desc *req_desc = hba->utrdl; 817 818 hba->dev_cmd.type = cmd_type; 819 820 ufshcd_prepare_req_desc_hdr(req_desc, &upiu_flags, DMA_NONE); 821 switch (cmd_type) { 822 case DEV_CMD_TYPE_QUERY: 823 ufshcd_prepare_utp_query_req_upiu(hba, upiu_flags); 824 break; 825 case DEV_CMD_TYPE_NOP: 826 ufshcd_prepare_utp_nop_upiu(hba); 827 break; 828 default: 829 ret = -EINVAL; 830 } 831 832 return ret; 833 } 834 835 static int ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag) 836 { 837 unsigned long start; 838 u32 intr_status; 839 u32 enabled_intr_status; 840 841 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL); 842 843 start = get_timer(0); 844 do { 845 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 846 enabled_intr_status = intr_status & hba->intr_mask; 847 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS); 848 849 if (get_timer(start) > QUERY_REQ_TIMEOUT) { 850 dev_err(hba->dev, 851 "Timedout waiting for UTP response\n"); 852 853 return -ETIMEDOUT; 854 } 855 856 if (enabled_intr_status & UFSHCD_ERROR_MASK) { 857 dev_err(hba->dev, "Error in status:%08x\n", 858 enabled_intr_status); 859 860 return -1; 861 } 862 } while (!(enabled_intr_status & UTP_TRANSFER_REQ_COMPL)); 863 864 return 0; 865 } 866 867 /** 868 * ufshcd_get_req_rsp - returns the TR response transaction type 869 */ 870 static inline int ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr) 871 { 872 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24; 873 } 874 875 /** 876 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status 877 * 878 */ 879 static inline int ufshcd_get_tr_ocs(struct ufs_hba *hba) 880 { 881 return le32_to_cpu(hba->utrdl->header.dword_2) & MASK_OCS; 882 } 883 884 static inline int ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr) 885 { 886 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT; 887 } 888 889 static int ufshcd_check_query_response(struct ufs_hba *hba) 890 { 891 struct ufs_query_res *query_res = &hba->dev_cmd.query.response; 892 893 /* Get the UPIU response */ 894 query_res->response = ufshcd_get_rsp_upiu_result(hba->ucd_rsp_ptr) >> 895 UPIU_RSP_CODE_OFFSET; 896 return query_res->response; 897 } 898 899 /** 900 * ufshcd_copy_query_response() - Copy the Query Response and the data 901 * descriptor 902 */ 903 static int ufshcd_copy_query_response(struct ufs_hba *hba) 904 { 905 struct ufs_query_res *query_res = &hba->dev_cmd.query.response; 906 907 memcpy(&query_res->upiu_res, &hba->ucd_rsp_ptr->qr, QUERY_OSF_SIZE); 908 909 /* Get the descriptor */ 910 if (hba->dev_cmd.query.descriptor && 911 hba->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) { 912 u8 *descp = (u8 *)hba->ucd_rsp_ptr + 913 GENERAL_UPIU_REQUEST_SIZE; 914 u16 resp_len; 915 u16 buf_len; 916 917 /* data segment length */ 918 resp_len = be32_to_cpu(hba->ucd_rsp_ptr->header.dword_2) & 919 MASK_QUERY_DATA_SEG_LEN; 920 buf_len = 921 be16_to_cpu(hba->dev_cmd.query.request.upiu_req.length); 922 if (likely(buf_len >= resp_len)) { 923 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len); 924 } else { 925 dev_warn(hba->dev, 926 "%s: Response size is bigger than buffer", 927 __func__); 928 return -EINVAL; 929 } 930 } 931 932 return 0; 933 } 934 935 /** 936 * ufshcd_exec_dev_cmd - API for sending device management requests 937 */ 938 static int ufshcd_exec_dev_cmd(struct ufs_hba *hba, enum dev_cmd_type cmd_type, 939 int timeout) 940 { 941 int err; 942 int resp; 943 944 err = ufshcd_comp_devman_upiu(hba, cmd_type); 945 if (err) 946 return err; 947 948 err = ufshcd_send_command(hba, TASK_TAG); 949 if (err) 950 return err; 951 952 err = ufshcd_get_tr_ocs(hba); 953 if (err) { 954 dev_err(hba->dev, "Error in OCS:%d\n", err); 955 return -EINVAL; 956 } 957 958 resp = ufshcd_get_req_rsp(hba->ucd_rsp_ptr); 959 switch (resp) { 960 case UPIU_TRANSACTION_NOP_IN: 961 break; 962 case UPIU_TRANSACTION_QUERY_RSP: 963 err = ufshcd_check_query_response(hba); 964 if (!err) 965 err = ufshcd_copy_query_response(hba); 966 break; 967 case UPIU_TRANSACTION_REJECT_UPIU: 968 /* TODO: handle Reject UPIU Response */ 969 err = -EPERM; 970 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n", 971 __func__); 972 break; 973 default: 974 err = -EINVAL; 975 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n", 976 __func__, resp); 977 } 978 979 return err; 980 } 981 982 /** 983 * ufshcd_init_query() - init the query response and request parameters 984 */ 985 static inline void ufshcd_init_query(struct ufs_hba *hba, 986 struct ufs_query_req **request, 987 struct ufs_query_res **response, 988 enum query_opcode opcode, 989 u8 idn, u8 index, u8 selector) 990 { 991 *request = &hba->dev_cmd.query.request; 992 *response = &hba->dev_cmd.query.response; 993 memset(*request, 0, sizeof(struct ufs_query_req)); 994 memset(*response, 0, sizeof(struct ufs_query_res)); 995 (*request)->upiu_req.opcode = opcode; 996 (*request)->upiu_req.idn = idn; 997 (*request)->upiu_req.index = index; 998 (*request)->upiu_req.selector = selector; 999 } 1000 1001 /** 1002 * ufshcd_query_flag() - API function for sending flag query requests 1003 */ 1004 int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode, 1005 enum flag_idn idn, bool *flag_res) 1006 { 1007 struct ufs_query_req *request = NULL; 1008 struct ufs_query_res *response = NULL; 1009 int err, index = 0, selector = 0; 1010 int timeout = QUERY_REQ_TIMEOUT; 1011 1012 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 1013 selector); 1014 1015 switch (opcode) { 1016 case UPIU_QUERY_OPCODE_SET_FLAG: 1017 case UPIU_QUERY_OPCODE_CLEAR_FLAG: 1018 case UPIU_QUERY_OPCODE_TOGGLE_FLAG: 1019 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 1020 break; 1021 case UPIU_QUERY_OPCODE_READ_FLAG: 1022 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 1023 if (!flag_res) { 1024 /* No dummy reads */ 1025 dev_err(hba->dev, "%s: Invalid argument for read request\n", 1026 __func__); 1027 err = -EINVAL; 1028 goto out; 1029 } 1030 break; 1031 default: 1032 dev_err(hba->dev, 1033 "%s: Expected query flag opcode but got = %d\n", 1034 __func__, opcode); 1035 err = -EINVAL; 1036 goto out; 1037 } 1038 1039 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout); 1040 1041 if (err) { 1042 dev_err(hba->dev, 1043 "%s: Sending flag query for idn %d failed, err = %d\n", 1044 __func__, idn, err); 1045 goto out; 1046 } 1047 1048 if (flag_res) 1049 *flag_res = (be32_to_cpu(response->upiu_res.value) & 1050 MASK_QUERY_UPIU_FLAG_LOC) & 0x1; 1051 1052 out: 1053 return err; 1054 } 1055 1056 static int ufshcd_query_flag_retry(struct ufs_hba *hba, 1057 enum query_opcode opcode, 1058 enum flag_idn idn, bool *flag_res) 1059 { 1060 int ret; 1061 int retries; 1062 1063 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) { 1064 ret = ufshcd_query_flag(hba, opcode, idn, flag_res); 1065 if (ret) 1066 dev_dbg(hba->dev, 1067 "%s: failed with error %d, retries %d\n", 1068 __func__, ret, retries); 1069 else 1070 break; 1071 } 1072 1073 if (ret) 1074 dev_err(hba->dev, 1075 "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n", 1076 __func__, opcode, idn, ret, retries); 1077 return ret; 1078 } 1079 1080 static int __ufshcd_query_descriptor(struct ufs_hba *hba, 1081 enum query_opcode opcode, 1082 enum desc_idn idn, u8 index, u8 selector, 1083 u8 *desc_buf, int *buf_len) 1084 { 1085 struct ufs_query_req *request = NULL; 1086 struct ufs_query_res *response = NULL; 1087 int err; 1088 1089 if (!desc_buf) { 1090 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n", 1091 __func__, opcode); 1092 err = -EINVAL; 1093 goto out; 1094 } 1095 1096 if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) { 1097 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n", 1098 __func__, *buf_len); 1099 err = -EINVAL; 1100 goto out; 1101 } 1102 1103 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 1104 selector); 1105 hba->dev_cmd.query.descriptor = desc_buf; 1106 request->upiu_req.length = cpu_to_be16(*buf_len); 1107 1108 switch (opcode) { 1109 case UPIU_QUERY_OPCODE_WRITE_DESC: 1110 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 1111 break; 1112 case UPIU_QUERY_OPCODE_READ_DESC: 1113 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 1114 break; 1115 default: 1116 dev_err(hba->dev, "%s: Expected query descriptor opcode but got = 0x%.2x\n", 1117 __func__, opcode); 1118 err = -EINVAL; 1119 goto out; 1120 } 1121 1122 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 1123 1124 if (err) { 1125 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n", 1126 __func__, opcode, idn, index, err); 1127 goto out; 1128 } 1129 1130 hba->dev_cmd.query.descriptor = NULL; 1131 *buf_len = be16_to_cpu(response->upiu_res.length); 1132 1133 out: 1134 return err; 1135 } 1136 1137 /** 1138 * ufshcd_query_descriptor_retry - API function for sending descriptor requests 1139 */ 1140 int ufshcd_query_descriptor_retry(struct ufs_hba *hba, enum query_opcode opcode, 1141 enum desc_idn idn, u8 index, u8 selector, 1142 u8 *desc_buf, int *buf_len) 1143 { 1144 int err; 1145 int retries; 1146 1147 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) { 1148 err = __ufshcd_query_descriptor(hba, opcode, idn, index, 1149 selector, desc_buf, buf_len); 1150 if (!err || err == -EINVAL) 1151 break; 1152 } 1153 1154 return err; 1155 } 1156 1157 /** 1158 * ufshcd_read_desc_length - read the specified descriptor length from header 1159 */ 1160 static int ufshcd_read_desc_length(struct ufs_hba *hba, enum desc_idn desc_id, 1161 int desc_index, int *desc_length) 1162 { 1163 int ret; 1164 u8 header[QUERY_DESC_HDR_SIZE]; 1165 int header_len = QUERY_DESC_HDR_SIZE; 1166 1167 if (desc_id >= QUERY_DESC_IDN_MAX) 1168 return -EINVAL; 1169 1170 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC, 1171 desc_id, desc_index, 0, header, 1172 &header_len); 1173 1174 if (ret) { 1175 dev_err(hba->dev, "%s: Failed to get descriptor header id %d", 1176 __func__, desc_id); 1177 return ret; 1178 } else if (desc_id != header[QUERY_DESC_DESC_TYPE_OFFSET]) { 1179 dev_warn(hba->dev, "%s: descriptor header id %d and desc_id %d mismatch", 1180 __func__, header[QUERY_DESC_DESC_TYPE_OFFSET], 1181 desc_id); 1182 ret = -EINVAL; 1183 } 1184 1185 *desc_length = header[QUERY_DESC_LENGTH_OFFSET]; 1186 1187 return ret; 1188 } 1189 1190 static void ufshcd_init_desc_sizes(struct ufs_hba *hba) 1191 { 1192 int err; 1193 1194 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_DEVICE, 0, 1195 &hba->desc_size.dev_desc); 1196 if (err) 1197 hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE; 1198 1199 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_POWER, 0, 1200 &hba->desc_size.pwr_desc); 1201 if (err) 1202 hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE; 1203 1204 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_INTERCONNECT, 0, 1205 &hba->desc_size.interc_desc); 1206 if (err) 1207 hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE; 1208 1209 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_CONFIGURATION, 0, 1210 &hba->desc_size.conf_desc); 1211 if (err) 1212 hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE; 1213 1214 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_UNIT, 0, 1215 &hba->desc_size.unit_desc); 1216 if (err) 1217 hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE; 1218 1219 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_GEOMETRY, 0, 1220 &hba->desc_size.geom_desc); 1221 if (err) 1222 hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE; 1223 1224 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_HEALTH, 0, 1225 &hba->desc_size.hlth_desc); 1226 if (err) 1227 hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE; 1228 } 1229 1230 /** 1231 * ufshcd_map_desc_id_to_length - map descriptor IDN to its length 1232 * 1233 */ 1234 int ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id, 1235 int *desc_len) 1236 { 1237 switch (desc_id) { 1238 case QUERY_DESC_IDN_DEVICE: 1239 *desc_len = hba->desc_size.dev_desc; 1240 break; 1241 case QUERY_DESC_IDN_POWER: 1242 *desc_len = hba->desc_size.pwr_desc; 1243 break; 1244 case QUERY_DESC_IDN_GEOMETRY: 1245 *desc_len = hba->desc_size.geom_desc; 1246 break; 1247 case QUERY_DESC_IDN_CONFIGURATION: 1248 *desc_len = hba->desc_size.conf_desc; 1249 break; 1250 case QUERY_DESC_IDN_UNIT: 1251 *desc_len = hba->desc_size.unit_desc; 1252 break; 1253 case QUERY_DESC_IDN_INTERCONNECT: 1254 *desc_len = hba->desc_size.interc_desc; 1255 break; 1256 case QUERY_DESC_IDN_STRING: 1257 *desc_len = QUERY_DESC_MAX_SIZE; 1258 break; 1259 case QUERY_DESC_IDN_HEALTH: 1260 *desc_len = hba->desc_size.hlth_desc; 1261 break; 1262 case QUERY_DESC_IDN_RFU_0: 1263 case QUERY_DESC_IDN_RFU_1: 1264 *desc_len = 0; 1265 break; 1266 default: 1267 *desc_len = 0; 1268 return -EINVAL; 1269 } 1270 return 0; 1271 } 1272 EXPORT_SYMBOL(ufshcd_map_desc_id_to_length); 1273 1274 /** 1275 * ufshcd_read_desc_param - read the specified descriptor parameter 1276 * 1277 */ 1278 int ufshcd_read_desc_param(struct ufs_hba *hba, enum desc_idn desc_id, 1279 int desc_index, u8 param_offset, u8 *param_read_buf, 1280 u8 param_size) 1281 { 1282 int ret; 1283 u8 *desc_buf; 1284 int buff_len; 1285 bool is_kmalloc = true; 1286 1287 /* Safety check */ 1288 if (desc_id >= QUERY_DESC_IDN_MAX || !param_size) 1289 return -EINVAL; 1290 1291 /* Get the max length of descriptor from structure filled up at probe 1292 * time. 1293 */ 1294 ret = ufshcd_map_desc_id_to_length(hba, desc_id, &buff_len); 1295 1296 /* Sanity checks */ 1297 if (ret || !buff_len) { 1298 dev_err(hba->dev, "%s: Failed to get full descriptor length", 1299 __func__); 1300 return ret; 1301 } 1302 1303 /* Check whether we need temp memory */ 1304 if (param_offset != 0 || param_size < buff_len) { 1305 desc_buf = kmalloc(buff_len, GFP_KERNEL); 1306 if (!desc_buf) 1307 return -ENOMEM; 1308 } else { 1309 desc_buf = param_read_buf; 1310 is_kmalloc = false; 1311 } 1312 1313 /* Request for full descriptor */ 1314 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC, 1315 desc_id, desc_index, 0, desc_buf, 1316 &buff_len); 1317 1318 if (ret) { 1319 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d", 1320 __func__, desc_id, desc_index, param_offset, ret); 1321 goto out; 1322 } 1323 1324 /* Sanity check */ 1325 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) { 1326 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header", 1327 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]); 1328 ret = -EINVAL; 1329 goto out; 1330 } 1331 1332 /* Check wherher we will not copy more data, than available */ 1333 if (is_kmalloc && param_size > buff_len) 1334 param_size = buff_len; 1335 1336 if (is_kmalloc) 1337 memcpy(param_read_buf, &desc_buf[param_offset], param_size); 1338 out: 1339 if (is_kmalloc) 1340 kfree(desc_buf); 1341 return ret; 1342 } 1343 1344 /* replace non-printable or non-ASCII characters with spaces */ 1345 static inline void ufshcd_remove_non_printable(uint8_t *val) 1346 { 1347 if (!val) 1348 return; 1349 1350 if (*val < 0x20 || *val > 0x7e) 1351 *val = ' '; 1352 } 1353 1354 /** 1355 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power 1356 * state) and waits for it to take effect. 1357 * 1358 */ 1359 static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd) 1360 { 1361 unsigned long start = 0; 1362 u8 status; 1363 int ret; 1364 1365 ret = ufshcd_send_uic_cmd(hba, cmd); 1366 if (ret) { 1367 dev_err(hba->dev, 1368 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n", 1369 cmd->command, cmd->argument3, ret); 1370 1371 return ret; 1372 } 1373 1374 start = get_timer(0); 1375 do { 1376 status = ufshcd_get_upmcrs(hba); 1377 if (get_timer(start) > UFS_UIC_CMD_TIMEOUT) { 1378 dev_err(hba->dev, 1379 "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n", 1380 cmd->command, status); 1381 ret = (status != PWR_OK) ? status : -1; 1382 break; 1383 } 1384 } while (status != PWR_LOCAL); 1385 1386 return ret; 1387 } 1388 1389 /** 1390 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode change 1391 * using DME_SET primitives. 1392 */ 1393 static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode) 1394 { 1395 struct uic_command uic_cmd = {0}; 1396 int ret; 1397 1398 uic_cmd.command = UIC_CMD_DME_SET; 1399 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE); 1400 uic_cmd.argument3 = mode; 1401 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 1402 1403 return ret; 1404 } 1405 1406 static 1407 void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufs_hba *hba, 1408 struct scsi_cmd *pccb, u32 upiu_flags) 1409 { 1410 struct utp_upiu_req *ucd_req_ptr = hba->ucd_req_ptr; 1411 unsigned int cdb_len; 1412 1413 /* command descriptor fields */ 1414 ucd_req_ptr->header.dword_0 = 1415 UPIU_HEADER_DWORD(UPIU_TRANSACTION_COMMAND, upiu_flags, 1416 pccb->lun, TASK_TAG); 1417 ucd_req_ptr->header.dword_1 = 1418 UPIU_HEADER_DWORD(UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0); 1419 1420 /* Total EHS length and Data segment length will be zero */ 1421 ucd_req_ptr->header.dword_2 = 0; 1422 1423 ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(pccb->datalen); 1424 1425 cdb_len = min_t(unsigned short, pccb->cmdlen, UFS_CDB_SIZE); 1426 memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE); 1427 memcpy(ucd_req_ptr->sc.cdb, pccb->cmd, cdb_len); 1428 1429 memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 1430 ufshcd_cache_flush_and_invalidate(ucd_req_ptr, sizeof(*ucd_req_ptr)); 1431 ufshcd_cache_flush_and_invalidate(hba->ucd_rsp_ptr, sizeof(*hba->ucd_rsp_ptr)); 1432 } 1433 1434 static inline void prepare_prdt_desc(struct ufshcd_sg_entry *entry, 1435 unsigned char *buf, ulong len) 1436 { 1437 entry->size = cpu_to_le32(len) | GENMASK(1, 0); 1438 entry->base_addr = cpu_to_le32(lower_32_bits((unsigned long)buf)); 1439 entry->upper_addr = cpu_to_le32(upper_32_bits((unsigned long)buf)); 1440 } 1441 1442 static void prepare_prdt_table(struct ufs_hba *hba, struct scsi_cmd *pccb) 1443 { 1444 struct utp_transfer_req_desc *req_desc = hba->utrdl; 1445 struct ufshcd_sg_entry *prd_table = hba->ucd_prdt_ptr; 1446 uintptr_t aaddr = (uintptr_t)(pccb->pdata) & ~(ARCH_DMA_MINALIGN - 1); 1447 ulong datalen = pccb->datalen; 1448 int table_length; 1449 u8 *buf; 1450 int i; 1451 1452 if (!datalen) { 1453 req_desc->prd_table_length = 0; 1454 ufshcd_cache_flush_and_invalidate(req_desc, sizeof(*req_desc)); 1455 return; 1456 } 1457 1458 if (pccb->dma_dir == DMA_TO_DEVICE) { /* Write to device */ 1459 flush_dcache_range(aaddr, aaddr + 1460 ALIGN(datalen, ARCH_DMA_MINALIGN)); 1461 } 1462 1463 /* In any case, invalidate cache to avoid stale data in it. */ 1464 invalidate_dcache_range(aaddr, aaddr + 1465 ALIGN(datalen, ARCH_DMA_MINALIGN)); 1466 1467 table_length = DIV_ROUND_UP(pccb->datalen, MAX_PRDT_ENTRY); 1468 buf = pccb->pdata; 1469 i = table_length; 1470 while (--i) { 1471 prepare_prdt_desc(&prd_table[table_length - i - 1], buf, 1472 MAX_PRDT_ENTRY - 1); 1473 buf += MAX_PRDT_ENTRY; 1474 datalen -= MAX_PRDT_ENTRY; 1475 } 1476 1477 prepare_prdt_desc(&prd_table[table_length - i - 1], buf, datalen - 1); 1478 1479 req_desc->prd_table_length = table_length; 1480 ufshcd_cache_flush_and_invalidate(prd_table, sizeof(*prd_table) * table_length); 1481 ufshcd_cache_flush_and_invalidate(req_desc, sizeof(*req_desc)); 1482 } 1483 1484 static int ufs_scsi_exec(struct udevice *scsi_dev, struct scsi_cmd *pccb) 1485 { 1486 struct ufs_hba *hba = dev_get_uclass_priv(scsi_dev->parent); 1487 struct utp_transfer_req_desc *req_desc = hba->utrdl; 1488 u32 upiu_flags; 1489 int ocs, result = 0; 1490 u8 scsi_status; 1491 1492 ufshcd_prepare_req_desc_hdr(req_desc, &upiu_flags, pccb->dma_dir); 1493 ufshcd_prepare_utp_scsi_cmd_upiu(hba, pccb, upiu_flags); 1494 prepare_prdt_table(hba, pccb); 1495 1496 ufshcd_send_command(hba, TASK_TAG); 1497 1498 ocs = ufshcd_get_tr_ocs(hba); 1499 switch (ocs) { 1500 case OCS_SUCCESS: 1501 result = ufshcd_get_req_rsp(hba->ucd_rsp_ptr); 1502 switch (result) { 1503 case UPIU_TRANSACTION_RESPONSE: 1504 result = ufshcd_get_rsp_upiu_result(hba->ucd_rsp_ptr); 1505 1506 scsi_status = result & MASK_SCSI_STATUS; 1507 if (scsi_status) 1508 return -EINVAL; 1509 1510 break; 1511 case UPIU_TRANSACTION_REJECT_UPIU: 1512 /* TODO: handle Reject UPIU Response */ 1513 dev_err(hba->dev, 1514 "Reject UPIU not fully implemented\n"); 1515 return -EINVAL; 1516 default: 1517 dev_err(hba->dev, 1518 "Unexpected request response code = %x\n", 1519 result); 1520 return -EINVAL; 1521 } 1522 break; 1523 default: 1524 dev_err(hba->dev, "OCS error from controller = %x\n", ocs); 1525 return -EINVAL; 1526 } 1527 1528 return 0; 1529 } 1530 1531 static inline int ufshcd_read_desc(struct ufs_hba *hba, enum desc_idn desc_id, 1532 int desc_index, u8 *buf, u32 size) 1533 { 1534 return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size); 1535 } 1536 1537 static int ufshcd_read_device_desc(struct ufs_hba *hba, u8 *buf, u32 size) 1538 { 1539 return ufshcd_read_desc(hba, QUERY_DESC_IDN_DEVICE, 0, buf, size); 1540 } 1541 1542 /** 1543 * ufshcd_read_string_desc - read string descriptor 1544 * 1545 */ 1546 int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index, 1547 u8 *buf, u32 size, bool ascii) 1548 { 1549 int err = 0; 1550 1551 err = ufshcd_read_desc(hba, QUERY_DESC_IDN_STRING, desc_index, buf, 1552 size); 1553 1554 if (err) { 1555 dev_err(hba->dev, "%s: reading String Desc failed after %d retries. err = %d\n", 1556 __func__, QUERY_REQ_RETRIES, err); 1557 goto out; 1558 } 1559 1560 if (ascii) { 1561 int desc_len; 1562 int ascii_len; 1563 int i; 1564 u8 *buff_ascii; 1565 1566 desc_len = buf[0]; 1567 /* remove header and divide by 2 to move from UTF16 to UTF8 */ 1568 ascii_len = (desc_len - QUERY_DESC_HDR_SIZE) / 2 + 1; 1569 if (size < ascii_len + QUERY_DESC_HDR_SIZE) { 1570 dev_err(hba->dev, "%s: buffer allocated size is too small\n", 1571 __func__); 1572 err = -ENOMEM; 1573 goto out; 1574 } 1575 1576 buff_ascii = kmalloc(ascii_len, GFP_KERNEL); 1577 if (!buff_ascii) { 1578 err = -ENOMEM; 1579 goto out; 1580 } 1581 1582 /* 1583 * the descriptor contains string in UTF16 format 1584 * we need to convert to utf-8 so it can be displayed 1585 */ 1586 utf16_to_utf8(buff_ascii, 1587 (uint16_t *)&buf[QUERY_DESC_HDR_SIZE], ascii_len); 1588 1589 /* replace non-printable or non-ASCII characters with spaces */ 1590 for (i = 0; i < ascii_len; i++) 1591 ufshcd_remove_non_printable(&buff_ascii[i]); 1592 1593 memset(buf + QUERY_DESC_HDR_SIZE, 0, 1594 size - QUERY_DESC_HDR_SIZE); 1595 memcpy(buf + QUERY_DESC_HDR_SIZE, buff_ascii, ascii_len); 1596 buf[QUERY_DESC_LENGTH_OFFSET] = ascii_len + QUERY_DESC_HDR_SIZE; 1597 kfree(buff_ascii); 1598 } 1599 out: 1600 return err; 1601 } 1602 1603 static int ufs_get_device_desc(struct ufs_hba *hba, 1604 struct ufs_dev_desc *dev_desc) 1605 { 1606 int err; 1607 size_t buff_len; 1608 u8 model_index; 1609 u8 *desc_buf; 1610 1611 buff_len = max_t(size_t, hba->desc_size.dev_desc, 1612 QUERY_DESC_MAX_SIZE + 1); 1613 desc_buf = kmalloc(buff_len, GFP_KERNEL); 1614 if (!desc_buf) { 1615 err = -ENOMEM; 1616 goto out; 1617 } 1618 1619 err = ufshcd_read_device_desc(hba, desc_buf, hba->desc_size.dev_desc); 1620 if (err) { 1621 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n", 1622 __func__, err); 1623 goto out; 1624 } 1625 1626 /* 1627 * getting vendor (manufacturerID) and Bank Index in big endian 1628 * format 1629 */ 1630 dev_desc->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 | 1631 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1]; 1632 1633 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME]; 1634 1635 /* Zero-pad entire buffer for string termination. */ 1636 memset(desc_buf, 0, buff_len); 1637 1638 err = ufshcd_read_string_desc(hba, model_index, desc_buf, 1639 QUERY_DESC_MAX_SIZE, true/*ASCII*/); 1640 if (err) { 1641 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n", 1642 __func__, err); 1643 goto out; 1644 } 1645 1646 desc_buf[QUERY_DESC_MAX_SIZE] = '\0'; 1647 strlcpy(dev_desc->model, (char *)(desc_buf + QUERY_DESC_HDR_SIZE), 1648 min_t(u8, desc_buf[QUERY_DESC_LENGTH_OFFSET], 1649 MAX_MODEL_LEN)); 1650 1651 /* Null terminate the model string */ 1652 dev_desc->model[MAX_MODEL_LEN] = '\0'; 1653 1654 out: 1655 kfree(desc_buf); 1656 return err; 1657 } 1658 1659 /** 1660 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device 1661 */ 1662 static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba) 1663 { 1664 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info; 1665 1666 if (hba->max_pwr_info.is_valid) 1667 return 0; 1668 1669 pwr_info->pwr_tx = FAST_MODE; 1670 pwr_info->pwr_rx = FAST_MODE; 1671 pwr_info->hs_rate = PA_HS_MODE_B; 1672 1673 /* Get the connected lane count */ 1674 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES), 1675 &pwr_info->lane_rx); 1676 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 1677 &pwr_info->lane_tx); 1678 1679 if (!pwr_info->lane_rx || !pwr_info->lane_tx) { 1680 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n", 1681 __func__, pwr_info->lane_rx, pwr_info->lane_tx); 1682 return -EINVAL; 1683 } 1684 1685 /* 1686 * First, get the maximum gears of HS speed. 1687 * If a zero value, it means there is no HSGEAR capability. 1688 * Then, get the maximum gears of PWM speed. 1689 */ 1690 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx); 1691 if (!pwr_info->gear_rx) { 1692 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), 1693 &pwr_info->gear_rx); 1694 if (!pwr_info->gear_rx) { 1695 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n", 1696 __func__, pwr_info->gear_rx); 1697 return -EINVAL; 1698 } 1699 pwr_info->pwr_rx = SLOW_MODE; 1700 } 1701 1702 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), 1703 &pwr_info->gear_tx); 1704 if (!pwr_info->gear_tx) { 1705 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), 1706 &pwr_info->gear_tx); 1707 if (!pwr_info->gear_tx) { 1708 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n", 1709 __func__, pwr_info->gear_tx); 1710 return -EINVAL; 1711 } 1712 pwr_info->pwr_tx = SLOW_MODE; 1713 } 1714 1715 hba->max_pwr_info.is_valid = true; 1716 return 0; 1717 } 1718 1719 static int ufshcd_change_power_mode(struct ufs_hba *hba, 1720 struct ufs_pa_layer_attr *pwr_mode) 1721 { 1722 int ret; 1723 1724 /* if already configured to the requested pwr_mode */ 1725 if (pwr_mode->gear_rx == hba->pwr_info.gear_rx && 1726 pwr_mode->gear_tx == hba->pwr_info.gear_tx && 1727 pwr_mode->lane_rx == hba->pwr_info.lane_rx && 1728 pwr_mode->lane_tx == hba->pwr_info.lane_tx && 1729 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx && 1730 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx && 1731 pwr_mode->hs_rate == hba->pwr_info.hs_rate) { 1732 dev_dbg(hba->dev, "%s: power already configured\n", __func__); 1733 return 0; 1734 } 1735 1736 /* 1737 * Configure attributes for power mode change with below. 1738 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION, 1739 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION, 1740 * - PA_HSSERIES 1741 */ 1742 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx); 1743 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES), 1744 pwr_mode->lane_rx); 1745 if (pwr_mode->pwr_rx == FASTAUTO_MODE || pwr_mode->pwr_rx == FAST_MODE) 1746 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE); 1747 else 1748 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE); 1749 1750 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx); 1751 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES), 1752 pwr_mode->lane_tx); 1753 if (pwr_mode->pwr_tx == FASTAUTO_MODE || pwr_mode->pwr_tx == FAST_MODE) 1754 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE); 1755 else 1756 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE); 1757 1758 if (pwr_mode->pwr_rx == FASTAUTO_MODE || 1759 pwr_mode->pwr_tx == FASTAUTO_MODE || 1760 pwr_mode->pwr_rx == FAST_MODE || 1761 pwr_mode->pwr_tx == FAST_MODE) 1762 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES), 1763 pwr_mode->hs_rate); 1764 1765 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4 | 1766 pwr_mode->pwr_tx); 1767 1768 if (ret) { 1769 dev_err(hba->dev, 1770 "%s: power mode change failed %d\n", __func__, ret); 1771 1772 return ret; 1773 } 1774 1775 /* Copy new Power Mode to power info */ 1776 memcpy(&hba->pwr_info, pwr_mode, sizeof(struct ufs_pa_layer_attr)); 1777 1778 return ret; 1779 } 1780 1781 /** 1782 * ufshcd_verify_dev_init() - Verify device initialization 1783 * 1784 */ 1785 static int ufshcd_verify_dev_init(struct ufs_hba *hba) 1786 { 1787 int retries; 1788 int err; 1789 1790 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) { 1791 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP, 1792 NOP_OUT_TIMEOUT); 1793 if (!err || err == -ETIMEDOUT) 1794 break; 1795 1796 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err); 1797 } 1798 1799 if (err) 1800 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err); 1801 1802 return err; 1803 } 1804 1805 /** 1806 * ufshcd_complete_dev_init() - checks device readiness 1807 */ 1808 static int ufshcd_complete_dev_init(struct ufs_hba *hba) 1809 { 1810 int i; 1811 int err; 1812 bool flag_res = 1; 1813 1814 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG, 1815 QUERY_FLAG_IDN_FDEVICEINIT, NULL); 1816 if (err) { 1817 dev_err(hba->dev, 1818 "%s setting fDeviceInit flag failed with error %d\n", 1819 __func__, err); 1820 goto out; 1821 } 1822 1823 /* poll for max. 1000 iterations for fDeviceInit flag to clear */ 1824 for (i = 0; i < 1000 && !err && flag_res; i++) 1825 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG, 1826 QUERY_FLAG_IDN_FDEVICEINIT, 1827 &flag_res); 1828 1829 if (err) 1830 dev_err(hba->dev, 1831 "%s reading fDeviceInit flag failed with error %d\n", 1832 __func__, err); 1833 else if (flag_res) 1834 dev_err(hba->dev, 1835 "%s fDeviceInit was not cleared by the device\n", 1836 __func__); 1837 1838 out: 1839 return err; 1840 } 1841 1842 static void ufshcd_def_desc_sizes(struct ufs_hba *hba) 1843 { 1844 hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE; 1845 hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE; 1846 hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE; 1847 hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE; 1848 hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE; 1849 hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE; 1850 hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE; 1851 } 1852 1853 int ufs_start(struct ufs_hba *hba) 1854 { 1855 struct ufs_dev_desc card = {0}; 1856 int ret; 1857 1858 ret = ufshcd_link_startup(hba); 1859 if (ret) 1860 return ret; 1861 1862 ret = ufshcd_verify_dev_init(hba); 1863 if (ret) 1864 return ret; 1865 1866 ret = ufshcd_complete_dev_init(hba); 1867 if (ret) 1868 return ret; 1869 1870 /* Init check for device descriptor sizes */ 1871 ufshcd_init_desc_sizes(hba); 1872 1873 ret = ufs_get_device_desc(hba, &card); 1874 if (ret) { 1875 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n", 1876 __func__, ret); 1877 1878 return ret; 1879 } 1880 1881 if (ufshcd_get_max_pwr_mode(hba)) { 1882 dev_err(hba->dev, 1883 "%s: Failed getting max supported power mode\n", 1884 __func__); 1885 } else { 1886 ret = ufshcd_change_power_mode(hba, &hba->max_pwr_info.info); 1887 if (ret) { 1888 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n", 1889 __func__, ret); 1890 1891 return ret; 1892 } 1893 1894 printf("Device at %s up at:", hba->dev->name); 1895 ufshcd_print_pwr_info(hba); 1896 } 1897 1898 return 0; 1899 } 1900 1901 int ufshcd_probe(struct udevice *ufs_dev, struct ufs_hba_ops *hba_ops) 1902 { 1903 struct ufs_hba *hba = dev_get_uclass_priv(ufs_dev); 1904 struct scsi_platdata *scsi_plat; 1905 struct udevice *scsi_dev; 1906 int err; 1907 1908 device_find_first_child(ufs_dev, &scsi_dev); 1909 if (!scsi_dev) 1910 return -ENODEV; 1911 1912 scsi_plat = dev_get_uclass_platdata(scsi_dev); 1913 scsi_plat->max_id = UFSHCD_MAX_ID; 1914 scsi_plat->max_lun = UFS_MAX_LUNS; 1915 //scsi_plat->max_bytes_per_req = UFS_MAX_BYTES; 1916 1917 hba->dev = ufs_dev; 1918 hba->ops = hba_ops; 1919 hba->mmio_base = (void *)dev_read_addr(ufs_dev); 1920 1921 /* Set descriptor lengths to specification defaults */ 1922 ufshcd_def_desc_sizes(hba); 1923 1924 ufshcd_ops_init(hba); 1925 1926 /* Read capabilties registers */ 1927 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES); 1928 1929 /* Get UFS version supported by the controller */ 1930 hba->version = ufshcd_get_ufs_version(hba); 1931 if (hba->version != UFSHCI_VERSION_10 && 1932 hba->version != UFSHCI_VERSION_11 && 1933 hba->version != UFSHCI_VERSION_20 && 1934 hba->version != UFSHCI_VERSION_21) 1935 dev_err(hba->dev, "invalid UFS version 0x%x\n", 1936 hba->version); 1937 1938 /* Get Interrupt bit mask per version */ 1939 hba->intr_mask = ufshcd_get_intr_mask(hba); 1940 1941 /* Allocate memory for host memory space */ 1942 err = ufshcd_memory_alloc(hba); 1943 if (err) { 1944 dev_err(hba->dev, "Memory allocation failed\n"); 1945 return err; 1946 } 1947 1948 /* Configure Local data structures */ 1949 ufshcd_host_memory_configure(hba); 1950 1951 /* 1952 * In order to avoid any spurious interrupt immediately after 1953 * registering UFS controller interrupt handler, clear any pending UFS 1954 * interrupt status and disable all the UFS interrupts. 1955 */ 1956 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS), 1957 REG_INTERRUPT_STATUS); 1958 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE); 1959 1960 err = ufshcd_hba_enable(hba); 1961 if (err) { 1962 dev_err(hba->dev, "Host controller enable failed\n"); 1963 return err; 1964 } 1965 1966 err = ufs_start(hba); 1967 if (err) 1968 return err; 1969 1970 return 0; 1971 } 1972 1973 int ufs_scsi_bind(struct udevice *ufs_dev, struct udevice **scsi_devp) 1974 { 1975 int ret = device_bind_driver(ufs_dev, "ufs_scsi", "ufs_scsi", 1976 scsi_devp); 1977 1978 return ret; 1979 } 1980 1981 static struct scsi_ops ufs_ops = { 1982 .exec = ufs_scsi_exec, 1983 }; 1984 1985 int ufs_probe_dev(int index) 1986 { 1987 struct udevice *dev; 1988 1989 return uclass_get_device(UCLASS_UFS, index, &dev); 1990 } 1991 1992 int ufs_probe(void) 1993 { 1994 struct udevice *dev; 1995 int ret, i; 1996 1997 for (i = 0;; i++) { 1998 ret = uclass_get_device(UCLASS_UFS, i, &dev); 1999 if (ret == -ENODEV) 2000 break; 2001 } 2002 2003 return 0; 2004 } 2005 2006 U_BOOT_DRIVER(ufs_scsi) = { 2007 .id = UCLASS_SCSI, 2008 .name = "ufs_scsi", 2009 .ops = &ufs_ops, 2010 }; 2011