1 // SPDX-License-Identifier: GPL-2.0+ 2 /** 3 * ufs.c - Universal Flash Subsystem (UFS) driver 4 * 5 * Taken from Linux Kernel v5.2 (drivers/scsi/ufs/ufshcd.c) and ported 6 * to u-boot. 7 * 8 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com 9 */ 10 #include <charset.h> 11 #include <common.h> 12 #include <dm.h> 13 #include <log.h> 14 #include <dm/lists.h> 15 #include <dm/device-internal.h> 16 #include <malloc.h> 17 #include <hexdump.h> 18 #include <scsi.h> 19 #include <asm/io.h> 20 #include <asm/dma-mapping.h> 21 #include <linux/bitops.h> 22 #include <linux/delay.h> 23 24 #if defined(CONFIG_SUPPORT_USBPLUG) 25 #include "ufs-rockchip-usbplug.h" 26 #endif 27 #include "ufs.h" 28 29 #define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\ 30 UTP_TASK_REQ_COMPL |\ 31 UFSHCD_ERROR_MASK) 32 /* maximum number of link-startup retries */ 33 #define DME_LINKSTARTUP_RETRIES 3 34 35 /* maximum number of retries for a general UIC command */ 36 #define UFS_UIC_COMMAND_RETRIES 3 37 38 /* Query request retries */ 39 #define QUERY_REQ_RETRIES 3 40 /* Query request timeout */ 41 #define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */ 42 43 /* maximum timeout in ms for a general UIC command */ 44 #define UFS_UIC_CMD_TIMEOUT 1000 45 /* NOP OUT retries waiting for NOP IN response */ 46 /* Polling time to wait for fDeviceInit */ 47 #define FDEVICEINIT_COMPL_TIMEOUT 1500 /* millisecs */ 48 49 #define NOP_OUT_RETRIES 10 50 /* Timeout after 30 msecs if NOP OUT hangs without response */ 51 #define NOP_OUT_TIMEOUT 30 /* msecs */ 52 53 /* Only use one Task Tag for all requests */ 54 #define TASK_TAG 0 55 56 /* Expose the flag value from utp_upiu_query.value */ 57 #define MASK_QUERY_UPIU_FLAG_LOC 0xFF 58 59 #define MAX_PRDT_ENTRY 262144 60 61 /* maximum bytes per request */ 62 #define UFS_MAX_BYTES (128 * 256 * 1024) 63 64 static inline bool ufshcd_is_hba_active(struct ufs_hba *hba); 65 static inline void ufshcd_hba_stop(struct ufs_hba *hba); 66 static int ufshcd_hba_enable(struct ufs_hba *hba); 67 68 /* 69 * ufshcd_wait_for_register - wait for register value to change 70 */ 71 static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask, 72 u32 val, unsigned long timeout_ms) 73 { 74 int err = 0; 75 unsigned long start = get_timer(0); 76 77 /* ignore bits that we don't intend to wait on */ 78 val = val & mask; 79 80 while ((ufshcd_readl(hba, reg) & mask) != val) { 81 if (get_timer(start) > timeout_ms) { 82 if ((ufshcd_readl(hba, reg) & mask) != val) 83 err = -ETIMEDOUT; 84 break; 85 } 86 } 87 88 return err; 89 } 90 91 /** 92 * ufshcd_init_pwr_info - setting the POR (power on reset) 93 * values in hba power info 94 */ 95 static void ufshcd_init_pwr_info(struct ufs_hba *hba) 96 { 97 hba->pwr_info.gear_rx = UFS_PWM_G1; 98 hba->pwr_info.gear_tx = UFS_PWM_G1; 99 hba->pwr_info.lane_rx = 1; 100 hba->pwr_info.lane_tx = 1; 101 hba->pwr_info.pwr_rx = SLOWAUTO_MODE; 102 hba->pwr_info.pwr_tx = SLOWAUTO_MODE; 103 hba->pwr_info.hs_rate = 0; 104 } 105 106 /** 107 * ufshcd_print_pwr_info - print power params as saved in hba 108 * power info 109 */ 110 static void ufshcd_print_pwr_info(struct ufs_hba *hba) 111 { 112 static const char * const names[] = { 113 "INVALID MODE", 114 "FAST MODE", 115 "SLOW_MODE", 116 "INVALID MODE", 117 "FASTAUTO_MODE", 118 "SLOWAUTO_MODE", 119 "INVALID MODE", 120 }; 121 122 dev_err(hba->dev, "[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n", 123 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx, 124 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx, 125 names[hba->pwr_info.pwr_rx], 126 names[hba->pwr_info.pwr_tx], 127 hba->pwr_info.hs_rate); 128 } 129 130 /** 131 * ufshcd_ready_for_uic_cmd - Check if controller is ready 132 * to accept UIC commands 133 */ 134 static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba) 135 { 136 if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY) 137 return true; 138 else 139 return false; 140 } 141 142 /** 143 * ufshcd_get_uic_cmd_result - Get the UIC command result 144 */ 145 static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba) 146 { 147 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) & 148 MASK_UIC_COMMAND_RESULT; 149 } 150 151 /** 152 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command 153 */ 154 static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba) 155 { 156 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3); 157 } 158 159 /** 160 * ufshcd_is_device_present - Check if any device connected to 161 * the host controller 162 */ 163 static inline bool ufshcd_is_device_present(struct ufs_hba *hba) 164 { 165 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & 166 DEVICE_PRESENT) ? true : false; 167 } 168 169 /** 170 * ufshcd_send_uic_cmd - UFS Interconnect layer command API 171 * 172 */ 173 static int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 174 { 175 unsigned long start = 0; 176 u32 intr_status; 177 u32 enabled_intr_status; 178 179 if (!ufshcd_ready_for_uic_cmd(hba)) { 180 dev_err(hba->dev, 181 "Controller not ready to accept UIC commands\n"); 182 return -EIO; 183 } 184 185 debug("sending uic command:%d\n", uic_cmd->command); 186 187 /* Write Args */ 188 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1); 189 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2); 190 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3); 191 192 /* Write UIC Cmd */ 193 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK, 194 REG_UIC_COMMAND); 195 196 start = get_timer(0); 197 do { 198 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 199 enabled_intr_status = intr_status & hba->intr_mask; 200 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS); 201 202 if (get_timer(start) > UFS_UIC_CMD_TIMEOUT) { 203 dev_err(hba->dev, 204 "Timedout waiting for UIC response\n"); 205 206 return -ETIMEDOUT; 207 } 208 209 if (enabled_intr_status & UFSHCD_ERROR_MASK) { 210 dev_err(hba->dev, "Error in status:%08x\n", 211 enabled_intr_status); 212 213 return -1; 214 } 215 } while (!(enabled_intr_status & UFSHCD_UIC_MASK)); 216 217 uic_cmd->argument2 = ufshcd_get_uic_cmd_result(hba); 218 uic_cmd->argument3 = ufshcd_get_dme_attr_val(hba); 219 220 debug("Sent successfully\n"); 221 222 return 0; 223 } 224 225 /** 226 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET 227 * 228 */ 229 int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, u8 attr_set, 230 u32 mib_val, u8 peer) 231 { 232 struct uic_command uic_cmd = {0}; 233 static const char *const action[] = { 234 "dme-set", 235 "dme-peer-set" 236 }; 237 const char *set = action[!!peer]; 238 int ret; 239 int retries = UFS_UIC_COMMAND_RETRIES; 240 241 uic_cmd.command = peer ? 242 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET; 243 uic_cmd.argument1 = attr_sel; 244 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set); 245 uic_cmd.argument3 = mib_val; 246 247 do { 248 /* for peer attributes we retry upon failure */ 249 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 250 if (ret) 251 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n", 252 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret); 253 } while (ret && peer && --retries); 254 255 if (ret) 256 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n", 257 set, UIC_GET_ATTR_ID(attr_sel), mib_val, 258 UFS_UIC_COMMAND_RETRIES - retries); 259 260 return ret; 261 } 262 263 /** 264 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET 265 * 266 */ 267 int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, 268 u32 *mib_val, u8 peer) 269 { 270 struct uic_command uic_cmd = {0}; 271 static const char *const action[] = { 272 "dme-get", 273 "dme-peer-get" 274 }; 275 const char *get = action[!!peer]; 276 int ret; 277 int retries = UFS_UIC_COMMAND_RETRIES; 278 279 uic_cmd.command = peer ? 280 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET; 281 uic_cmd.argument1 = attr_sel; 282 283 do { 284 /* for peer attributes we retry upon failure */ 285 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 286 if (ret) 287 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n", 288 get, UIC_GET_ATTR_ID(attr_sel), ret); 289 } while (ret && peer && --retries); 290 291 if (ret) 292 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n", 293 get, UIC_GET_ATTR_ID(attr_sel), 294 UFS_UIC_COMMAND_RETRIES - retries); 295 296 if (mib_val && !ret) 297 *mib_val = uic_cmd.argument3; 298 299 return ret; 300 } 301 302 static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer) 303 { 304 u32 tx_lanes, i, err = 0; 305 306 if (!peer) 307 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 308 &tx_lanes); 309 else 310 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 311 &tx_lanes); 312 for (i = 0; i < tx_lanes; i++) { 313 if (!peer) 314 err = ufshcd_dme_set(hba, 315 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, 316 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), 317 0); 318 else 319 err = ufshcd_dme_peer_set(hba, 320 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, 321 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), 322 0); 323 if (err) { 324 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d\n", 325 __func__, peer, i, err); 326 break; 327 } 328 } 329 330 return err; 331 } 332 333 static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba) 334 { 335 return ufshcd_disable_tx_lcc(hba, true); 336 } 337 338 /** 339 * ufshcd_dme_link_startup - Notify Unipro to perform link startup 340 * 341 */ 342 static int ufshcd_dme_link_startup(struct ufs_hba *hba) 343 { 344 struct uic_command uic_cmd = {0}; 345 int ret; 346 347 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP; 348 349 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 350 if (ret) 351 dev_dbg(hba->dev, 352 "dme-link-startup: error code %d\n", ret); 353 return ret; 354 } 355 356 int ufshcd_dme_enable(struct ufs_hba *hba) 357 { 358 struct uic_command uic_cmd = {0}; 359 int ret; 360 361 uic_cmd.command = UIC_CMD_DME_ENABLE; 362 363 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 364 if (ret) 365 dev_err(hba->dev, 366 "dme-enable: error code %d\n", ret); 367 return ret; 368 } 369 370 int ufshcd_dme_reset(struct ufs_hba *hba) 371 { 372 struct uic_command uic_cmd = {0}; 373 int ret; 374 375 uic_cmd.command = UIC_CMD_DME_RESET; 376 377 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 378 if (ret) 379 dev_err(hba->dev, 380 "dme-reset: error code %d\n", ret); 381 return ret; 382 } 383 384 /** 385 * ufshcd_disable_intr_aggr - Disables interrupt aggregation. 386 * 387 */ 388 static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba) 389 { 390 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 391 } 392 393 /** 394 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY 395 */ 396 static inline int ufshcd_get_lists_status(u32 reg) 397 { 398 return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY); 399 } 400 401 /** 402 * ufshcd_enable_run_stop_reg - Enable run-stop registers, 403 * When run-stop registers are set to 1, it indicates the 404 * host controller that it can process the requests 405 */ 406 static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba) 407 { 408 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT, 409 REG_UTP_TASK_REQ_LIST_RUN_STOP); 410 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT, 411 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP); 412 } 413 414 /** 415 * ufshcd_enable_intr - enable interrupts 416 */ 417 static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs) 418 { 419 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 420 u32 rw; 421 422 if (hba->version == UFSHCI_VERSION_10) { 423 rw = set & INTERRUPT_MASK_RW_VER_10; 424 set = rw | ((set ^ intrs) & intrs); 425 } else { 426 set |= intrs; 427 } 428 429 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); 430 431 hba->intr_mask = set; 432 } 433 434 /** 435 * ufshcd_make_hba_operational - Make UFS controller operational 436 * 437 * To bring UFS host controller to operational state, 438 * 1. Enable required interrupts 439 * 2. Configure interrupt aggregation 440 * 3. Program UTRL and UTMRL base address 441 * 4. Configure run-stop-registers 442 * 443 */ 444 static int ufshcd_make_hba_operational(struct ufs_hba *hba) 445 { 446 int err = 0; 447 u32 reg; 448 449 /* Enable required interrupts */ 450 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS); 451 452 /* Disable interrupt aggregation */ 453 ufshcd_disable_intr_aggr(hba); 454 455 /* Configure UTRL and UTMRL base address registers */ 456 ufshcd_writel(hba, lower_32_bits((dma_addr_t)hba->utrdl), 457 REG_UTP_TRANSFER_REQ_LIST_BASE_L); 458 ufshcd_writel(hba, upper_32_bits((dma_addr_t)hba->utrdl), 459 REG_UTP_TRANSFER_REQ_LIST_BASE_H); 460 ufshcd_writel(hba, lower_32_bits((dma_addr_t)hba->utmrdl), 461 REG_UTP_TASK_REQ_LIST_BASE_L); 462 ufshcd_writel(hba, upper_32_bits((dma_addr_t)hba->utmrdl), 463 REG_UTP_TASK_REQ_LIST_BASE_H); 464 465 /* 466 * UCRDY, UTMRLDY and UTRLRDY bits must be 1 467 */ 468 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS); 469 if (!(ufshcd_get_lists_status(reg))) { 470 ufshcd_enable_run_stop_reg(hba); 471 } else { 472 dev_err(hba->dev, 473 "Host controller not ready to process requests\n"); 474 err = -EIO; 475 goto out; 476 } 477 478 out: 479 return err; 480 } 481 482 /** 483 * ufshcd_link_startup - Initialize unipro link startup 484 */ 485 static int ufshcd_link_startup(struct ufs_hba *hba) 486 { 487 int ret; 488 int retries = DME_LINKSTARTUP_RETRIES; 489 bool link_startup_again = true; 490 491 link_startup: 492 do { 493 ufshcd_ops_link_startup_notify(hba, PRE_CHANGE); 494 495 ret = ufshcd_dme_link_startup(hba); 496 497 /* check if device is detected by inter-connect layer */ 498 if (!ret && !ufshcd_is_device_present(hba)) { 499 dev_err(hba->dev, "%s: Device not present\n", __func__); 500 ret = -ENXIO; 501 goto out; 502 } 503 504 /* 505 * DME link lost indication is only received when link is up, 506 * but we can't be sure if the link is up until link startup 507 * succeeds. So reset the local Uni-Pro and try again. 508 */ 509 if (ret && ufshcd_hba_enable(hba)) 510 goto out; 511 } while (ret && retries--); 512 513 if (ret) 514 /* failed to get the link up... retire */ 515 goto out; 516 517 if (link_startup_again) { 518 link_startup_again = false; 519 retries = DME_LINKSTARTUP_RETRIES; 520 goto link_startup; 521 } 522 523 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */ 524 ufshcd_init_pwr_info(hba); 525 526 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) { 527 ret = ufshcd_disable_device_tx_lcc(hba); 528 if (ret) 529 goto out; 530 } 531 532 /* Include any host controller configuration via UIC commands */ 533 ret = ufshcd_ops_link_startup_notify(hba, POST_CHANGE); 534 if (ret) 535 goto out; 536 537 ret = ufshcd_make_hba_operational(hba); 538 out: 539 if (ret) 540 dev_err(hba->dev, "link startup failed %d\n", ret); 541 542 return ret; 543 } 544 545 /** 546 * ufshcd_hba_stop - Send controller to reset state 547 */ 548 static inline void ufshcd_hba_stop(struct ufs_hba *hba) 549 { 550 int err; 551 552 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE); 553 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE, 554 CONTROLLER_ENABLE, CONTROLLER_DISABLE, 555 10); 556 if (err) 557 dev_err(hba->dev, "%s: Controller disable failed\n", __func__); 558 } 559 560 /** 561 * ufshcd_is_hba_active - Get controller state 562 */ 563 static inline bool ufshcd_is_hba_active(struct ufs_hba *hba) 564 { 565 return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE) 566 ? false : true; 567 } 568 569 /** 570 * ufshcd_hba_start - Start controller initialization sequence 571 */ 572 static inline void ufshcd_hba_start(struct ufs_hba *hba) 573 { 574 ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE); 575 } 576 577 /** 578 * ufshcd_hba_enable - initialize the controller 579 */ 580 static int ufshcd_hba_enable(struct ufs_hba *hba) 581 { 582 int retry; 583 584 if (!ufshcd_is_hba_active(hba)) 585 /* change controller state to "reset state" */ 586 ufshcd_hba_stop(hba); 587 588 ufshcd_ops_hce_enable_notify(hba, PRE_CHANGE); 589 590 /* start controller initialization sequence */ 591 ufshcd_hba_start(hba); 592 593 /* 594 * To initialize a UFS host controller HCE bit must be set to 1. 595 * During initialization the HCE bit value changes from 1->0->1. 596 * When the host controller completes initialization sequence 597 * it sets the value of HCE bit to 1. The same HCE bit is read back 598 * to check if the controller has completed initialization sequence. 599 * So without this delay the value HCE = 1, set in the previous 600 * instruction might be read back. 601 * This delay can be changed based on the controller. 602 */ 603 mdelay(1); 604 605 /* wait for the host controller to complete initialization */ 606 retry = 10; 607 while (ufshcd_is_hba_active(hba)) { 608 if (retry) { 609 retry--; 610 } else { 611 dev_err(hba->dev, "Controller enable failed\n"); 612 return -EIO; 613 } 614 mdelay(5); 615 } 616 617 /* enable UIC related interrupts */ 618 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK); 619 620 if (ufshcd_ops_hce_enable_notify(hba, POST_CHANGE)) 621 return -EIO; 622 623 return 0; 624 } 625 626 /** 627 * ufshcd_host_memory_configure - configure local reference block with 628 * memory offsets 629 */ 630 static void ufshcd_host_memory_configure(struct ufs_hba *hba) 631 { 632 struct utp_transfer_req_desc *utrdlp; 633 dma_addr_t cmd_desc_dma_addr; 634 u16 response_offset; 635 u16 prdt_offset; 636 637 utrdlp = hba->utrdl; 638 cmd_desc_dma_addr = (dma_addr_t)hba->ucdl; 639 640 utrdlp->command_desc_base_addr_lo = 641 cpu_to_le32(lower_32_bits(cmd_desc_dma_addr)); 642 utrdlp->command_desc_base_addr_hi = 643 cpu_to_le32(upper_32_bits(cmd_desc_dma_addr)); 644 645 response_offset = offsetof(struct utp_transfer_cmd_desc, response_upiu); 646 prdt_offset = offsetof(struct utp_transfer_cmd_desc, prd_table); 647 648 utrdlp->response_upiu_offset = cpu_to_le16(response_offset >> 2); 649 utrdlp->prd_table_offset = cpu_to_le16(prdt_offset >> 2); 650 utrdlp->response_upiu_length = cpu_to_le16(ALIGNED_UPIU_SIZE >> 2); 651 652 hba->ucd_req_ptr = (struct utp_upiu_req *)hba->ucdl; 653 hba->ucd_rsp_ptr = 654 (struct utp_upiu_rsp *)&hba->ucdl->response_upiu; 655 hba->ucd_prdt_ptr = 656 (struct ufshcd_sg_entry *)&hba->ucdl->prd_table; 657 } 658 659 /** 660 * ufshcd_memory_alloc - allocate memory for host memory space data structures 661 */ 662 static int ufshcd_memory_alloc(struct ufs_hba *hba) 663 { 664 /* Allocate one Transfer Request Descriptor 665 * Should be aligned to 1k boundary. 666 */ 667 hba->utrdl = memalign(1024, sizeof(struct utp_transfer_req_desc)); 668 if (!hba->utrdl) { 669 dev_err(hba->dev, "Transfer Descriptor memory allocation failed\n"); 670 return -ENOMEM; 671 } 672 673 /* Allocate one Command Descriptor 674 * Should be aligned to 1k boundary. 675 */ 676 hba->ucdl = memalign(1024, sizeof(struct utp_transfer_cmd_desc)); 677 if (!hba->ucdl) { 678 dev_err(hba->dev, "Command descriptor memory allocation failed\n"); 679 return -ENOMEM; 680 } 681 682 hba->dev_desc = memalign(ARCH_DMA_MINALIGN, sizeof(struct ufs_device_descriptor)); 683 if (!hba->dev_desc) { 684 dev_err(hba->dev, "memory allocation failed\n"); 685 return -ENOMEM; 686 } 687 688 #if defined(CONFIG_SUPPORT_USBPLUG) 689 hba->rc_desc = memalign(ARCH_DMA_MINALIGN, sizeof(struct ufs_configuration_descriptor)); 690 hba->wc_desc = memalign(ARCH_DMA_MINALIGN, sizeof(struct ufs_configuration_descriptor)); 691 hba->geo_desc = memalign(ARCH_DMA_MINALIGN, sizeof(struct ufs_geometry_descriptor)); 692 if (!hba->rc_desc || !hba->wc_desc || !hba->geo_desc) { 693 dev_err(hba->dev, "memory allocation failed\n"); 694 return -ENOMEM; 695 } 696 #endif 697 return 0; 698 } 699 700 /** 701 * ufshcd_get_intr_mask - Get the interrupt bit mask 702 */ 703 static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba) 704 { 705 u32 intr_mask = 0; 706 707 switch (hba->version) { 708 case UFSHCI_VERSION_10: 709 intr_mask = INTERRUPT_MASK_ALL_VER_10; 710 break; 711 case UFSHCI_VERSION_11: 712 case UFSHCI_VERSION_20: 713 intr_mask = INTERRUPT_MASK_ALL_VER_11; 714 break; 715 case UFSHCI_VERSION_21: 716 default: 717 intr_mask = INTERRUPT_MASK_ALL_VER_21; 718 break; 719 } 720 721 return intr_mask; 722 } 723 724 /** 725 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA 726 */ 727 static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba) 728 { 729 return ufshcd_readl(hba, REG_UFS_VERSION); 730 } 731 732 /** 733 * ufshcd_get_upmcrs - Get the power mode change request status 734 */ 735 static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba) 736 { 737 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7; 738 } 739 740 /** 741 * ufshcd_cache_flush_and_invalidate - Flush and invalidate cache 742 * 743 * Flush and invalidate cache in aligned address..address+size range. 744 * The invalidation is in place to avoid stale data in cache. 745 */ 746 static void ufshcd_cache_flush_and_invalidate(void *addr, unsigned long size) 747 { 748 uintptr_t aaddr = (uintptr_t)addr & ~(ARCH_DMA_MINALIGN - 1); 749 unsigned long asize = ALIGN(size, ARCH_DMA_MINALIGN); 750 751 flush_dcache_range(aaddr, aaddr + asize); 752 invalidate_dcache_range(aaddr, aaddr + asize); 753 } 754 755 /** 756 * ufshcd_prepare_req_desc_hdr() - Fills the requests header 757 * descriptor according to request 758 */ 759 static void ufshcd_prepare_req_desc_hdr(struct utp_transfer_req_desc *req_desc, 760 u32 *upiu_flags, 761 enum dma_data_direction cmd_dir) 762 { 763 u32 data_direction; 764 u32 dword_0; 765 766 if (cmd_dir == DMA_FROM_DEVICE) { 767 data_direction = UTP_DEVICE_TO_HOST; 768 *upiu_flags = UPIU_CMD_FLAGS_READ; 769 } else if (cmd_dir == DMA_TO_DEVICE) { 770 data_direction = UTP_HOST_TO_DEVICE; 771 *upiu_flags = UPIU_CMD_FLAGS_WRITE; 772 } else { 773 data_direction = UTP_NO_DATA_TRANSFER; 774 *upiu_flags = UPIU_CMD_FLAGS_NONE; 775 } 776 777 dword_0 = data_direction | (0x1 << UPIU_COMMAND_TYPE_OFFSET); 778 779 /* Enable Interrupt for command */ 780 dword_0 |= UTP_REQ_DESC_INT_CMD; 781 782 /* Transfer request descriptor header fields */ 783 req_desc->header.dword_0 = cpu_to_le32(dword_0); 784 /* dword_1 is reserved, hence it is set to 0 */ 785 req_desc->header.dword_1 = 0; 786 /* 787 * assigning invalid value for command status. Controller 788 * updates OCS on command completion, with the command 789 * status 790 */ 791 req_desc->header.dword_2 = 792 cpu_to_le32(OCS_INVALID_COMMAND_STATUS); 793 /* dword_3 is reserved, hence it is set to 0 */ 794 req_desc->header.dword_3 = 0; 795 796 req_desc->prd_table_length = 0; 797 798 ufshcd_cache_flush_and_invalidate(req_desc, sizeof(*req_desc)); 799 } 800 801 static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba, 802 u32 upiu_flags) 803 { 804 struct utp_upiu_req *ucd_req_ptr = hba->ucd_req_ptr; 805 struct ufs_query *query = &hba->dev_cmd.query; 806 u16 len = be16_to_cpu(query->request.upiu_req.length); 807 808 /* Query request header */ 809 ucd_req_ptr->header.dword_0 = 810 UPIU_HEADER_DWORD(UPIU_TRANSACTION_QUERY_REQ, 811 upiu_flags, 0, TASK_TAG); 812 ucd_req_ptr->header.dword_1 = 813 UPIU_HEADER_DWORD(0, query->request.query_func, 814 0, 0); 815 816 /* Data segment length only need for WRITE_DESC */ 817 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC) 818 ucd_req_ptr->header.dword_2 = 819 UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len); 820 else 821 ucd_req_ptr->header.dword_2 = 0; 822 823 /* Copy the Query Request buffer as is */ 824 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req, QUERY_OSF_SIZE); 825 826 /* Copy the Descriptor */ 827 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC) { 828 memcpy(ucd_req_ptr + 1, query->descriptor, len); 829 ufshcd_cache_flush_and_invalidate(ucd_req_ptr, 830 ALIGN(sizeof(*ucd_req_ptr) + len, ARCH_DMA_MINALIGN)); 831 } else { 832 ufshcd_cache_flush_and_invalidate(ucd_req_ptr, sizeof(*ucd_req_ptr)); 833 } 834 835 memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 836 ufshcd_cache_flush_and_invalidate(hba->ucd_rsp_ptr, sizeof(*hba->ucd_rsp_ptr)); 837 } 838 839 static inline void ufshcd_prepare_utp_nop_upiu(struct ufs_hba *hba) 840 { 841 struct utp_upiu_req *ucd_req_ptr = hba->ucd_req_ptr; 842 843 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req)); 844 845 /* command descriptor fields */ 846 ucd_req_ptr->header.dword_0 = 847 UPIU_HEADER_DWORD(UPIU_TRANSACTION_NOP_OUT, 0, 0, TASK_TAG); 848 /* clear rest of the fields of basic header */ 849 ucd_req_ptr->header.dword_1 = 0; 850 ucd_req_ptr->header.dword_2 = 0; 851 852 memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 853 854 ufshcd_cache_flush_and_invalidate(ucd_req_ptr, sizeof(*ucd_req_ptr)); 855 ufshcd_cache_flush_and_invalidate(hba->ucd_rsp_ptr, sizeof(*hba->ucd_rsp_ptr)); 856 } 857 858 /** 859 * ufshcd_comp_devman_upiu - UFS Protocol Information Unit(UPIU) 860 * for Device Management Purposes 861 */ 862 static int ufshcd_comp_devman_upiu(struct ufs_hba *hba, 863 enum dev_cmd_type cmd_type) 864 { 865 u32 upiu_flags; 866 int ret = 0; 867 struct utp_transfer_req_desc *req_desc = hba->utrdl; 868 869 hba->dev_cmd.type = cmd_type; 870 871 ufshcd_prepare_req_desc_hdr(req_desc, &upiu_flags, DMA_NONE); 872 switch (cmd_type) { 873 case DEV_CMD_TYPE_QUERY: 874 ufshcd_prepare_utp_query_req_upiu(hba, upiu_flags); 875 break; 876 case DEV_CMD_TYPE_NOP: 877 ufshcd_prepare_utp_nop_upiu(hba); 878 break; 879 default: 880 ret = -EINVAL; 881 } 882 883 return ret; 884 } 885 886 static int ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag) 887 { 888 unsigned long start; 889 u32 intr_status; 890 u32 enabled_intr_status; 891 892 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL); 893 894 start = get_timer(0); 895 do { 896 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 897 enabled_intr_status = intr_status & hba->intr_mask; 898 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS); 899 900 if (get_timer(start) > QUERY_REQ_TIMEOUT) { 901 dev_err(hba->dev, 902 "Timedout waiting for UTP response\n"); 903 904 return -ETIMEDOUT; 905 } 906 907 if (enabled_intr_status & UFSHCD_ERROR_MASK) { 908 dev_err(hba->dev, "Error in status:%08x\n", 909 enabled_intr_status); 910 911 return -1; 912 } 913 } while (!(enabled_intr_status & UTP_TRANSFER_REQ_COMPL)); 914 915 return 0; 916 } 917 918 /** 919 * ufshcd_get_req_rsp - returns the TR response transaction type 920 */ 921 static inline int ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr) 922 { 923 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24; 924 } 925 926 /** 927 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status 928 * 929 */ 930 static inline int ufshcd_get_tr_ocs(struct ufs_hba *hba) 931 { 932 return le32_to_cpu(hba->utrdl->header.dword_2) & MASK_OCS; 933 } 934 935 static inline int ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr) 936 { 937 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT; 938 } 939 940 static int ufshcd_check_query_response(struct ufs_hba *hba) 941 { 942 struct ufs_query_res *query_res = &hba->dev_cmd.query.response; 943 944 /* Get the UPIU response */ 945 query_res->response = ufshcd_get_rsp_upiu_result(hba->ucd_rsp_ptr) >> 946 UPIU_RSP_CODE_OFFSET; 947 return query_res->response; 948 } 949 950 /** 951 * ufshcd_copy_query_response() - Copy the Query Response and the data 952 * descriptor 953 */ 954 static int ufshcd_copy_query_response(struct ufs_hba *hba) 955 { 956 struct ufs_query_res *query_res = &hba->dev_cmd.query.response; 957 958 memcpy(&query_res->upiu_res, &hba->ucd_rsp_ptr->qr, QUERY_OSF_SIZE); 959 960 /* Get the descriptor */ 961 if (hba->dev_cmd.query.descriptor && 962 hba->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) { 963 u8 *descp = (u8 *)hba->ucd_rsp_ptr + 964 GENERAL_UPIU_REQUEST_SIZE; 965 u16 resp_len; 966 u16 buf_len; 967 968 /* data segment length */ 969 resp_len = be32_to_cpu(hba->ucd_rsp_ptr->header.dword_2) & 970 MASK_QUERY_DATA_SEG_LEN; 971 buf_len = 972 be16_to_cpu(hba->dev_cmd.query.request.upiu_req.length); 973 if (likely(buf_len >= resp_len)) { 974 int size = ALIGN(GENERAL_UPIU_REQUEST_SIZE + resp_len, ARCH_DMA_MINALIGN); 975 976 invalidate_dcache_range((uintptr_t)hba->ucd_rsp_ptr, (uintptr_t)hba->ucd_rsp_ptr + size); 977 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len); 978 } else { 979 dev_warn(hba->dev, 980 "%s: Response size is bigger than buffer", 981 __func__); 982 return -EINVAL; 983 } 984 } 985 986 return 0; 987 } 988 989 /** 990 * ufshcd_exec_dev_cmd - API for sending device management requests 991 */ 992 int ufshcd_exec_dev_cmd(struct ufs_hba *hba, enum dev_cmd_type cmd_type, int timeout) 993 { 994 int err; 995 int resp; 996 997 err = ufshcd_comp_devman_upiu(hba, cmd_type); 998 if (err) 999 return err; 1000 1001 err = ufshcd_send_command(hba, TASK_TAG); 1002 if (err) 1003 return err; 1004 1005 err = ufshcd_get_tr_ocs(hba); 1006 if (err) { 1007 dev_err(hba->dev, "Error in OCS:%d\n", err); 1008 return -EINVAL; 1009 } 1010 1011 resp = ufshcd_get_req_rsp(hba->ucd_rsp_ptr); 1012 switch (resp) { 1013 case UPIU_TRANSACTION_NOP_IN: 1014 break; 1015 case UPIU_TRANSACTION_QUERY_RSP: 1016 err = ufshcd_check_query_response(hba); 1017 if (!err) 1018 err = ufshcd_copy_query_response(hba); 1019 break; 1020 case UPIU_TRANSACTION_REJECT_UPIU: 1021 /* TODO: handle Reject UPIU Response */ 1022 err = -EPERM; 1023 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n", 1024 __func__); 1025 break; 1026 default: 1027 err = -EINVAL; 1028 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n", 1029 __func__, resp); 1030 } 1031 1032 return err; 1033 } 1034 1035 /** 1036 * ufshcd_init_query() - init the query response and request parameters 1037 */ 1038 static inline void ufshcd_init_query(struct ufs_hba *hba, 1039 struct ufs_query_req **request, 1040 struct ufs_query_res **response, 1041 enum query_opcode opcode, 1042 u8 idn, u8 index, u8 selector) 1043 { 1044 *request = &hba->dev_cmd.query.request; 1045 *response = &hba->dev_cmd.query.response; 1046 memset(*request, 0, sizeof(struct ufs_query_req)); 1047 memset(*response, 0, sizeof(struct ufs_query_res)); 1048 (*request)->upiu_req.opcode = opcode; 1049 (*request)->upiu_req.idn = idn; 1050 (*request)->upiu_req.index = index; 1051 (*request)->upiu_req.selector = selector; 1052 } 1053 1054 /** 1055 * ufshcd_query_flag() - API function for sending flag query requests 1056 */ 1057 int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode, 1058 enum flag_idn idn, bool *flag_res) 1059 { 1060 struct ufs_query_req *request = NULL; 1061 struct ufs_query_res *response = NULL; 1062 int err, index = 0, selector = 0; 1063 int timeout = QUERY_REQ_TIMEOUT; 1064 1065 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 1066 selector); 1067 1068 switch (opcode) { 1069 case UPIU_QUERY_OPCODE_SET_FLAG: 1070 case UPIU_QUERY_OPCODE_CLEAR_FLAG: 1071 case UPIU_QUERY_OPCODE_TOGGLE_FLAG: 1072 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 1073 break; 1074 case UPIU_QUERY_OPCODE_READ_FLAG: 1075 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 1076 if (!flag_res) { 1077 /* No dummy reads */ 1078 dev_err(hba->dev, "%s: Invalid argument for read request\n", 1079 __func__); 1080 err = -EINVAL; 1081 goto out; 1082 } 1083 break; 1084 default: 1085 dev_err(hba->dev, 1086 "%s: Expected query flag opcode but got = %d\n", 1087 __func__, opcode); 1088 err = -EINVAL; 1089 goto out; 1090 } 1091 1092 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout); 1093 1094 if (err) { 1095 dev_err(hba->dev, 1096 "%s: Sending flag query for idn %d failed, err = %d\n", 1097 __func__, idn, err); 1098 goto out; 1099 } 1100 1101 if (flag_res) 1102 *flag_res = (be32_to_cpu(response->upiu_res.value) & 1103 MASK_QUERY_UPIU_FLAG_LOC) & 0x1; 1104 1105 out: 1106 return err; 1107 } 1108 1109 static int ufshcd_query_flag_retry(struct ufs_hba *hba, 1110 enum query_opcode opcode, 1111 enum flag_idn idn, bool *flag_res) 1112 { 1113 int ret; 1114 int retries; 1115 1116 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) { 1117 ret = ufshcd_query_flag(hba, opcode, idn, flag_res); 1118 if (ret) 1119 dev_dbg(hba->dev, 1120 "%s: failed with error %d, retries %d\n", 1121 __func__, ret, retries); 1122 else 1123 break; 1124 } 1125 1126 if (ret) 1127 dev_err(hba->dev, 1128 "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n", 1129 __func__, opcode, idn, ret, retries); 1130 return ret; 1131 } 1132 1133 static int __ufshcd_query_descriptor(struct ufs_hba *hba, 1134 enum query_opcode opcode, 1135 enum desc_idn idn, u8 index, u8 selector, 1136 u8 *desc_buf, int *buf_len) 1137 { 1138 struct ufs_query_req *request = NULL; 1139 struct ufs_query_res *response = NULL; 1140 int err; 1141 1142 if (!desc_buf) { 1143 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n", 1144 __func__, opcode); 1145 err = -EINVAL; 1146 goto out; 1147 } 1148 1149 if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) { 1150 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n", 1151 __func__, *buf_len); 1152 err = -EINVAL; 1153 goto out; 1154 } 1155 1156 ufshcd_init_query(hba, &request, &response, opcode, idn, index, selector); 1157 hba->dev_cmd.query.descriptor = desc_buf; 1158 request->upiu_req.length = cpu_to_be16(*buf_len); 1159 1160 switch (opcode) { 1161 case UPIU_QUERY_OPCODE_WRITE_DESC: 1162 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 1163 break; 1164 case UPIU_QUERY_OPCODE_READ_DESC: 1165 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 1166 break; 1167 default: 1168 dev_err(hba->dev, "%s: Expected query descriptor opcode but got = 0x%.2x\n", 1169 __func__, opcode); 1170 err = -EINVAL; 1171 goto out; 1172 } 1173 1174 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 1175 1176 if (err) { 1177 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n", 1178 __func__, opcode, idn, index, err); 1179 goto out; 1180 } 1181 1182 hba->dev_cmd.query.descriptor = NULL; 1183 *buf_len = be16_to_cpu(response->upiu_res.length); 1184 1185 out: 1186 return err; 1187 } 1188 1189 /** 1190 * ufshcd_query_descriptor_retry - API function for sending descriptor requests 1191 */ 1192 int ufshcd_query_descriptor_retry(struct ufs_hba *hba, enum query_opcode opcode, 1193 enum desc_idn idn, u8 index, u8 selector, 1194 u8 *desc_buf, int *buf_len) 1195 { 1196 int err; 1197 int retries; 1198 1199 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) { 1200 err = __ufshcd_query_descriptor(hba, opcode, idn, index, 1201 selector, desc_buf, buf_len); 1202 if (!err || err == -EINVAL) 1203 break; 1204 } 1205 1206 return err; 1207 } 1208 1209 /** 1210 * ufshcd_read_desc_length - read the specified descriptor length from header 1211 */ 1212 int ufshcd_read_desc_length(struct ufs_hba *hba, enum desc_idn desc_id, 1213 int desc_index, int *desc_length) 1214 { 1215 int ret; 1216 u8 header[QUERY_DESC_HDR_SIZE]; 1217 int header_len = QUERY_DESC_HDR_SIZE; 1218 1219 if (desc_id >= QUERY_DESC_IDN_MAX) 1220 return -EINVAL; 1221 1222 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC, 1223 desc_id, desc_index, 0, header, 1224 &header_len); 1225 1226 if (ret) { 1227 dev_err(hba->dev, "%s: Failed to get descriptor header id %d\n", 1228 __func__, desc_id); 1229 return ret; 1230 } else if (desc_id != header[QUERY_DESC_DESC_TYPE_OFFSET]) { 1231 dev_warn(hba->dev, "%s: descriptor header id %d and desc_id %d mismatch\n", 1232 __func__, header[QUERY_DESC_DESC_TYPE_OFFSET], 1233 desc_id); 1234 ret = -EINVAL; 1235 } 1236 1237 *desc_length = header[QUERY_DESC_LENGTH_OFFSET]; 1238 1239 return ret; 1240 } 1241 1242 static void ufshcd_init_desc_sizes(struct ufs_hba *hba) 1243 { 1244 int err; 1245 1246 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_DEVICE, 0, 1247 &hba->desc_size.dev_desc); 1248 if (err) 1249 hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE; 1250 1251 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_POWER, 0, 1252 &hba->desc_size.pwr_desc); 1253 if (err) 1254 hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE; 1255 1256 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_INTERCONNECT, 0, 1257 &hba->desc_size.interc_desc); 1258 if (err) 1259 hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE; 1260 1261 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_CONFIGURATION, 0, 1262 &hba->desc_size.conf_desc); 1263 if (err) 1264 hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE; 1265 1266 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_UNIT, 0, 1267 &hba->desc_size.unit_desc); 1268 if (err) 1269 hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE; 1270 1271 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_GEOMETRY, 0, 1272 &hba->desc_size.geom_desc); 1273 if (err) 1274 hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE; 1275 1276 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_HEALTH, 0, 1277 &hba->desc_size.hlth_desc); 1278 if (err) 1279 hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE; 1280 } 1281 1282 /** 1283 * ufshcd_map_desc_id_to_length - map descriptor IDN to its length 1284 * 1285 */ 1286 int ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id, 1287 int *desc_len) 1288 { 1289 switch (desc_id) { 1290 case QUERY_DESC_IDN_DEVICE: 1291 *desc_len = hba->desc_size.dev_desc; 1292 break; 1293 case QUERY_DESC_IDN_POWER: 1294 *desc_len = hba->desc_size.pwr_desc; 1295 break; 1296 case QUERY_DESC_IDN_GEOMETRY: 1297 *desc_len = hba->desc_size.geom_desc; 1298 break; 1299 case QUERY_DESC_IDN_CONFIGURATION: 1300 *desc_len = hba->desc_size.conf_desc; 1301 break; 1302 case QUERY_DESC_IDN_UNIT: 1303 *desc_len = hba->desc_size.unit_desc; 1304 break; 1305 case QUERY_DESC_IDN_INTERCONNECT: 1306 *desc_len = hba->desc_size.interc_desc; 1307 break; 1308 case QUERY_DESC_IDN_STRING: 1309 *desc_len = QUERY_DESC_MAX_SIZE; 1310 break; 1311 case QUERY_DESC_IDN_HEALTH: 1312 *desc_len = hba->desc_size.hlth_desc; 1313 break; 1314 case QUERY_DESC_IDN_RFU_0: 1315 case QUERY_DESC_IDN_RFU_1: 1316 *desc_len = 0; 1317 break; 1318 default: 1319 *desc_len = 0; 1320 return -EINVAL; 1321 } 1322 return 0; 1323 } 1324 EXPORT_SYMBOL(ufshcd_map_desc_id_to_length); 1325 1326 /** 1327 * ufshcd_read_desc_param - read the specified descriptor parameter 1328 * 1329 */ 1330 int ufshcd_read_desc_param(struct ufs_hba *hba, enum desc_idn desc_id, 1331 int desc_index, u8 param_offset, u8 *param_read_buf, 1332 u8 param_size) 1333 { 1334 int ret; 1335 u8 *desc_buf; 1336 int buff_len; 1337 bool is_kmalloc = true; 1338 1339 /* Safety check */ 1340 if (desc_id >= QUERY_DESC_IDN_MAX || !param_size) 1341 return -EINVAL; 1342 1343 /* Get the max length of descriptor from structure filled up at probe 1344 * time. 1345 */ 1346 ret = ufshcd_map_desc_id_to_length(hba, desc_id, &buff_len); 1347 1348 /* Sanity checks */ 1349 if (ret || !buff_len) { 1350 dev_err(hba->dev, "%s: Failed to get full descriptor length\n", 1351 __func__); 1352 return ret; 1353 } 1354 1355 /* Check whether we need temp memory */ 1356 if (param_offset != 0 || param_size < buff_len) { 1357 desc_buf = kmalloc(buff_len, GFP_KERNEL); 1358 if (!desc_buf) 1359 return -ENOMEM; 1360 } else { 1361 desc_buf = param_read_buf; 1362 is_kmalloc = false; 1363 } 1364 1365 /* Request for full descriptor */ 1366 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC, 1367 desc_id, desc_index, 0, desc_buf, 1368 &buff_len); 1369 1370 if (ret) { 1371 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d\n", 1372 __func__, desc_id, desc_index, param_offset, ret); 1373 goto out; 1374 } 1375 1376 /* Sanity check */ 1377 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) { 1378 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header\n", 1379 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]); 1380 ret = -EINVAL; 1381 goto out; 1382 } 1383 1384 /* Check wherher we will not copy more data, than available */ 1385 if (is_kmalloc && param_size > buff_len) 1386 param_size = buff_len; 1387 1388 if (is_kmalloc) 1389 memcpy(param_read_buf, &desc_buf[param_offset], param_size); 1390 out: 1391 if (is_kmalloc) 1392 kfree(desc_buf); 1393 return ret; 1394 } 1395 1396 /* replace non-printable or non-ASCII characters with spaces */ 1397 static inline void ufshcd_remove_non_printable(uint8_t *val) 1398 { 1399 if (!val) 1400 return; 1401 1402 if (*val < 0x20 || *val > 0x7e) 1403 *val = ' '; 1404 } 1405 1406 /** 1407 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power 1408 * state) and waits for it to take effect. 1409 * 1410 */ 1411 static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd) 1412 { 1413 unsigned long start = 0; 1414 u8 status; 1415 int ret; 1416 1417 ret = ufshcd_send_uic_cmd(hba, cmd); 1418 if (ret) { 1419 dev_err(hba->dev, 1420 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n", 1421 cmd->command, cmd->argument3, ret); 1422 1423 return ret; 1424 } 1425 1426 start = get_timer(0); 1427 do { 1428 status = ufshcd_get_upmcrs(hba); 1429 if (get_timer(start) > UFS_UIC_CMD_TIMEOUT) { 1430 dev_err(hba->dev, 1431 "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n", 1432 cmd->command, status); 1433 ret = (status != PWR_OK) ? status : -1; 1434 break; 1435 } 1436 } while (status != PWR_LOCAL); 1437 1438 return ret; 1439 } 1440 1441 /** 1442 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode change 1443 * using DME_SET primitives. 1444 */ 1445 static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode) 1446 { 1447 struct uic_command uic_cmd = {0}; 1448 int ret; 1449 1450 uic_cmd.command = UIC_CMD_DME_SET; 1451 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE); 1452 uic_cmd.argument3 = mode; 1453 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 1454 1455 return ret; 1456 } 1457 1458 static 1459 void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufs_hba *hba, 1460 struct scsi_cmd *pccb, u32 upiu_flags) 1461 { 1462 struct utp_upiu_req *ucd_req_ptr = hba->ucd_req_ptr; 1463 unsigned int cdb_len; 1464 1465 /* command descriptor fields */ 1466 ucd_req_ptr->header.dword_0 = 1467 UPIU_HEADER_DWORD(UPIU_TRANSACTION_COMMAND, upiu_flags, 1468 pccb->lun, TASK_TAG); 1469 ucd_req_ptr->header.dword_1 = 1470 UPIU_HEADER_DWORD(UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0); 1471 1472 /* Total EHS length and Data segment length will be zero */ 1473 ucd_req_ptr->header.dword_2 = 0; 1474 1475 ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(pccb->datalen); 1476 1477 cdb_len = min_t(unsigned short, pccb->cmdlen, UFS_CDB_SIZE); 1478 memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE); 1479 memcpy(ucd_req_ptr->sc.cdb, pccb->cmd, cdb_len); 1480 1481 memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 1482 ufshcd_cache_flush_and_invalidate(ucd_req_ptr, sizeof(*ucd_req_ptr)); 1483 ufshcd_cache_flush_and_invalidate(hba->ucd_rsp_ptr, sizeof(*hba->ucd_rsp_ptr)); 1484 } 1485 1486 static inline void prepare_prdt_desc(struct ufshcd_sg_entry *entry, 1487 unsigned char *buf, ulong len) 1488 { 1489 entry->size = cpu_to_le32(len) | GENMASK(1, 0); 1490 entry->base_addr = cpu_to_le32(lower_32_bits((unsigned long)buf)); 1491 entry->upper_addr = cpu_to_le32(upper_32_bits((unsigned long)buf)); 1492 } 1493 1494 static void prepare_prdt_table(struct ufs_hba *hba, struct scsi_cmd *pccb) 1495 { 1496 struct utp_transfer_req_desc *req_desc = hba->utrdl; 1497 struct ufshcd_sg_entry *prd_table = hba->ucd_prdt_ptr; 1498 uintptr_t aaddr = (uintptr_t)(pccb->pdata) & ~(ARCH_DMA_MINALIGN - 1); 1499 ulong datalen = pccb->datalen; 1500 int table_length; 1501 u8 *buf; 1502 int i; 1503 1504 if (!datalen) { 1505 req_desc->prd_table_length = 0; 1506 ufshcd_cache_flush_and_invalidate(req_desc, sizeof(*req_desc)); 1507 return; 1508 } 1509 1510 if (pccb->dma_dir == DMA_TO_DEVICE) { /* Write to device */ 1511 flush_dcache_range(aaddr, ALIGN(aaddr + datalen + ARCH_DMA_MINALIGN - 1, ARCH_DMA_MINALIGN)); 1512 } 1513 1514 /* In any case, invalidate cache to avoid stale data in it. */ 1515 invalidate_dcache_range(aaddr, ALIGN(aaddr + datalen + ARCH_DMA_MINALIGN - 1, ARCH_DMA_MINALIGN)); 1516 1517 table_length = DIV_ROUND_UP(pccb->datalen, MAX_PRDT_ENTRY); 1518 buf = pccb->pdata; 1519 i = table_length; 1520 while (--i) { 1521 prepare_prdt_desc(&prd_table[table_length - i - 1], buf, 1522 MAX_PRDT_ENTRY - 1); 1523 buf += MAX_PRDT_ENTRY; 1524 datalen -= MAX_PRDT_ENTRY; 1525 } 1526 1527 prepare_prdt_desc(&prd_table[table_length - i - 1], buf, datalen - 1); 1528 1529 req_desc->prd_table_length = table_length; 1530 ufshcd_cache_flush_and_invalidate(prd_table, sizeof(*prd_table) * table_length); 1531 ufshcd_cache_flush_and_invalidate(req_desc, sizeof(*req_desc)); 1532 } 1533 1534 static int ufs_scsi_exec(struct udevice *scsi_dev, struct scsi_cmd *pccb) 1535 { 1536 struct ufs_hba *hba = dev_get_uclass_priv(scsi_dev->parent); 1537 struct utp_transfer_req_desc *req_desc = hba->utrdl; 1538 u32 upiu_flags; 1539 int ocs, result = 0, retry_count = 3; 1540 u8 scsi_status; 1541 1542 /* cmd do not set lun for ufs 2.1 */ 1543 if (hba->dev_desc->w_spec_version == 0x1002) /* verison 0x210 in big end */ 1544 pccb->cmd[1] &= 0x1F; 1545 retry: 1546 ufshcd_prepare_req_desc_hdr(req_desc, &upiu_flags, pccb->dma_dir); 1547 ufshcd_prepare_utp_scsi_cmd_upiu(hba, pccb, upiu_flags); 1548 prepare_prdt_table(hba, pccb); 1549 1550 if (ufshcd_send_command(hba, TASK_TAG) == -ETIMEDOUT && retry_count) { 1551 retry_count--; 1552 goto retry; 1553 } 1554 1555 ocs = ufshcd_get_tr_ocs(hba); 1556 switch (ocs) { 1557 case OCS_SUCCESS: 1558 result = ufshcd_get_req_rsp(hba->ucd_rsp_ptr); 1559 switch (result) { 1560 case UPIU_TRANSACTION_RESPONSE: 1561 result = ufshcd_get_rsp_upiu_result(hba->ucd_rsp_ptr); 1562 1563 scsi_status = result & MASK_SCSI_STATUS; 1564 if (pccb->cmd[0] == SCSI_TST_U_RDY && scsi_status) { 1565 /* Test ready cmd will fail with Phison UFS, break to continue */ 1566 if (retry_count) { 1567 retry_count--; 1568 goto retry; 1569 } 1570 break; 1571 } 1572 if (scsi_status) 1573 return -EINVAL; 1574 1575 break; 1576 case UPIU_TRANSACTION_REJECT_UPIU: 1577 /* TODO: handle Reject UPIU Response */ 1578 dev_err(hba->dev, 1579 "Reject UPIU not fully implemented\n"); 1580 return -EINVAL; 1581 default: 1582 dev_err(hba->dev, 1583 "Unexpected request response code = %x\n", 1584 result); 1585 return -EINVAL; 1586 } 1587 break; 1588 default: 1589 dev_err(hba->dev, "OCS error from controller = %x\n", ocs); 1590 return -EINVAL; 1591 } 1592 1593 return 0; 1594 } 1595 1596 static inline int ufshcd_read_desc(struct ufs_hba *hba, enum desc_idn desc_id, 1597 int desc_index, u8 *buf, u32 size) 1598 { 1599 return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size); 1600 } 1601 1602 static int ufshcd_read_device_desc(struct ufs_hba *hba, u8 *buf, u32 size) 1603 { 1604 return ufshcd_read_desc(hba, QUERY_DESC_IDN_DEVICE, 0, buf, size); 1605 } 1606 1607 /** 1608 * ufshcd_read_string_desc - read string descriptor 1609 * 1610 */ 1611 int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index, 1612 u8 *buf, u32 size, bool ascii) 1613 { 1614 int err = 0; 1615 1616 err = ufshcd_read_desc(hba, QUERY_DESC_IDN_STRING, desc_index, buf, 1617 size); 1618 1619 if (err) { 1620 dev_err(hba->dev, "%s: reading String Desc failed after %d retries. err = %d\n", 1621 __func__, QUERY_REQ_RETRIES, err); 1622 goto out; 1623 } 1624 1625 if (ascii) { 1626 int desc_len; 1627 int ascii_len; 1628 int i; 1629 u8 *buff_ascii; 1630 1631 desc_len = buf[0]; 1632 /* remove header and divide by 2 to move from UTF16 to UTF8 */ 1633 ascii_len = (desc_len - QUERY_DESC_HDR_SIZE) / 2 + 1; 1634 if (size < ascii_len + QUERY_DESC_HDR_SIZE) { 1635 dev_err(hba->dev, "%s: buffer allocated size is too small\n", 1636 __func__); 1637 err = -ENOMEM; 1638 goto out; 1639 } 1640 1641 buff_ascii = kmalloc(ALIGN(ascii_len, ARCH_DMA_MINALIGN), GFP_KERNEL); 1642 if (!buff_ascii) { 1643 err = -ENOMEM; 1644 goto out; 1645 } 1646 1647 /* 1648 * the descriptor contains string in UTF16 format 1649 * we need to convert to utf-8 so it can be displayed 1650 */ 1651 utf16_to_utf8(buff_ascii, 1652 (uint16_t *)&buf[QUERY_DESC_HDR_SIZE], ascii_len); 1653 1654 /* replace non-printable or non-ASCII characters with spaces */ 1655 for (i = 0; i < ascii_len; i++) 1656 ufshcd_remove_non_printable(&buff_ascii[i]); 1657 1658 memset(buf + QUERY_DESC_HDR_SIZE, 0, 1659 size - QUERY_DESC_HDR_SIZE); 1660 memcpy(buf + QUERY_DESC_HDR_SIZE, buff_ascii, ascii_len); 1661 buf[QUERY_DESC_LENGTH_OFFSET] = ascii_len + QUERY_DESC_HDR_SIZE; 1662 kfree(buff_ascii); 1663 } 1664 out: 1665 return err; 1666 } 1667 1668 static int ufs_get_device_desc(struct ufs_hba *hba, struct ufs_device_descriptor *dev_desc) 1669 { 1670 int err; 1671 size_t buff_len; 1672 1673 buff_len = sizeof(*dev_desc); 1674 if (buff_len > hba->desc_size.dev_desc) 1675 buff_len = hba->desc_size.dev_desc; 1676 1677 err = ufshcd_read_device_desc(hba, (u8 *)dev_desc, buff_len); 1678 if (err) 1679 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n", 1680 __func__, err); 1681 1682 return err; 1683 } 1684 1685 /** 1686 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device 1687 */ 1688 static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba) 1689 { 1690 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info; 1691 1692 if (hba->max_pwr_info.is_valid) 1693 return 0; 1694 1695 pwr_info->pwr_tx = FAST_MODE; 1696 pwr_info->pwr_rx = FAST_MODE; 1697 pwr_info->hs_rate = PA_HS_MODE_B; 1698 1699 /* Get the connected lane count */ 1700 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES), 1701 &pwr_info->lane_rx); 1702 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 1703 &pwr_info->lane_tx); 1704 1705 if (!pwr_info->lane_rx || !pwr_info->lane_tx) { 1706 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n", 1707 __func__, pwr_info->lane_rx, pwr_info->lane_tx); 1708 return -EINVAL; 1709 } 1710 1711 /* 1712 * First, get the maximum gears of HS speed. 1713 * If a zero value, it means there is no HSGEAR capability. 1714 * Then, get the maximum gears of PWM speed. 1715 */ 1716 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx); 1717 if (!pwr_info->gear_rx) { 1718 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), 1719 &pwr_info->gear_rx); 1720 if (!pwr_info->gear_rx) { 1721 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n", 1722 __func__, pwr_info->gear_rx); 1723 return -EINVAL; 1724 } 1725 pwr_info->pwr_rx = SLOW_MODE; 1726 } 1727 1728 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), 1729 &pwr_info->gear_tx); 1730 if (!pwr_info->gear_tx) { 1731 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), 1732 &pwr_info->gear_tx); 1733 if (!pwr_info->gear_tx) { 1734 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n", 1735 __func__, pwr_info->gear_tx); 1736 return -EINVAL; 1737 } 1738 pwr_info->pwr_tx = SLOW_MODE; 1739 } 1740 1741 hba->max_pwr_info.is_valid = true; 1742 return 0; 1743 } 1744 1745 static int ufshcd_change_power_mode(struct ufs_hba *hba, 1746 struct ufs_pa_layer_attr *pwr_mode) 1747 { 1748 int ret; 1749 1750 /* if already configured to the requested pwr_mode */ 1751 if (pwr_mode->gear_rx == hba->pwr_info.gear_rx && 1752 pwr_mode->gear_tx == hba->pwr_info.gear_tx && 1753 pwr_mode->lane_rx == hba->pwr_info.lane_rx && 1754 pwr_mode->lane_tx == hba->pwr_info.lane_tx && 1755 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx && 1756 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx && 1757 pwr_mode->hs_rate == hba->pwr_info.hs_rate) { 1758 dev_dbg(hba->dev, "%s: power already configured\n", __func__); 1759 return 0; 1760 } 1761 1762 /* 1763 * Configure attributes for power mode change with below. 1764 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION, 1765 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION, 1766 * - PA_HSSERIES 1767 */ 1768 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx); 1769 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES), 1770 pwr_mode->lane_rx); 1771 if (pwr_mode->pwr_rx == FASTAUTO_MODE || pwr_mode->pwr_rx == FAST_MODE) 1772 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE); 1773 else 1774 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE); 1775 1776 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx); 1777 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES), 1778 pwr_mode->lane_tx); 1779 if (pwr_mode->pwr_tx == FASTAUTO_MODE || pwr_mode->pwr_tx == FAST_MODE) 1780 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE); 1781 else 1782 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE); 1783 1784 if (pwr_mode->pwr_rx == FASTAUTO_MODE || 1785 pwr_mode->pwr_tx == FASTAUTO_MODE || 1786 pwr_mode->pwr_rx == FAST_MODE || 1787 pwr_mode->pwr_tx == FAST_MODE) 1788 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES), 1789 pwr_mode->hs_rate); 1790 1791 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4 | 1792 pwr_mode->pwr_tx); 1793 1794 if (ret) { 1795 dev_err(hba->dev, 1796 "%s: power mode change failed %d\n", __func__, ret); 1797 1798 return ret; 1799 } 1800 1801 /* Copy new Power Mode to power info */ 1802 memcpy(&hba->pwr_info, pwr_mode, sizeof(struct ufs_pa_layer_attr)); 1803 1804 return ret; 1805 } 1806 1807 /** 1808 * ufshcd_verify_dev_init() - Verify device initialization 1809 * 1810 */ 1811 static int ufshcd_verify_dev_init(struct ufs_hba *hba) 1812 { 1813 int retries; 1814 int err; 1815 1816 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) { 1817 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP, 1818 NOP_OUT_TIMEOUT); 1819 if (!err || err == -ETIMEDOUT) 1820 break; 1821 1822 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err); 1823 } 1824 1825 if (err) 1826 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err); 1827 1828 return err; 1829 } 1830 1831 /** 1832 * ufshcd_complete_dev_init() - checks device readiness 1833 */ 1834 static int ufshcd_complete_dev_init(struct ufs_hba *hba) 1835 { 1836 unsigned long start = 0; 1837 int i; 1838 int err; 1839 bool flag_res = 1; 1840 1841 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG, 1842 QUERY_FLAG_IDN_FDEVICEINIT, NULL); 1843 if (err) { 1844 dev_err(hba->dev, 1845 "%s setting fDeviceInit flag failed with error %d\n", 1846 __func__, err); 1847 goto out; 1848 } 1849 1850 /* poll for max. 1500ms for fDeviceInit flag to clear */ 1851 start = get_timer(0); 1852 for (i = 0; i < 3000 && !err && flag_res; i++) { 1853 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG, 1854 QUERY_FLAG_IDN_FDEVICEINIT, 1855 &flag_res); 1856 if (get_timer(start) > FDEVICEINIT_COMPL_TIMEOUT) 1857 break; 1858 udelay(500); 1859 } 1860 1861 if (err) 1862 dev_err(hba->dev, 1863 "%s reading fDeviceInit flag failed with error %d\n", 1864 __func__, err); 1865 else if (flag_res) 1866 dev_err(hba->dev, 1867 "%s fDeviceInit was not cleared by the device\n", 1868 __func__); 1869 1870 out: 1871 return err; 1872 } 1873 1874 static void ufshcd_def_desc_sizes(struct ufs_hba *hba) 1875 { 1876 hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE; 1877 hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE; 1878 hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE; 1879 hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE; 1880 hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE; 1881 hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE; 1882 hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE; 1883 } 1884 1885 int _ufs_start(struct ufs_hba *hba) 1886 { 1887 int ret; 1888 1889 ret = ufshcd_link_startup(hba); 1890 if (ret) 1891 return ret; 1892 1893 ret = ufshcd_verify_dev_init(hba); 1894 if (ret) 1895 return ret; 1896 1897 ret = ufshcd_complete_dev_init(hba); 1898 if (ret) 1899 return ret; 1900 1901 /* Init check for device descriptor sizes */ 1902 ufshcd_init_desc_sizes(hba); 1903 1904 ret = ufs_get_device_desc(hba, hba->dev_desc); 1905 if (ret) { 1906 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n", 1907 __func__, ret); 1908 1909 return ret; 1910 } 1911 1912 return ret; 1913 } 1914 1915 int ufs_start(struct ufs_hba *hba) 1916 { 1917 int ret; 1918 1919 ret = _ufs_start(hba); 1920 if (ret) 1921 return ret; 1922 1923 #if defined(CONFIG_SUPPORT_USBPLUG) 1924 ret = ufs_create_partition_inventory(hba); 1925 if (ret) { 1926 dev_err(hba->dev, "%s: Failed to creat partition. err = %d\n", __func__, ret); 1927 return ret; 1928 } 1929 #endif 1930 if (ufshcd_get_max_pwr_mode(hba)) { 1931 dev_err(hba->dev, 1932 "%s: Failed getting max supported power mode\n", 1933 __func__); 1934 } else { 1935 ret = ufshcd_change_power_mode(hba, &hba->max_pwr_info.info); 1936 if (ret) { 1937 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n", 1938 __func__, ret); 1939 1940 return ret; 1941 } 1942 1943 printf("Device at %s up at:", hba->dev->name); 1944 ufshcd_print_pwr_info(hba); 1945 } 1946 1947 return 0; 1948 } 1949 1950 int ufshcd_probe(struct udevice *ufs_dev, struct ufs_hba_ops *hba_ops) 1951 { 1952 struct ufs_hba *hba = dev_get_uclass_priv(ufs_dev); 1953 struct scsi_platdata *scsi_plat; 1954 struct udevice *scsi_dev; 1955 int err; 1956 1957 device_find_first_child(ufs_dev, &scsi_dev); 1958 if (!scsi_dev) 1959 return -ENODEV; 1960 1961 scsi_plat = dev_get_uclass_platdata(scsi_dev); 1962 scsi_plat->max_id = UFSHCD_MAX_ID; 1963 scsi_plat->max_lun = UFS_MAX_LUNS; 1964 //scsi_plat->max_bytes_per_req = UFS_MAX_BYTES; 1965 1966 hba->dev = ufs_dev; 1967 hba->ops = hba_ops; 1968 hba->mmio_base = (void *)dev_read_addr(ufs_dev); 1969 1970 /* Set descriptor lengths to specification defaults */ 1971 ufshcd_def_desc_sizes(hba); 1972 1973 ufshcd_ops_init(hba); 1974 1975 /* Read capabilties registers */ 1976 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES); 1977 1978 /* Get UFS version supported by the controller */ 1979 hba->version = ufshcd_get_ufs_version(hba); 1980 if (hba->version != UFSHCI_VERSION_10 && 1981 hba->version != UFSHCI_VERSION_11 && 1982 hba->version != UFSHCI_VERSION_20 && 1983 hba->version != UFSHCI_VERSION_21) 1984 dev_err(hba->dev, "invalid UFS version 0x%x\n", 1985 hba->version); 1986 1987 /* Get Interrupt bit mask per version */ 1988 hba->intr_mask = ufshcd_get_intr_mask(hba); 1989 1990 /* Allocate memory for host memory space */ 1991 err = ufshcd_memory_alloc(hba); 1992 if (err) { 1993 dev_err(hba->dev, "Memory allocation failed\n"); 1994 return err; 1995 } 1996 1997 /* Configure Local data structures */ 1998 ufshcd_host_memory_configure(hba); 1999 2000 /* 2001 * In order to avoid any spurious interrupt immediately after 2002 * registering UFS controller interrupt handler, clear any pending UFS 2003 * interrupt status and disable all the UFS interrupts. 2004 */ 2005 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS), 2006 REG_INTERRUPT_STATUS); 2007 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE); 2008 2009 err = ufshcd_hba_enable(hba); 2010 if (err) { 2011 dev_err(hba->dev, "Host controller enable failed\n"); 2012 return err; 2013 } 2014 2015 err = ufs_start(hba); 2016 if (err) 2017 return err; 2018 2019 return 0; 2020 } 2021 2022 int ufs_scsi_bind(struct udevice *ufs_dev, struct udevice **scsi_devp) 2023 { 2024 int ret = device_bind_driver(ufs_dev, "ufs_scsi", "ufs_scsi", 2025 scsi_devp); 2026 2027 return ret; 2028 } 2029 2030 static struct scsi_ops ufs_ops = { 2031 .exec = ufs_scsi_exec, 2032 }; 2033 2034 int ufs_probe_dev(int index) 2035 { 2036 struct udevice *dev; 2037 2038 return uclass_get_device(UCLASS_UFS, index, &dev); 2039 } 2040 2041 int ufs_probe(void) 2042 { 2043 struct udevice *dev; 2044 int ret, i; 2045 2046 for (i = 0;; i++) { 2047 ret = uclass_get_device(UCLASS_UFS, i, &dev); 2048 if (ret == -ENODEV) 2049 break; 2050 } 2051 2052 return 0; 2053 } 2054 2055 U_BOOT_DRIVER(ufs_scsi) = { 2056 .id = UCLASS_SCSI, 2057 .name = "ufs_scsi", 2058 .ops = &ufs_ops, 2059 }; 2060