1 // SPDX-License-Identifier: GPL-2.0+ 2 /** 3 * ufs.c - Universal Flash Subsystem (UFS) driver 4 * 5 * Taken from Linux Kernel v5.2 (drivers/scsi/ufs/ufshcd.c) and ported 6 * to u-boot. 7 * 8 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com 9 */ 10 #include <charset.h> 11 #include <common.h> 12 #include <dm.h> 13 #include <log.h> 14 #include <dm/lists.h> 15 #include <dm/device-internal.h> 16 #include <malloc.h> 17 #include <hexdump.h> 18 #include <scsi.h> 19 #include <asm/io.h> 20 #include <asm/dma-mapping.h> 21 #include <linux/bitops.h> 22 #include <linux/delay.h> 23 24 #if defined(CONFIG_SUPPORT_USBPLUG) 25 #include "ufs-rockchip-usbplug.h" 26 #endif 27 #include "ufs.h" 28 29 #define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\ 30 UTP_TASK_REQ_COMPL |\ 31 UFSHCD_ERROR_MASK) 32 /* maximum number of link-startup retries */ 33 #define DME_LINKSTARTUP_RETRIES 3 34 35 /* maximum number of retries for a general UIC command */ 36 #define UFS_UIC_COMMAND_RETRIES 3 37 38 /* Query request retries */ 39 #define QUERY_REQ_RETRIES 3 40 /* Query request timeout */ 41 #define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */ 42 43 /* maximum timeout in ms for a general UIC command */ 44 #define UFS_UIC_CMD_TIMEOUT 1000 45 /* NOP OUT retries waiting for NOP IN response */ 46 #define NOP_OUT_RETRIES 10 47 /* Timeout after 30 msecs if NOP OUT hangs without response */ 48 #define NOP_OUT_TIMEOUT 30 /* msecs */ 49 50 /* Only use one Task Tag for all requests */ 51 #define TASK_TAG 0 52 53 /* Expose the flag value from utp_upiu_query.value */ 54 #define MASK_QUERY_UPIU_FLAG_LOC 0xFF 55 56 #define MAX_PRDT_ENTRY 262144 57 58 /* maximum bytes per request */ 59 #define UFS_MAX_BYTES (128 * 256 * 1024) 60 61 static inline bool ufshcd_is_hba_active(struct ufs_hba *hba); 62 static inline void ufshcd_hba_stop(struct ufs_hba *hba); 63 static int ufshcd_hba_enable(struct ufs_hba *hba); 64 65 /* 66 * ufshcd_wait_for_register - wait for register value to change 67 */ 68 static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask, 69 u32 val, unsigned long timeout_ms) 70 { 71 int err = 0; 72 unsigned long start = get_timer(0); 73 74 /* ignore bits that we don't intend to wait on */ 75 val = val & mask; 76 77 while ((ufshcd_readl(hba, reg) & mask) != val) { 78 if (get_timer(start) > timeout_ms) { 79 if ((ufshcd_readl(hba, reg) & mask) != val) 80 err = -ETIMEDOUT; 81 break; 82 } 83 } 84 85 return err; 86 } 87 88 /** 89 * ufshcd_init_pwr_info - setting the POR (power on reset) 90 * values in hba power info 91 */ 92 static void ufshcd_init_pwr_info(struct ufs_hba *hba) 93 { 94 hba->pwr_info.gear_rx = UFS_PWM_G1; 95 hba->pwr_info.gear_tx = UFS_PWM_G1; 96 hba->pwr_info.lane_rx = 1; 97 hba->pwr_info.lane_tx = 1; 98 hba->pwr_info.pwr_rx = SLOWAUTO_MODE; 99 hba->pwr_info.pwr_tx = SLOWAUTO_MODE; 100 hba->pwr_info.hs_rate = 0; 101 } 102 103 /** 104 * ufshcd_print_pwr_info - print power params as saved in hba 105 * power info 106 */ 107 static void ufshcd_print_pwr_info(struct ufs_hba *hba) 108 { 109 static const char * const names[] = { 110 "INVALID MODE", 111 "FAST MODE", 112 "SLOW_MODE", 113 "INVALID MODE", 114 "FASTAUTO_MODE", 115 "SLOWAUTO_MODE", 116 "INVALID MODE", 117 }; 118 119 dev_err(hba->dev, "[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n", 120 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx, 121 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx, 122 names[hba->pwr_info.pwr_rx], 123 names[hba->pwr_info.pwr_tx], 124 hba->pwr_info.hs_rate); 125 } 126 127 /** 128 * ufshcd_ready_for_uic_cmd - Check if controller is ready 129 * to accept UIC commands 130 */ 131 static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba) 132 { 133 if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY) 134 return true; 135 else 136 return false; 137 } 138 139 /** 140 * ufshcd_get_uic_cmd_result - Get the UIC command result 141 */ 142 static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba) 143 { 144 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) & 145 MASK_UIC_COMMAND_RESULT; 146 } 147 148 /** 149 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command 150 */ 151 static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba) 152 { 153 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3); 154 } 155 156 /** 157 * ufshcd_is_device_present - Check if any device connected to 158 * the host controller 159 */ 160 static inline bool ufshcd_is_device_present(struct ufs_hba *hba) 161 { 162 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & 163 DEVICE_PRESENT) ? true : false; 164 } 165 166 /** 167 * ufshcd_send_uic_cmd - UFS Interconnect layer command API 168 * 169 */ 170 static int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 171 { 172 unsigned long start = 0; 173 u32 intr_status; 174 u32 enabled_intr_status; 175 176 if (!ufshcd_ready_for_uic_cmd(hba)) { 177 dev_err(hba->dev, 178 "Controller not ready to accept UIC commands\n"); 179 return -EIO; 180 } 181 182 debug("sending uic command:%d\n", uic_cmd->command); 183 184 /* Write Args */ 185 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1); 186 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2); 187 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3); 188 189 /* Write UIC Cmd */ 190 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK, 191 REG_UIC_COMMAND); 192 193 start = get_timer(0); 194 do { 195 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 196 enabled_intr_status = intr_status & hba->intr_mask; 197 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS); 198 199 if (get_timer(start) > UFS_UIC_CMD_TIMEOUT) { 200 dev_err(hba->dev, 201 "Timedout waiting for UIC response\n"); 202 203 return -ETIMEDOUT; 204 } 205 206 if (enabled_intr_status & UFSHCD_ERROR_MASK) { 207 dev_err(hba->dev, "Error in status:%08x\n", 208 enabled_intr_status); 209 210 return -1; 211 } 212 } while (!(enabled_intr_status & UFSHCD_UIC_MASK)); 213 214 uic_cmd->argument2 = ufshcd_get_uic_cmd_result(hba); 215 uic_cmd->argument3 = ufshcd_get_dme_attr_val(hba); 216 217 debug("Sent successfully\n"); 218 219 return 0; 220 } 221 222 /** 223 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET 224 * 225 */ 226 int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, u8 attr_set, 227 u32 mib_val, u8 peer) 228 { 229 struct uic_command uic_cmd = {0}; 230 static const char *const action[] = { 231 "dme-set", 232 "dme-peer-set" 233 }; 234 const char *set = action[!!peer]; 235 int ret; 236 int retries = UFS_UIC_COMMAND_RETRIES; 237 238 uic_cmd.command = peer ? 239 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET; 240 uic_cmd.argument1 = attr_sel; 241 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set); 242 uic_cmd.argument3 = mib_val; 243 244 do { 245 /* for peer attributes we retry upon failure */ 246 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 247 if (ret) 248 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n", 249 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret); 250 } while (ret && peer && --retries); 251 252 if (ret) 253 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n", 254 set, UIC_GET_ATTR_ID(attr_sel), mib_val, 255 UFS_UIC_COMMAND_RETRIES - retries); 256 257 return ret; 258 } 259 260 /** 261 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET 262 * 263 */ 264 int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, 265 u32 *mib_val, u8 peer) 266 { 267 struct uic_command uic_cmd = {0}; 268 static const char *const action[] = { 269 "dme-get", 270 "dme-peer-get" 271 }; 272 const char *get = action[!!peer]; 273 int ret; 274 int retries = UFS_UIC_COMMAND_RETRIES; 275 276 uic_cmd.command = peer ? 277 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET; 278 uic_cmd.argument1 = attr_sel; 279 280 do { 281 /* for peer attributes we retry upon failure */ 282 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 283 if (ret) 284 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n", 285 get, UIC_GET_ATTR_ID(attr_sel), ret); 286 } while (ret && peer && --retries); 287 288 if (ret) 289 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n", 290 get, UIC_GET_ATTR_ID(attr_sel), 291 UFS_UIC_COMMAND_RETRIES - retries); 292 293 if (mib_val && !ret) 294 *mib_val = uic_cmd.argument3; 295 296 return ret; 297 } 298 299 static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer) 300 { 301 u32 tx_lanes, i, err = 0; 302 303 if (!peer) 304 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 305 &tx_lanes); 306 else 307 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 308 &tx_lanes); 309 for (i = 0; i < tx_lanes; i++) { 310 if (!peer) 311 err = ufshcd_dme_set(hba, 312 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, 313 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), 314 0); 315 else 316 err = ufshcd_dme_peer_set(hba, 317 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, 318 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), 319 0); 320 if (err) { 321 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d\n", 322 __func__, peer, i, err); 323 break; 324 } 325 } 326 327 return err; 328 } 329 330 static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba) 331 { 332 return ufshcd_disable_tx_lcc(hba, true); 333 } 334 335 /** 336 * ufshcd_dme_link_startup - Notify Unipro to perform link startup 337 * 338 */ 339 static int ufshcd_dme_link_startup(struct ufs_hba *hba) 340 { 341 struct uic_command uic_cmd = {0}; 342 int ret; 343 344 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP; 345 346 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 347 if (ret) 348 dev_dbg(hba->dev, 349 "dme-link-startup: error code %d\n", ret); 350 return ret; 351 } 352 353 int ufshcd_dme_enable(struct ufs_hba *hba) 354 { 355 struct uic_command uic_cmd = {0}; 356 int ret; 357 358 uic_cmd.command = UIC_CMD_DME_ENABLE; 359 360 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 361 if (ret) 362 dev_err(hba->dev, 363 "dme-enable: error code %d\n", ret); 364 return ret; 365 } 366 367 int ufshcd_dme_reset(struct ufs_hba *hba) 368 { 369 struct uic_command uic_cmd = {0}; 370 int ret; 371 372 uic_cmd.command = UIC_CMD_DME_RESET; 373 374 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 375 if (ret) 376 dev_err(hba->dev, 377 "dme-reset: error code %d\n", ret); 378 return ret; 379 } 380 381 /** 382 * ufshcd_disable_intr_aggr - Disables interrupt aggregation. 383 * 384 */ 385 static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba) 386 { 387 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 388 } 389 390 /** 391 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY 392 */ 393 static inline int ufshcd_get_lists_status(u32 reg) 394 { 395 return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY); 396 } 397 398 /** 399 * ufshcd_enable_run_stop_reg - Enable run-stop registers, 400 * When run-stop registers are set to 1, it indicates the 401 * host controller that it can process the requests 402 */ 403 static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba) 404 { 405 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT, 406 REG_UTP_TASK_REQ_LIST_RUN_STOP); 407 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT, 408 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP); 409 } 410 411 /** 412 * ufshcd_enable_intr - enable interrupts 413 */ 414 static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs) 415 { 416 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 417 u32 rw; 418 419 if (hba->version == UFSHCI_VERSION_10) { 420 rw = set & INTERRUPT_MASK_RW_VER_10; 421 set = rw | ((set ^ intrs) & intrs); 422 } else { 423 set |= intrs; 424 } 425 426 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); 427 428 hba->intr_mask = set; 429 } 430 431 /** 432 * ufshcd_make_hba_operational - Make UFS controller operational 433 * 434 * To bring UFS host controller to operational state, 435 * 1. Enable required interrupts 436 * 2. Configure interrupt aggregation 437 * 3. Program UTRL and UTMRL base address 438 * 4. Configure run-stop-registers 439 * 440 */ 441 static int ufshcd_make_hba_operational(struct ufs_hba *hba) 442 { 443 int err = 0; 444 u32 reg; 445 446 /* Enable required interrupts */ 447 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS); 448 449 /* Disable interrupt aggregation */ 450 ufshcd_disable_intr_aggr(hba); 451 452 /* Configure UTRL and UTMRL base address registers */ 453 ufshcd_writel(hba, lower_32_bits((dma_addr_t)hba->utrdl), 454 REG_UTP_TRANSFER_REQ_LIST_BASE_L); 455 ufshcd_writel(hba, upper_32_bits((dma_addr_t)hba->utrdl), 456 REG_UTP_TRANSFER_REQ_LIST_BASE_H); 457 ufshcd_writel(hba, lower_32_bits((dma_addr_t)hba->utmrdl), 458 REG_UTP_TASK_REQ_LIST_BASE_L); 459 ufshcd_writel(hba, upper_32_bits((dma_addr_t)hba->utmrdl), 460 REG_UTP_TASK_REQ_LIST_BASE_H); 461 462 /* 463 * UCRDY, UTMRLDY and UTRLRDY bits must be 1 464 */ 465 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS); 466 if (!(ufshcd_get_lists_status(reg))) { 467 ufshcd_enable_run_stop_reg(hba); 468 } else { 469 dev_err(hba->dev, 470 "Host controller not ready to process requests\n"); 471 err = -EIO; 472 goto out; 473 } 474 475 out: 476 return err; 477 } 478 479 /** 480 * ufshcd_link_startup - Initialize unipro link startup 481 */ 482 static int ufshcd_link_startup(struct ufs_hba *hba) 483 { 484 int ret; 485 int retries = DME_LINKSTARTUP_RETRIES; 486 bool link_startup_again = true; 487 488 link_startup: 489 do { 490 ufshcd_ops_link_startup_notify(hba, PRE_CHANGE); 491 492 ret = ufshcd_dme_link_startup(hba); 493 494 /* check if device is detected by inter-connect layer */ 495 if (!ret && !ufshcd_is_device_present(hba)) { 496 dev_err(hba->dev, "%s: Device not present\n", __func__); 497 ret = -ENXIO; 498 goto out; 499 } 500 501 /* 502 * DME link lost indication is only received when link is up, 503 * but we can't be sure if the link is up until link startup 504 * succeeds. So reset the local Uni-Pro and try again. 505 */ 506 if (ret && ufshcd_hba_enable(hba)) 507 goto out; 508 } while (ret && retries--); 509 510 if (ret) 511 /* failed to get the link up... retire */ 512 goto out; 513 514 if (link_startup_again) { 515 link_startup_again = false; 516 retries = DME_LINKSTARTUP_RETRIES; 517 goto link_startup; 518 } 519 520 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */ 521 ufshcd_init_pwr_info(hba); 522 523 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) { 524 ret = ufshcd_disable_device_tx_lcc(hba); 525 if (ret) 526 goto out; 527 } 528 529 /* Include any host controller configuration via UIC commands */ 530 ret = ufshcd_ops_link_startup_notify(hba, POST_CHANGE); 531 if (ret) 532 goto out; 533 534 ret = ufshcd_make_hba_operational(hba); 535 out: 536 if (ret) 537 dev_err(hba->dev, "link startup failed %d\n", ret); 538 539 return ret; 540 } 541 542 /** 543 * ufshcd_hba_stop - Send controller to reset state 544 */ 545 static inline void ufshcd_hba_stop(struct ufs_hba *hba) 546 { 547 int err; 548 549 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE); 550 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE, 551 CONTROLLER_ENABLE, CONTROLLER_DISABLE, 552 10); 553 if (err) 554 dev_err(hba->dev, "%s: Controller disable failed\n", __func__); 555 } 556 557 /** 558 * ufshcd_is_hba_active - Get controller state 559 */ 560 static inline bool ufshcd_is_hba_active(struct ufs_hba *hba) 561 { 562 return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE) 563 ? false : true; 564 } 565 566 /** 567 * ufshcd_hba_start - Start controller initialization sequence 568 */ 569 static inline void ufshcd_hba_start(struct ufs_hba *hba) 570 { 571 ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE); 572 } 573 574 /** 575 * ufshcd_hba_enable - initialize the controller 576 */ 577 static int ufshcd_hba_enable(struct ufs_hba *hba) 578 { 579 int retry; 580 581 if (!ufshcd_is_hba_active(hba)) 582 /* change controller state to "reset state" */ 583 ufshcd_hba_stop(hba); 584 585 ufshcd_ops_hce_enable_notify(hba, PRE_CHANGE); 586 587 /* start controller initialization sequence */ 588 ufshcd_hba_start(hba); 589 590 /* 591 * To initialize a UFS host controller HCE bit must be set to 1. 592 * During initialization the HCE bit value changes from 1->0->1. 593 * When the host controller completes initialization sequence 594 * it sets the value of HCE bit to 1. The same HCE bit is read back 595 * to check if the controller has completed initialization sequence. 596 * So without this delay the value HCE = 1, set in the previous 597 * instruction might be read back. 598 * This delay can be changed based on the controller. 599 */ 600 mdelay(1); 601 602 /* wait for the host controller to complete initialization */ 603 retry = 10; 604 while (ufshcd_is_hba_active(hba)) { 605 if (retry) { 606 retry--; 607 } else { 608 dev_err(hba->dev, "Controller enable failed\n"); 609 return -EIO; 610 } 611 mdelay(5); 612 } 613 614 /* enable UIC related interrupts */ 615 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK); 616 617 if (ufshcd_ops_hce_enable_notify(hba, POST_CHANGE)) 618 return -EIO; 619 620 return 0; 621 } 622 623 /** 624 * ufshcd_host_memory_configure - configure local reference block with 625 * memory offsets 626 */ 627 static void ufshcd_host_memory_configure(struct ufs_hba *hba) 628 { 629 struct utp_transfer_req_desc *utrdlp; 630 dma_addr_t cmd_desc_dma_addr; 631 u16 response_offset; 632 u16 prdt_offset; 633 634 utrdlp = hba->utrdl; 635 cmd_desc_dma_addr = (dma_addr_t)hba->ucdl; 636 637 utrdlp->command_desc_base_addr_lo = 638 cpu_to_le32(lower_32_bits(cmd_desc_dma_addr)); 639 utrdlp->command_desc_base_addr_hi = 640 cpu_to_le32(upper_32_bits(cmd_desc_dma_addr)); 641 642 response_offset = offsetof(struct utp_transfer_cmd_desc, response_upiu); 643 prdt_offset = offsetof(struct utp_transfer_cmd_desc, prd_table); 644 645 utrdlp->response_upiu_offset = cpu_to_le16(response_offset >> 2); 646 utrdlp->prd_table_offset = cpu_to_le16(prdt_offset >> 2); 647 utrdlp->response_upiu_length = cpu_to_le16(ALIGNED_UPIU_SIZE >> 2); 648 649 hba->ucd_req_ptr = (struct utp_upiu_req *)hba->ucdl; 650 hba->ucd_rsp_ptr = 651 (struct utp_upiu_rsp *)&hba->ucdl->response_upiu; 652 hba->ucd_prdt_ptr = 653 (struct ufshcd_sg_entry *)&hba->ucdl->prd_table; 654 } 655 656 /** 657 * ufshcd_memory_alloc - allocate memory for host memory space data structures 658 */ 659 static int ufshcd_memory_alloc(struct ufs_hba *hba) 660 { 661 /* Allocate one Transfer Request Descriptor 662 * Should be aligned to 1k boundary. 663 */ 664 hba->utrdl = memalign(1024, sizeof(struct utp_transfer_req_desc)); 665 if (!hba->utrdl) { 666 dev_err(hba->dev, "Transfer Descriptor memory allocation failed\n"); 667 return -ENOMEM; 668 } 669 670 /* Allocate one Command Descriptor 671 * Should be aligned to 1k boundary. 672 */ 673 hba->ucdl = memalign(1024, sizeof(struct utp_transfer_cmd_desc)); 674 if (!hba->ucdl) { 675 dev_err(hba->dev, "Command descriptor memory allocation failed\n"); 676 return -ENOMEM; 677 } 678 679 hba->dev_desc = memalign(ARCH_DMA_MINALIGN, sizeof(struct ufs_device_descriptor)); 680 if (!hba->dev_desc) { 681 dev_err(hba->dev, "memory allocation failed\n"); 682 return -ENOMEM; 683 } 684 685 #if defined(CONFIG_SUPPORT_USBPLUG) 686 hba->rc_desc = memalign(ARCH_DMA_MINALIGN, sizeof(struct ufs_configuration_descriptor)); 687 hba->wc_desc = memalign(ARCH_DMA_MINALIGN, sizeof(struct ufs_configuration_descriptor)); 688 hba->geo_desc = memalign(ARCH_DMA_MINALIGN, sizeof(struct ufs_geometry_descriptor)); 689 if (!hba->rc_desc || !hba->wc_desc || !hba->geo_desc) { 690 dev_err(hba->dev, "memory allocation failed\n"); 691 return -ENOMEM; 692 } 693 #endif 694 return 0; 695 } 696 697 /** 698 * ufshcd_get_intr_mask - Get the interrupt bit mask 699 */ 700 static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba) 701 { 702 u32 intr_mask = 0; 703 704 switch (hba->version) { 705 case UFSHCI_VERSION_10: 706 intr_mask = INTERRUPT_MASK_ALL_VER_10; 707 break; 708 case UFSHCI_VERSION_11: 709 case UFSHCI_VERSION_20: 710 intr_mask = INTERRUPT_MASK_ALL_VER_11; 711 break; 712 case UFSHCI_VERSION_21: 713 default: 714 intr_mask = INTERRUPT_MASK_ALL_VER_21; 715 break; 716 } 717 718 return intr_mask; 719 } 720 721 /** 722 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA 723 */ 724 static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba) 725 { 726 return ufshcd_readl(hba, REG_UFS_VERSION); 727 } 728 729 /** 730 * ufshcd_get_upmcrs - Get the power mode change request status 731 */ 732 static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba) 733 { 734 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7; 735 } 736 737 /** 738 * ufshcd_cache_flush_and_invalidate - Flush and invalidate cache 739 * 740 * Flush and invalidate cache in aligned address..address+size range. 741 * The invalidation is in place to avoid stale data in cache. 742 */ 743 static void ufshcd_cache_flush_and_invalidate(void *addr, unsigned long size) 744 { 745 uintptr_t aaddr = (uintptr_t)addr & ~(ARCH_DMA_MINALIGN - 1); 746 unsigned long asize = ALIGN(size, ARCH_DMA_MINALIGN); 747 748 flush_dcache_range(aaddr, aaddr + asize); 749 invalidate_dcache_range(aaddr, aaddr + asize); 750 } 751 752 /** 753 * ufshcd_prepare_req_desc_hdr() - Fills the requests header 754 * descriptor according to request 755 */ 756 static void ufshcd_prepare_req_desc_hdr(struct utp_transfer_req_desc *req_desc, 757 u32 *upiu_flags, 758 enum dma_data_direction cmd_dir) 759 { 760 u32 data_direction; 761 u32 dword_0; 762 763 if (cmd_dir == DMA_FROM_DEVICE) { 764 data_direction = UTP_DEVICE_TO_HOST; 765 *upiu_flags = UPIU_CMD_FLAGS_READ; 766 } else if (cmd_dir == DMA_TO_DEVICE) { 767 data_direction = UTP_HOST_TO_DEVICE; 768 *upiu_flags = UPIU_CMD_FLAGS_WRITE; 769 } else { 770 data_direction = UTP_NO_DATA_TRANSFER; 771 *upiu_flags = UPIU_CMD_FLAGS_NONE; 772 } 773 774 dword_0 = data_direction | (0x1 << UPIU_COMMAND_TYPE_OFFSET); 775 776 /* Enable Interrupt for command */ 777 dword_0 |= UTP_REQ_DESC_INT_CMD; 778 779 /* Transfer request descriptor header fields */ 780 req_desc->header.dword_0 = cpu_to_le32(dword_0); 781 /* dword_1 is reserved, hence it is set to 0 */ 782 req_desc->header.dword_1 = 0; 783 /* 784 * assigning invalid value for command status. Controller 785 * updates OCS on command completion, with the command 786 * status 787 */ 788 req_desc->header.dword_2 = 789 cpu_to_le32(OCS_INVALID_COMMAND_STATUS); 790 /* dword_3 is reserved, hence it is set to 0 */ 791 req_desc->header.dword_3 = 0; 792 793 req_desc->prd_table_length = 0; 794 795 ufshcd_cache_flush_and_invalidate(req_desc, sizeof(*req_desc)); 796 } 797 798 static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba, 799 u32 upiu_flags) 800 { 801 struct utp_upiu_req *ucd_req_ptr = hba->ucd_req_ptr; 802 struct ufs_query *query = &hba->dev_cmd.query; 803 u16 len = be16_to_cpu(query->request.upiu_req.length); 804 805 /* Query request header */ 806 ucd_req_ptr->header.dword_0 = 807 UPIU_HEADER_DWORD(UPIU_TRANSACTION_QUERY_REQ, 808 upiu_flags, 0, TASK_TAG); 809 ucd_req_ptr->header.dword_1 = 810 UPIU_HEADER_DWORD(0, query->request.query_func, 811 0, 0); 812 813 /* Data segment length only need for WRITE_DESC */ 814 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC) 815 ucd_req_ptr->header.dword_2 = 816 UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len); 817 else 818 ucd_req_ptr->header.dword_2 = 0; 819 820 /* Copy the Query Request buffer as is */ 821 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req, QUERY_OSF_SIZE); 822 823 /* Copy the Descriptor */ 824 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC) { 825 memcpy(ucd_req_ptr + 1, query->descriptor, len); 826 ufshcd_cache_flush_and_invalidate(ucd_req_ptr, 827 ALIGN(sizeof(*ucd_req_ptr) + len, ARCH_DMA_MINALIGN)); 828 } else { 829 ufshcd_cache_flush_and_invalidate(ucd_req_ptr, sizeof(*ucd_req_ptr)); 830 } 831 832 memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 833 ufshcd_cache_flush_and_invalidate(hba->ucd_rsp_ptr, sizeof(*hba->ucd_rsp_ptr)); 834 } 835 836 static inline void ufshcd_prepare_utp_nop_upiu(struct ufs_hba *hba) 837 { 838 struct utp_upiu_req *ucd_req_ptr = hba->ucd_req_ptr; 839 840 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req)); 841 842 /* command descriptor fields */ 843 ucd_req_ptr->header.dword_0 = 844 UPIU_HEADER_DWORD(UPIU_TRANSACTION_NOP_OUT, 0, 0, TASK_TAG); 845 /* clear rest of the fields of basic header */ 846 ucd_req_ptr->header.dword_1 = 0; 847 ucd_req_ptr->header.dword_2 = 0; 848 849 memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 850 851 ufshcd_cache_flush_and_invalidate(ucd_req_ptr, sizeof(*ucd_req_ptr)); 852 ufshcd_cache_flush_and_invalidate(hba->ucd_rsp_ptr, sizeof(*hba->ucd_rsp_ptr)); 853 } 854 855 /** 856 * ufshcd_comp_devman_upiu - UFS Protocol Information Unit(UPIU) 857 * for Device Management Purposes 858 */ 859 static int ufshcd_comp_devman_upiu(struct ufs_hba *hba, 860 enum dev_cmd_type cmd_type) 861 { 862 u32 upiu_flags; 863 int ret = 0; 864 struct utp_transfer_req_desc *req_desc = hba->utrdl; 865 866 hba->dev_cmd.type = cmd_type; 867 868 ufshcd_prepare_req_desc_hdr(req_desc, &upiu_flags, DMA_NONE); 869 switch (cmd_type) { 870 case DEV_CMD_TYPE_QUERY: 871 ufshcd_prepare_utp_query_req_upiu(hba, upiu_flags); 872 break; 873 case DEV_CMD_TYPE_NOP: 874 ufshcd_prepare_utp_nop_upiu(hba); 875 break; 876 default: 877 ret = -EINVAL; 878 } 879 880 return ret; 881 } 882 883 static int ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag) 884 { 885 unsigned long start; 886 u32 intr_status; 887 u32 enabled_intr_status; 888 889 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL); 890 891 start = get_timer(0); 892 do { 893 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 894 enabled_intr_status = intr_status & hba->intr_mask; 895 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS); 896 897 if (get_timer(start) > QUERY_REQ_TIMEOUT) { 898 dev_err(hba->dev, 899 "Timedout waiting for UTP response\n"); 900 901 return -ETIMEDOUT; 902 } 903 904 if (enabled_intr_status & UFSHCD_ERROR_MASK) { 905 dev_err(hba->dev, "Error in status:%08x\n", 906 enabled_intr_status); 907 908 return -1; 909 } 910 } while (!(enabled_intr_status & UTP_TRANSFER_REQ_COMPL)); 911 912 return 0; 913 } 914 915 /** 916 * ufshcd_get_req_rsp - returns the TR response transaction type 917 */ 918 static inline int ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr) 919 { 920 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24; 921 } 922 923 /** 924 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status 925 * 926 */ 927 static inline int ufshcd_get_tr_ocs(struct ufs_hba *hba) 928 { 929 return le32_to_cpu(hba->utrdl->header.dword_2) & MASK_OCS; 930 } 931 932 static inline int ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr) 933 { 934 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT; 935 } 936 937 static int ufshcd_check_query_response(struct ufs_hba *hba) 938 { 939 struct ufs_query_res *query_res = &hba->dev_cmd.query.response; 940 941 /* Get the UPIU response */ 942 query_res->response = ufshcd_get_rsp_upiu_result(hba->ucd_rsp_ptr) >> 943 UPIU_RSP_CODE_OFFSET; 944 return query_res->response; 945 } 946 947 /** 948 * ufshcd_copy_query_response() - Copy the Query Response and the data 949 * descriptor 950 */ 951 static int ufshcd_copy_query_response(struct ufs_hba *hba) 952 { 953 struct ufs_query_res *query_res = &hba->dev_cmd.query.response; 954 955 memcpy(&query_res->upiu_res, &hba->ucd_rsp_ptr->qr, QUERY_OSF_SIZE); 956 957 /* Get the descriptor */ 958 if (hba->dev_cmd.query.descriptor && 959 hba->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) { 960 u8 *descp = (u8 *)hba->ucd_rsp_ptr + 961 GENERAL_UPIU_REQUEST_SIZE; 962 u16 resp_len; 963 u16 buf_len; 964 965 /* data segment length */ 966 resp_len = be32_to_cpu(hba->ucd_rsp_ptr->header.dword_2) & 967 MASK_QUERY_DATA_SEG_LEN; 968 buf_len = 969 be16_to_cpu(hba->dev_cmd.query.request.upiu_req.length); 970 if (likely(buf_len >= resp_len)) { 971 int size = ALIGN(GENERAL_UPIU_REQUEST_SIZE + resp_len, ARCH_DMA_MINALIGN); 972 973 invalidate_dcache_range((uintptr_t)hba->ucd_rsp_ptr, (uintptr_t)hba->ucd_rsp_ptr + size); 974 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len); 975 } else { 976 dev_warn(hba->dev, 977 "%s: Response size is bigger than buffer", 978 __func__); 979 return -EINVAL; 980 } 981 } else if (hba->dev_cmd.query.descriptor && hba->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_ATTR) { 982 u8 *value = (u8 *)&query_res->upiu_res.value; 983 hba->dev_cmd.query.descriptor[0] = value[11]; 984 hba->dev_cmd.query.descriptor[1] = value[10]; 985 hba->dev_cmd.query.descriptor[2] = value[9]; 986 hba->dev_cmd.query.descriptor[3] = value[8]; 987 } 988 989 return 0; 990 } 991 992 /** 993 * ufshcd_exec_dev_cmd - API for sending device management requests 994 */ 995 static int ufshcd_exec_dev_cmd(struct ufs_hba *hba, enum dev_cmd_type cmd_type, 996 int timeout) 997 { 998 int err; 999 int resp; 1000 1001 err = ufshcd_comp_devman_upiu(hba, cmd_type); 1002 if (err) 1003 return err; 1004 1005 err = ufshcd_send_command(hba, TASK_TAG); 1006 if (err) 1007 return err; 1008 1009 err = ufshcd_get_tr_ocs(hba); 1010 if (err) { 1011 dev_err(hba->dev, "Error in OCS:%d\n", err); 1012 return -EINVAL; 1013 } 1014 1015 resp = ufshcd_get_req_rsp(hba->ucd_rsp_ptr); 1016 switch (resp) { 1017 case UPIU_TRANSACTION_NOP_IN: 1018 break; 1019 case UPIU_TRANSACTION_QUERY_RSP: 1020 err = ufshcd_check_query_response(hba); 1021 if (!err) 1022 err = ufshcd_copy_query_response(hba); 1023 break; 1024 case UPIU_TRANSACTION_REJECT_UPIU: 1025 /* TODO: handle Reject UPIU Response */ 1026 err = -EPERM; 1027 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n", 1028 __func__); 1029 break; 1030 default: 1031 err = -EINVAL; 1032 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n", 1033 __func__, resp); 1034 } 1035 1036 return err; 1037 } 1038 1039 /** 1040 * ufshcd_init_query() - init the query response and request parameters 1041 */ 1042 static inline void ufshcd_init_query(struct ufs_hba *hba, 1043 struct ufs_query_req **request, 1044 struct ufs_query_res **response, 1045 enum query_opcode opcode, 1046 u8 idn, u8 index, u8 selector) 1047 { 1048 *request = &hba->dev_cmd.query.request; 1049 *response = &hba->dev_cmd.query.response; 1050 memset(*request, 0, sizeof(struct ufs_query_req)); 1051 memset(*response, 0, sizeof(struct ufs_query_res)); 1052 (*request)->upiu_req.opcode = opcode; 1053 (*request)->upiu_req.idn = idn; 1054 (*request)->upiu_req.index = index; 1055 (*request)->upiu_req.selector = selector; 1056 } 1057 1058 /** 1059 * ufshcd_query_flag() - API function for sending flag query requests 1060 */ 1061 int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode, 1062 enum flag_idn idn, bool *flag_res) 1063 { 1064 struct ufs_query_req *request = NULL; 1065 struct ufs_query_res *response = NULL; 1066 int err, index = 0, selector = 0; 1067 int timeout = QUERY_REQ_TIMEOUT; 1068 1069 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 1070 selector); 1071 1072 switch (opcode) { 1073 case UPIU_QUERY_OPCODE_SET_FLAG: 1074 case UPIU_QUERY_OPCODE_CLEAR_FLAG: 1075 case UPIU_QUERY_OPCODE_TOGGLE_FLAG: 1076 case UPIU_QUERY_OPCODE_WRITE_ATTR: 1077 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 1078 break; 1079 case UPIU_QUERY_OPCODE_READ_ATTR: 1080 case UPIU_QUERY_OPCODE_READ_FLAG: 1081 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 1082 if (!flag_res) { 1083 /* No dummy reads */ 1084 dev_err(hba->dev, "%s: Invalid argument for read request\n", 1085 __func__); 1086 err = -EINVAL; 1087 goto out; 1088 } 1089 break; 1090 default: 1091 dev_err(hba->dev, 1092 "%s: Expected query flag opcode but got = %d\n", 1093 __func__, opcode); 1094 err = -EINVAL; 1095 goto out; 1096 } 1097 1098 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout); 1099 1100 if (err) { 1101 dev_err(hba->dev, 1102 "%s: Sending flag query for idn %d failed, err = %d\n", 1103 __func__, idn, err); 1104 goto out; 1105 } 1106 1107 if (flag_res) 1108 *flag_res = (be32_to_cpu(response->upiu_res.value) & 1109 MASK_QUERY_UPIU_FLAG_LOC) & 0x1; 1110 1111 out: 1112 return err; 1113 } 1114 1115 static int ufshcd_query_flag_retry(struct ufs_hba *hba, 1116 enum query_opcode opcode, 1117 enum flag_idn idn, bool *flag_res) 1118 { 1119 int ret; 1120 int retries; 1121 1122 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) { 1123 ret = ufshcd_query_flag(hba, opcode, idn, flag_res); 1124 if (ret) 1125 dev_dbg(hba->dev, 1126 "%s: failed with error %d, retries %d\n", 1127 __func__, ret, retries); 1128 else 1129 break; 1130 } 1131 1132 if (ret) 1133 dev_err(hba->dev, 1134 "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n", 1135 __func__, opcode, idn, ret, retries); 1136 return ret; 1137 } 1138 1139 static int __ufshcd_query_descriptor(struct ufs_hba *hba, 1140 enum query_opcode opcode, 1141 enum desc_idn idn, u8 index, u8 selector, 1142 u8 *desc_buf, int *buf_len) 1143 { 1144 struct ufs_query_req *request = NULL; 1145 struct ufs_query_res *response = NULL; 1146 int err; 1147 1148 if (!desc_buf) { 1149 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n", 1150 __func__, opcode); 1151 err = -EINVAL; 1152 goto out; 1153 } 1154 1155 if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) { 1156 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n", 1157 __func__, *buf_len); 1158 err = -EINVAL; 1159 goto out; 1160 } 1161 1162 ufshcd_init_query(hba, &request, &response, opcode, idn, index, selector); 1163 hba->dev_cmd.query.descriptor = desc_buf; 1164 request->upiu_req.length = cpu_to_be16(*buf_len); 1165 1166 switch (opcode) { 1167 case UPIU_QUERY_OPCODE_WRITE_ATTR: 1168 request->upiu_req.value = (desc_buf[0] << 24 | desc_buf[1] << 16 | desc_buf[2] << 8 | desc_buf[3]); 1169 case UPIU_QUERY_OPCODE_WRITE_DESC: 1170 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 1171 break; 1172 case UPIU_QUERY_OPCODE_READ_ATTR: 1173 case UPIU_QUERY_OPCODE_READ_DESC: 1174 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 1175 break; 1176 default: 1177 dev_err(hba->dev, "%s: Expected query descriptor opcode but got = 0x%.2x\n", 1178 __func__, opcode); 1179 err = -EINVAL; 1180 goto out; 1181 } 1182 1183 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 1184 1185 if (err) { 1186 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n", 1187 __func__, opcode, idn, index, err); 1188 goto out; 1189 } 1190 1191 hba->dev_cmd.query.descriptor = NULL; 1192 *buf_len = be16_to_cpu(response->upiu_res.length); 1193 1194 out: 1195 return err; 1196 } 1197 1198 /** 1199 * ufshcd_query_descriptor_retry - API function for sending descriptor requests 1200 */ 1201 int ufshcd_query_descriptor_retry(struct ufs_hba *hba, enum query_opcode opcode, 1202 enum desc_idn idn, u8 index, u8 selector, 1203 u8 *desc_buf, int *buf_len) 1204 { 1205 int err; 1206 int retries; 1207 1208 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) { 1209 err = __ufshcd_query_descriptor(hba, opcode, idn, index, 1210 selector, desc_buf, buf_len); 1211 if (!err || err == -EINVAL) 1212 break; 1213 } 1214 1215 return err; 1216 } 1217 1218 /** 1219 * ufshcd_read_desc_length - read the specified descriptor length from header 1220 */ 1221 int ufshcd_read_desc_length(struct ufs_hba *hba, enum desc_idn desc_id, 1222 int desc_index, int *desc_length) 1223 { 1224 int ret; 1225 u8 header[QUERY_DESC_HDR_SIZE]; 1226 int header_len = QUERY_DESC_HDR_SIZE; 1227 1228 if (desc_id >= QUERY_DESC_IDN_MAX) 1229 return -EINVAL; 1230 1231 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC, 1232 desc_id, desc_index, 0, header, 1233 &header_len); 1234 1235 if (ret) { 1236 dev_err(hba->dev, "%s: Failed to get descriptor header id %d\n", 1237 __func__, desc_id); 1238 return ret; 1239 } else if (desc_id != header[QUERY_DESC_DESC_TYPE_OFFSET]) { 1240 dev_warn(hba->dev, "%s: descriptor header id %d and desc_id %d mismatch\n", 1241 __func__, header[QUERY_DESC_DESC_TYPE_OFFSET], 1242 desc_id); 1243 ret = -EINVAL; 1244 } 1245 1246 *desc_length = header[QUERY_DESC_LENGTH_OFFSET]; 1247 1248 return ret; 1249 } 1250 1251 static void ufshcd_init_desc_sizes(struct ufs_hba *hba) 1252 { 1253 int err; 1254 1255 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_DEVICE, 0, 1256 &hba->desc_size.dev_desc); 1257 if (err) 1258 hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE; 1259 1260 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_POWER, 0, 1261 &hba->desc_size.pwr_desc); 1262 if (err) 1263 hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE; 1264 1265 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_INTERCONNECT, 0, 1266 &hba->desc_size.interc_desc); 1267 if (err) 1268 hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE; 1269 1270 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_CONFIGURATION, 0, 1271 &hba->desc_size.conf_desc); 1272 if (err) 1273 hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE; 1274 1275 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_UNIT, 0, 1276 &hba->desc_size.unit_desc); 1277 if (err) 1278 hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE; 1279 1280 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_GEOMETRY, 0, 1281 &hba->desc_size.geom_desc); 1282 if (err) 1283 hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE; 1284 1285 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_HEALTH, 0, 1286 &hba->desc_size.hlth_desc); 1287 if (err) 1288 hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE; 1289 } 1290 1291 /** 1292 * ufshcd_map_desc_id_to_length - map descriptor IDN to its length 1293 * 1294 */ 1295 int ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id, 1296 int *desc_len) 1297 { 1298 switch (desc_id) { 1299 case QUERY_DESC_IDN_DEVICE: 1300 *desc_len = hba->desc_size.dev_desc; 1301 break; 1302 case QUERY_DESC_IDN_POWER: 1303 *desc_len = hba->desc_size.pwr_desc; 1304 break; 1305 case QUERY_DESC_IDN_GEOMETRY: 1306 *desc_len = hba->desc_size.geom_desc; 1307 break; 1308 case QUERY_DESC_IDN_CONFIGURATION: 1309 *desc_len = hba->desc_size.conf_desc; 1310 break; 1311 case QUERY_DESC_IDN_UNIT: 1312 *desc_len = hba->desc_size.unit_desc; 1313 break; 1314 case QUERY_DESC_IDN_INTERCONNECT: 1315 *desc_len = hba->desc_size.interc_desc; 1316 break; 1317 case QUERY_DESC_IDN_STRING: 1318 *desc_len = QUERY_DESC_MAX_SIZE; 1319 break; 1320 case QUERY_DESC_IDN_HEALTH: 1321 *desc_len = hba->desc_size.hlth_desc; 1322 break; 1323 case QUERY_DESC_IDN_RFU_0: 1324 case QUERY_DESC_IDN_RFU_1: 1325 *desc_len = 0; 1326 break; 1327 default: 1328 *desc_len = 0; 1329 return -EINVAL; 1330 } 1331 return 0; 1332 } 1333 EXPORT_SYMBOL(ufshcd_map_desc_id_to_length); 1334 1335 /** 1336 * ufshcd_read_desc_param - read the specified descriptor parameter 1337 * 1338 */ 1339 int ufshcd_read_desc_param(struct ufs_hba *hba, enum desc_idn desc_id, 1340 int desc_index, u8 param_offset, u8 *param_read_buf, 1341 u8 param_size) 1342 { 1343 int ret; 1344 u8 *desc_buf; 1345 int buff_len; 1346 bool is_kmalloc = true; 1347 1348 /* Safety check */ 1349 if (desc_id >= QUERY_DESC_IDN_MAX || !param_size) 1350 return -EINVAL; 1351 1352 /* Get the max length of descriptor from structure filled up at probe 1353 * time. 1354 */ 1355 ret = ufshcd_map_desc_id_to_length(hba, desc_id, &buff_len); 1356 1357 /* Sanity checks */ 1358 if (ret || !buff_len) { 1359 dev_err(hba->dev, "%s: Failed to get full descriptor length\n", 1360 __func__); 1361 return ret; 1362 } 1363 1364 /* Check whether we need temp memory */ 1365 if (param_offset != 0 || param_size < buff_len) { 1366 desc_buf = kmalloc(buff_len, GFP_KERNEL); 1367 if (!desc_buf) 1368 return -ENOMEM; 1369 } else { 1370 desc_buf = param_read_buf; 1371 is_kmalloc = false; 1372 } 1373 1374 /* Request for full descriptor */ 1375 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC, 1376 desc_id, desc_index, 0, desc_buf, 1377 &buff_len); 1378 1379 if (ret) { 1380 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d\n", 1381 __func__, desc_id, desc_index, param_offset, ret); 1382 goto out; 1383 } 1384 1385 /* Sanity check */ 1386 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) { 1387 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header\n", 1388 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]); 1389 ret = -EINVAL; 1390 goto out; 1391 } 1392 1393 /* Check wherher we will not copy more data, than available */ 1394 if (is_kmalloc && param_size > buff_len) 1395 param_size = buff_len; 1396 1397 if (is_kmalloc) 1398 memcpy(param_read_buf, &desc_buf[param_offset], param_size); 1399 out: 1400 if (is_kmalloc) 1401 kfree(desc_buf); 1402 return ret; 1403 } 1404 1405 /* replace non-printable or non-ASCII characters with spaces */ 1406 static inline void ufshcd_remove_non_printable(uint8_t *val) 1407 { 1408 if (!val) 1409 return; 1410 1411 if (*val < 0x20 || *val > 0x7e) 1412 *val = ' '; 1413 } 1414 1415 /** 1416 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power 1417 * state) and waits for it to take effect. 1418 * 1419 */ 1420 static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd) 1421 { 1422 unsigned long start = 0; 1423 u8 status; 1424 int ret; 1425 1426 ret = ufshcd_send_uic_cmd(hba, cmd); 1427 if (ret) { 1428 dev_err(hba->dev, 1429 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n", 1430 cmd->command, cmd->argument3, ret); 1431 1432 return ret; 1433 } 1434 1435 start = get_timer(0); 1436 do { 1437 status = ufshcd_get_upmcrs(hba); 1438 if (get_timer(start) > UFS_UIC_CMD_TIMEOUT) { 1439 dev_err(hba->dev, 1440 "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n", 1441 cmd->command, status); 1442 ret = (status != PWR_OK) ? status : -1; 1443 break; 1444 } 1445 } while (status != PWR_LOCAL); 1446 1447 return ret; 1448 } 1449 1450 /** 1451 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode change 1452 * using DME_SET primitives. 1453 */ 1454 static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode) 1455 { 1456 struct uic_command uic_cmd = {0}; 1457 int ret; 1458 1459 uic_cmd.command = UIC_CMD_DME_SET; 1460 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE); 1461 uic_cmd.argument3 = mode; 1462 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 1463 1464 return ret; 1465 } 1466 1467 static 1468 void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufs_hba *hba, 1469 struct scsi_cmd *pccb, u32 upiu_flags) 1470 { 1471 struct utp_upiu_req *ucd_req_ptr = hba->ucd_req_ptr; 1472 unsigned int cdb_len; 1473 1474 /* command descriptor fields */ 1475 ucd_req_ptr->header.dword_0 = 1476 UPIU_HEADER_DWORD(UPIU_TRANSACTION_COMMAND, upiu_flags, 1477 pccb->lun, TASK_TAG); 1478 ucd_req_ptr->header.dword_1 = 1479 UPIU_HEADER_DWORD(UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0); 1480 1481 /* Total EHS length and Data segment length will be zero */ 1482 ucd_req_ptr->header.dword_2 = 0; 1483 1484 ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(pccb->datalen); 1485 1486 cdb_len = min_t(unsigned short, pccb->cmdlen, UFS_CDB_SIZE); 1487 memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE); 1488 memcpy(ucd_req_ptr->sc.cdb, pccb->cmd, cdb_len); 1489 1490 memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 1491 ufshcd_cache_flush_and_invalidate(ucd_req_ptr, sizeof(*ucd_req_ptr)); 1492 ufshcd_cache_flush_and_invalidate(hba->ucd_rsp_ptr, sizeof(*hba->ucd_rsp_ptr)); 1493 } 1494 1495 static inline void prepare_prdt_desc(struct ufshcd_sg_entry *entry, 1496 unsigned char *buf, ulong len) 1497 { 1498 entry->size = cpu_to_le32(len) | GENMASK(1, 0); 1499 entry->base_addr = cpu_to_le32(lower_32_bits((unsigned long)buf)); 1500 entry->upper_addr = cpu_to_le32(upper_32_bits((unsigned long)buf)); 1501 } 1502 1503 static void prepare_prdt_table(struct ufs_hba *hba, struct scsi_cmd *pccb) 1504 { 1505 struct utp_transfer_req_desc *req_desc = hba->utrdl; 1506 struct ufshcd_sg_entry *prd_table = hba->ucd_prdt_ptr; 1507 uintptr_t aaddr = (uintptr_t)(pccb->pdata) & ~(ARCH_DMA_MINALIGN - 1); 1508 ulong datalen = pccb->datalen; 1509 int table_length; 1510 u8 *buf; 1511 int i; 1512 1513 if (!datalen) { 1514 req_desc->prd_table_length = 0; 1515 ufshcd_cache_flush_and_invalidate(req_desc, sizeof(*req_desc)); 1516 return; 1517 } 1518 1519 if (pccb->dma_dir == DMA_TO_DEVICE) { /* Write to device */ 1520 flush_dcache_range(aaddr, ALIGN(aaddr + datalen + ARCH_DMA_MINALIGN - 1, ARCH_DMA_MINALIGN)); 1521 } 1522 1523 /* In any case, invalidate cache to avoid stale data in it. */ 1524 invalidate_dcache_range(aaddr, ALIGN(aaddr + datalen + ARCH_DMA_MINALIGN - 1, ARCH_DMA_MINALIGN)); 1525 1526 table_length = DIV_ROUND_UP(pccb->datalen, MAX_PRDT_ENTRY); 1527 buf = pccb->pdata; 1528 i = table_length; 1529 while (--i) { 1530 prepare_prdt_desc(&prd_table[table_length - i - 1], buf, 1531 MAX_PRDT_ENTRY - 1); 1532 buf += MAX_PRDT_ENTRY; 1533 datalen -= MAX_PRDT_ENTRY; 1534 } 1535 1536 prepare_prdt_desc(&prd_table[table_length - i - 1], buf, datalen - 1); 1537 1538 req_desc->prd_table_length = table_length; 1539 ufshcd_cache_flush_and_invalidate(prd_table, sizeof(*prd_table) * table_length); 1540 ufshcd_cache_flush_and_invalidate(req_desc, sizeof(*req_desc)); 1541 } 1542 1543 static int ufs_scsi_exec(struct udevice *scsi_dev, struct scsi_cmd *pccb) 1544 { 1545 struct ufs_hba *hba = dev_get_uclass_priv(scsi_dev->parent); 1546 struct utp_transfer_req_desc *req_desc = hba->utrdl; 1547 u32 upiu_flags; 1548 int ocs, result = 0, retry_count = 5; 1549 u8 scsi_status; 1550 1551 /* cmd do not set lun for ufs 2.1 */ 1552 if (hba->dev_desc->w_spec_version == 0x1002) /* verison 0x210 in big end */ 1553 pccb->cmd[1] &= 0x1F; 1554 retry: 1555 ufshcd_prepare_req_desc_hdr(req_desc, &upiu_flags, pccb->dma_dir); 1556 ufshcd_prepare_utp_scsi_cmd_upiu(hba, pccb, upiu_flags); 1557 prepare_prdt_table(hba, pccb); 1558 1559 ufshcd_send_command(hba, TASK_TAG); 1560 1561 ocs = ufshcd_get_tr_ocs(hba); 1562 switch (ocs) { 1563 case OCS_SUCCESS: 1564 result = ufshcd_get_req_rsp(hba->ucd_rsp_ptr); 1565 switch (result) { 1566 case UPIU_TRANSACTION_RESPONSE: 1567 result = ufshcd_get_rsp_upiu_result(hba->ucd_rsp_ptr); 1568 1569 scsi_status = result & MASK_SCSI_STATUS; 1570 1571 if ((pccb->cmd[0] == SCSI_TST_U_RDY) && scsi_status == SENSE_NOT_READY && retry_count--) 1572 goto retry; 1573 if (scsi_status) 1574 return -EINVAL; 1575 1576 break; 1577 case UPIU_TRANSACTION_REJECT_UPIU: 1578 /* TODO: handle Reject UPIU Response */ 1579 dev_err(hba->dev, 1580 "Reject UPIU not fully implemented\n"); 1581 return -EINVAL; 1582 default: 1583 dev_err(hba->dev, 1584 "Unexpected request response code = %x\n", 1585 result); 1586 return -EINVAL; 1587 } 1588 break; 1589 default: 1590 dev_err(hba->dev, "OCS error from controller = %x\n", ocs); 1591 return -EINVAL; 1592 } 1593 1594 return 0; 1595 } 1596 1597 static inline int ufshcd_read_desc(struct ufs_hba *hba, enum desc_idn desc_id, 1598 int desc_index, u8 *buf, u32 size) 1599 { 1600 return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size); 1601 } 1602 1603 static int ufshcd_read_device_desc(struct ufs_hba *hba, u8 *buf, u32 size) 1604 { 1605 return ufshcd_read_desc(hba, QUERY_DESC_IDN_DEVICE, 0, buf, size); 1606 } 1607 1608 /** 1609 * ufshcd_read_string_desc - read string descriptor 1610 * 1611 */ 1612 int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index, 1613 u8 *buf, u32 size, bool ascii) 1614 { 1615 int err = 0; 1616 1617 err = ufshcd_read_desc(hba, QUERY_DESC_IDN_STRING, desc_index, buf, 1618 size); 1619 1620 if (err) { 1621 dev_err(hba->dev, "%s: reading String Desc failed after %d retries. err = %d\n", 1622 __func__, QUERY_REQ_RETRIES, err); 1623 goto out; 1624 } 1625 1626 if (ascii) { 1627 int desc_len; 1628 int ascii_len; 1629 int i; 1630 u8 *buff_ascii; 1631 1632 desc_len = buf[0]; 1633 /* remove header and divide by 2 to move from UTF16 to UTF8 */ 1634 ascii_len = (desc_len - QUERY_DESC_HDR_SIZE) / 2 + 1; 1635 if (size < ascii_len + QUERY_DESC_HDR_SIZE) { 1636 dev_err(hba->dev, "%s: buffer allocated size is too small\n", 1637 __func__); 1638 err = -ENOMEM; 1639 goto out; 1640 } 1641 1642 buff_ascii = kmalloc(ALIGN(ascii_len, ARCH_DMA_MINALIGN), GFP_KERNEL); 1643 if (!buff_ascii) { 1644 err = -ENOMEM; 1645 goto out; 1646 } 1647 1648 /* 1649 * the descriptor contains string in UTF16 format 1650 * we need to convert to utf-8 so it can be displayed 1651 */ 1652 utf16_to_utf8(buff_ascii, 1653 (uint16_t *)&buf[QUERY_DESC_HDR_SIZE], ascii_len); 1654 1655 /* replace non-printable or non-ASCII characters with spaces */ 1656 for (i = 0; i < ascii_len; i++) 1657 ufshcd_remove_non_printable(&buff_ascii[i]); 1658 1659 memset(buf + QUERY_DESC_HDR_SIZE, 0, 1660 size - QUERY_DESC_HDR_SIZE); 1661 memcpy(buf + QUERY_DESC_HDR_SIZE, buff_ascii, ascii_len); 1662 buf[QUERY_DESC_LENGTH_OFFSET] = ascii_len + QUERY_DESC_HDR_SIZE; 1663 kfree(buff_ascii); 1664 } 1665 out: 1666 return err; 1667 } 1668 1669 static int ufs_get_device_desc(struct ufs_hba *hba, struct ufs_device_descriptor *dev_desc) 1670 { 1671 int err; 1672 size_t buff_len; 1673 1674 buff_len = sizeof(*dev_desc); 1675 if (buff_len > hba->desc_size.dev_desc) 1676 buff_len = hba->desc_size.dev_desc; 1677 1678 err = ufshcd_read_device_desc(hba, (u8 *)dev_desc, buff_len); 1679 if (err) 1680 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n", 1681 __func__, err); 1682 1683 return err; 1684 } 1685 1686 /** 1687 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device 1688 */ 1689 static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba) 1690 { 1691 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info; 1692 1693 if (hba->max_pwr_info.is_valid) 1694 return 0; 1695 1696 pwr_info->pwr_tx = FAST_MODE; 1697 pwr_info->pwr_rx = FAST_MODE; 1698 pwr_info->hs_rate = PA_HS_MODE_B; 1699 1700 /* Get the connected lane count */ 1701 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES), 1702 &pwr_info->lane_rx); 1703 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 1704 &pwr_info->lane_tx); 1705 1706 if (!pwr_info->lane_rx || !pwr_info->lane_tx) { 1707 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n", 1708 __func__, pwr_info->lane_rx, pwr_info->lane_tx); 1709 return -EINVAL; 1710 } 1711 1712 /* 1713 * First, get the maximum gears of HS speed. 1714 * If a zero value, it means there is no HSGEAR capability. 1715 * Then, get the maximum gears of PWM speed. 1716 */ 1717 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx); 1718 if (!pwr_info->gear_rx) { 1719 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), 1720 &pwr_info->gear_rx); 1721 if (!pwr_info->gear_rx) { 1722 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n", 1723 __func__, pwr_info->gear_rx); 1724 return -EINVAL; 1725 } 1726 pwr_info->pwr_rx = SLOW_MODE; 1727 } 1728 1729 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), 1730 &pwr_info->gear_tx); 1731 if (!pwr_info->gear_tx) { 1732 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), 1733 &pwr_info->gear_tx); 1734 if (!pwr_info->gear_tx) { 1735 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n", 1736 __func__, pwr_info->gear_tx); 1737 return -EINVAL; 1738 } 1739 pwr_info->pwr_tx = SLOW_MODE; 1740 } 1741 1742 hba->max_pwr_info.is_valid = true; 1743 return 0; 1744 } 1745 1746 static int ufshcd_change_power_mode(struct ufs_hba *hba, 1747 struct ufs_pa_layer_attr *pwr_mode) 1748 { 1749 int ret; 1750 1751 /* if already configured to the requested pwr_mode */ 1752 if (pwr_mode->gear_rx == hba->pwr_info.gear_rx && 1753 pwr_mode->gear_tx == hba->pwr_info.gear_tx && 1754 pwr_mode->lane_rx == hba->pwr_info.lane_rx && 1755 pwr_mode->lane_tx == hba->pwr_info.lane_tx && 1756 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx && 1757 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx && 1758 pwr_mode->hs_rate == hba->pwr_info.hs_rate) { 1759 dev_dbg(hba->dev, "%s: power already configured\n", __func__); 1760 return 0; 1761 } 1762 1763 /* 1764 * Configure attributes for power mode change with below. 1765 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION, 1766 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION, 1767 * - PA_HSSERIES 1768 */ 1769 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx); 1770 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES), 1771 pwr_mode->lane_rx); 1772 if (pwr_mode->pwr_rx == FASTAUTO_MODE || pwr_mode->pwr_rx == FAST_MODE) 1773 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE); 1774 else 1775 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE); 1776 1777 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx); 1778 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES), 1779 pwr_mode->lane_tx); 1780 if (pwr_mode->pwr_tx == FASTAUTO_MODE || pwr_mode->pwr_tx == FAST_MODE) 1781 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE); 1782 else 1783 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE); 1784 1785 if (pwr_mode->pwr_rx == FASTAUTO_MODE || 1786 pwr_mode->pwr_tx == FASTAUTO_MODE || 1787 pwr_mode->pwr_rx == FAST_MODE || 1788 pwr_mode->pwr_tx == FAST_MODE) 1789 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES), 1790 pwr_mode->hs_rate); 1791 1792 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4 | 1793 pwr_mode->pwr_tx); 1794 1795 if (ret) { 1796 dev_err(hba->dev, 1797 "%s: power mode change failed %d\n", __func__, ret); 1798 1799 return ret; 1800 } 1801 1802 /* Copy new Power Mode to power info */ 1803 memcpy(&hba->pwr_info, pwr_mode, sizeof(struct ufs_pa_layer_attr)); 1804 1805 return ret; 1806 } 1807 1808 /** 1809 * ufshcd_verify_dev_init() - Verify device initialization 1810 * 1811 */ 1812 static int ufshcd_verify_dev_init(struct ufs_hba *hba) 1813 { 1814 int retries; 1815 int err; 1816 1817 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) { 1818 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP, 1819 NOP_OUT_TIMEOUT); 1820 if (!err || err == -ETIMEDOUT) 1821 break; 1822 1823 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err); 1824 } 1825 1826 if (err) 1827 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err); 1828 1829 return err; 1830 } 1831 1832 /** 1833 * ufshcd_complete_dev_init() - checks device readiness 1834 */ 1835 static int ufshcd_complete_dev_init(struct ufs_hba *hba) 1836 { 1837 int i; 1838 int err; 1839 bool flag_res = 1; 1840 1841 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG, 1842 QUERY_FLAG_IDN_FDEVICEINIT, NULL); 1843 if (err) { 1844 dev_err(hba->dev, 1845 "%s setting fDeviceInit flag failed with error %d\n", 1846 __func__, err); 1847 goto out; 1848 } 1849 1850 /* poll for max. 1000 iterations for fDeviceInit flag to clear */ 1851 for (i = 0; i < 1000 && !err && flag_res; i++) 1852 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG, 1853 QUERY_FLAG_IDN_FDEVICEINIT, 1854 &flag_res); 1855 1856 if (err) 1857 dev_err(hba->dev, 1858 "%s reading fDeviceInit flag failed with error %d\n", 1859 __func__, err); 1860 else if (flag_res) 1861 dev_err(hba->dev, 1862 "%s fDeviceInit was not cleared by the device\n", 1863 __func__); 1864 1865 out: 1866 return err; 1867 } 1868 1869 static void ufshcd_def_desc_sizes(struct ufs_hba *hba) 1870 { 1871 hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE; 1872 hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE; 1873 hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE; 1874 hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE; 1875 hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE; 1876 hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE; 1877 hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE; 1878 } 1879 1880 int _ufs_start(struct ufs_hba *hba) 1881 { 1882 int ret; 1883 1884 ret = ufshcd_link_startup(hba); 1885 if (ret) 1886 return ret; 1887 1888 ret = ufshcd_verify_dev_init(hba); 1889 if (ret) 1890 return ret; 1891 1892 ret = ufshcd_complete_dev_init(hba); 1893 if (ret) 1894 return ret; 1895 1896 /* Init check for device descriptor sizes */ 1897 ufshcd_init_desc_sizes(hba); 1898 1899 ret = ufs_get_device_desc(hba, hba->dev_desc); 1900 if (ret) { 1901 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n", 1902 __func__, ret); 1903 1904 return ret; 1905 } 1906 1907 return ret; 1908 } 1909 1910 int ufs_start(struct ufs_hba *hba) 1911 { 1912 int ret; 1913 1914 ret = _ufs_start(hba); 1915 if (ret) 1916 return ret; 1917 1918 #if defined(CONFIG_SUPPORT_USBPLUG) 1919 ret = ufs_create_partition_inventory(hba); 1920 if (ret) { 1921 dev_err(hba->dev, "%s: Failed to creat partition. err = %d\n", __func__, ret); 1922 return ret; 1923 } 1924 #endif 1925 if (ufshcd_get_max_pwr_mode(hba)) { 1926 dev_err(hba->dev, 1927 "%s: Failed getting max supported power mode\n", 1928 __func__); 1929 } else { 1930 ret = ufshcd_change_power_mode(hba, &hba->max_pwr_info.info); 1931 if (ret) { 1932 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n", 1933 __func__, ret); 1934 1935 return ret; 1936 } 1937 1938 printf("Device at %s up at:", hba->dev->name); 1939 ufshcd_print_pwr_info(hba); 1940 } 1941 1942 return 0; 1943 } 1944 1945 int ufshcd_probe(struct udevice *ufs_dev, struct ufs_hba_ops *hba_ops) 1946 { 1947 struct ufs_hba *hba = dev_get_uclass_priv(ufs_dev); 1948 struct scsi_platdata *scsi_plat; 1949 struct udevice *scsi_dev; 1950 int err; 1951 1952 device_find_first_child(ufs_dev, &scsi_dev); 1953 if (!scsi_dev) 1954 return -ENODEV; 1955 1956 scsi_plat = dev_get_uclass_platdata(scsi_dev); 1957 scsi_plat->max_id = UFSHCD_MAX_ID; 1958 scsi_plat->max_lun = UFS_MAX_LUNS; 1959 //scsi_plat->max_bytes_per_req = UFS_MAX_BYTES; 1960 1961 hba->dev = ufs_dev; 1962 hba->ops = hba_ops; 1963 hba->mmio_base = (void *)dev_read_addr(ufs_dev); 1964 1965 /* Set descriptor lengths to specification defaults */ 1966 ufshcd_def_desc_sizes(hba); 1967 1968 ufshcd_ops_init(hba); 1969 1970 /* Read capabilties registers */ 1971 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES); 1972 1973 /* Get UFS version supported by the controller */ 1974 hba->version = ufshcd_get_ufs_version(hba); 1975 if (hba->version != UFSHCI_VERSION_10 && 1976 hba->version != UFSHCI_VERSION_11 && 1977 hba->version != UFSHCI_VERSION_20 && 1978 hba->version != UFSHCI_VERSION_21) 1979 dev_err(hba->dev, "invalid UFS version 0x%x\n", 1980 hba->version); 1981 1982 /* Get Interrupt bit mask per version */ 1983 hba->intr_mask = ufshcd_get_intr_mask(hba); 1984 1985 /* Allocate memory for host memory space */ 1986 err = ufshcd_memory_alloc(hba); 1987 if (err) { 1988 dev_err(hba->dev, "Memory allocation failed\n"); 1989 return err; 1990 } 1991 1992 /* Configure Local data structures */ 1993 ufshcd_host_memory_configure(hba); 1994 1995 /* 1996 * In order to avoid any spurious interrupt immediately after 1997 * registering UFS controller interrupt handler, clear any pending UFS 1998 * interrupt status and disable all the UFS interrupts. 1999 */ 2000 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS), 2001 REG_INTERRUPT_STATUS); 2002 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE); 2003 2004 err = ufshcd_hba_enable(hba); 2005 if (err) { 2006 dev_err(hba->dev, "Host controller enable failed\n"); 2007 return err; 2008 } 2009 2010 err = ufs_start(hba); 2011 if (err) 2012 return err; 2013 2014 return 0; 2015 } 2016 2017 int ufs_scsi_bind(struct udevice *ufs_dev, struct udevice **scsi_devp) 2018 { 2019 int ret = device_bind_driver(ufs_dev, "ufs_scsi", "ufs_scsi", 2020 scsi_devp); 2021 2022 return ret; 2023 } 2024 2025 static struct scsi_ops ufs_ops = { 2026 .exec = ufs_scsi_exec, 2027 }; 2028 2029 int ufs_probe_dev(int index) 2030 { 2031 struct udevice *dev; 2032 2033 return uclass_get_device(UCLASS_UFS, index, &dev); 2034 } 2035 2036 int ufs_probe(void) 2037 { 2038 struct udevice *dev; 2039 int ret, i; 2040 2041 for (i = 0;; i++) { 2042 ret = uclass_get_device(UCLASS_UFS, i, &dev); 2043 if (ret == -ENODEV) 2044 break; 2045 } 2046 2047 return 0; 2048 } 2049 2050 U_BOOT_DRIVER(ufs_scsi) = { 2051 .id = UCLASS_SCSI, 2052 .name = "ufs_scsi", 2053 .ops = &ufs_ops, 2054 }; 2055