1*dadf3137SMugunthan V N /* 2*dadf3137SMugunthan V N * TI OMAP timer driver 3*dadf3137SMugunthan V N * 4*dadf3137SMugunthan V N * Copyright (C) 2015, Texas Instruments, Incorporated 5*dadf3137SMugunthan V N * 6*dadf3137SMugunthan V N * SPDX-License-Identifier: GPL-2.0+ 7*dadf3137SMugunthan V N */ 8*dadf3137SMugunthan V N 9*dadf3137SMugunthan V N #include <common.h> 10*dadf3137SMugunthan V N #include <dm.h> 11*dadf3137SMugunthan V N #include <errno.h> 12*dadf3137SMugunthan V N #include <timer.h> 13*dadf3137SMugunthan V N #include <asm/io.h> 14*dadf3137SMugunthan V N #include <asm/arch/clock.h> 15*dadf3137SMugunthan V N 16*dadf3137SMugunthan V N DECLARE_GLOBAL_DATA_PTR; 17*dadf3137SMugunthan V N 18*dadf3137SMugunthan V N /* Timer register bits */ 19*dadf3137SMugunthan V N #define TCLR_START BIT(0) /* Start=1 */ 20*dadf3137SMugunthan V N #define TCLR_AUTO_RELOAD BIT(1) /* Auto reload */ 21*dadf3137SMugunthan V N #define TCLR_PRE_EN BIT(5) /* Pre-scaler enable */ 22*dadf3137SMugunthan V N #define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */ 23*dadf3137SMugunthan V N 24*dadf3137SMugunthan V N #define TIMER_CLOCK (V_SCLK / (2 << CONFIG_SYS_PTV)) 25*dadf3137SMugunthan V N 26*dadf3137SMugunthan V N struct omap_gptimer_regs { 27*dadf3137SMugunthan V N unsigned int tidr; /* offset 0x00 */ 28*dadf3137SMugunthan V N unsigned char res1[12]; 29*dadf3137SMugunthan V N unsigned int tiocp_cfg; /* offset 0x10 */ 30*dadf3137SMugunthan V N unsigned char res2[12]; 31*dadf3137SMugunthan V N unsigned int tier; /* offset 0x20 */ 32*dadf3137SMugunthan V N unsigned int tistatr; /* offset 0x24 */ 33*dadf3137SMugunthan V N unsigned int tistat; /* offset 0x28 */ 34*dadf3137SMugunthan V N unsigned int tisr; /* offset 0x2c */ 35*dadf3137SMugunthan V N unsigned int tcicr; /* offset 0x30 */ 36*dadf3137SMugunthan V N unsigned int twer; /* offset 0x34 */ 37*dadf3137SMugunthan V N unsigned int tclr; /* offset 0x38 */ 38*dadf3137SMugunthan V N unsigned int tcrr; /* offset 0x3c */ 39*dadf3137SMugunthan V N unsigned int tldr; /* offset 0x40 */ 40*dadf3137SMugunthan V N unsigned int ttgr; /* offset 0x44 */ 41*dadf3137SMugunthan V N unsigned int twpc; /* offset 0x48 */ 42*dadf3137SMugunthan V N unsigned int tmar; /* offset 0x4c */ 43*dadf3137SMugunthan V N unsigned int tcar1; /* offset 0x50 */ 44*dadf3137SMugunthan V N unsigned int tscir; /* offset 0x54 */ 45*dadf3137SMugunthan V N unsigned int tcar2; /* offset 0x58 */ 46*dadf3137SMugunthan V N }; 47*dadf3137SMugunthan V N 48*dadf3137SMugunthan V N /* Omap Timer Priv */ 49*dadf3137SMugunthan V N struct omap_timer_priv { 50*dadf3137SMugunthan V N struct omap_gptimer_regs *regs; 51*dadf3137SMugunthan V N }; 52*dadf3137SMugunthan V N 53*dadf3137SMugunthan V N static int omap_timer_get_count(struct udevice *dev, u64 *count) 54*dadf3137SMugunthan V N { 55*dadf3137SMugunthan V N struct omap_timer_priv *priv = dev_get_priv(dev); 56*dadf3137SMugunthan V N 57*dadf3137SMugunthan V N *count = readl(&priv->regs->tcrr); 58*dadf3137SMugunthan V N 59*dadf3137SMugunthan V N return 0; 60*dadf3137SMugunthan V N } 61*dadf3137SMugunthan V N 62*dadf3137SMugunthan V N static int omap_timer_probe(struct udevice *dev) 63*dadf3137SMugunthan V N { 64*dadf3137SMugunthan V N struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); 65*dadf3137SMugunthan V N struct omap_timer_priv *priv = dev_get_priv(dev); 66*dadf3137SMugunthan V N 67*dadf3137SMugunthan V N uc_priv->clock_rate = TIMER_CLOCK; 68*dadf3137SMugunthan V N 69*dadf3137SMugunthan V N /* start the counter ticking up, reload value on overflow */ 70*dadf3137SMugunthan V N writel(0, &priv->regs->tldr); 71*dadf3137SMugunthan V N /* enable timer */ 72*dadf3137SMugunthan V N writel((CONFIG_SYS_PTV << 2) | TCLR_PRE_EN | TCLR_AUTO_RELOAD | 73*dadf3137SMugunthan V N TCLR_START, &priv->regs->tclr); 74*dadf3137SMugunthan V N 75*dadf3137SMugunthan V N return 0; 76*dadf3137SMugunthan V N } 77*dadf3137SMugunthan V N 78*dadf3137SMugunthan V N static int omap_timer_ofdata_to_platdata(struct udevice *dev) 79*dadf3137SMugunthan V N { 80*dadf3137SMugunthan V N struct omap_timer_priv *priv = dev_get_priv(dev); 81*dadf3137SMugunthan V N 82*dadf3137SMugunthan V N priv->regs = (struct omap_gptimer_regs *)dev_get_addr(dev); 83*dadf3137SMugunthan V N 84*dadf3137SMugunthan V N return 0; 85*dadf3137SMugunthan V N } 86*dadf3137SMugunthan V N 87*dadf3137SMugunthan V N 88*dadf3137SMugunthan V N static const struct timer_ops omap_timer_ops = { 89*dadf3137SMugunthan V N .get_count = omap_timer_get_count, 90*dadf3137SMugunthan V N }; 91*dadf3137SMugunthan V N 92*dadf3137SMugunthan V N static const struct udevice_id omap_timer_ids[] = { 93*dadf3137SMugunthan V N { .compatible = "ti,am335x-timer" }, 94*dadf3137SMugunthan V N { .compatible = "ti,am4372-timer" }, 95*dadf3137SMugunthan V N { .compatible = "ti,omap5430-timer" }, 96*dadf3137SMugunthan V N {} 97*dadf3137SMugunthan V N }; 98*dadf3137SMugunthan V N 99*dadf3137SMugunthan V N U_BOOT_DRIVER(omap_timer) = { 100*dadf3137SMugunthan V N .name = "omap_timer", 101*dadf3137SMugunthan V N .id = UCLASS_TIMER, 102*dadf3137SMugunthan V N .of_match = omap_timer_ids, 103*dadf3137SMugunthan V N .ofdata_to_platdata = omap_timer_ofdata_to_platdata, 104*dadf3137SMugunthan V N .priv_auto_alloc_size = sizeof(struct omap_timer_priv), 105*dadf3137SMugunthan V N .probe = omap_timer_probe, 106*dadf3137SMugunthan V N .ops = &omap_timer_ops, 107*dadf3137SMugunthan V N .flags = DM_FLAG_PRE_RELOC, 108*dadf3137SMugunthan V N }; 109