1dadf3137SMugunthan V N /*
2dadf3137SMugunthan V N * TI OMAP timer driver
3dadf3137SMugunthan V N *
4dadf3137SMugunthan V N * Copyright (C) 2015, Texas Instruments, Incorporated
5dadf3137SMugunthan V N *
6dadf3137SMugunthan V N * SPDX-License-Identifier: GPL-2.0+
7dadf3137SMugunthan V N */
8dadf3137SMugunthan V N
9dadf3137SMugunthan V N #include <common.h>
10dadf3137SMugunthan V N #include <dm.h>
11dadf3137SMugunthan V N #include <errno.h>
12dadf3137SMugunthan V N #include <timer.h>
13dadf3137SMugunthan V N #include <asm/io.h>
14dadf3137SMugunthan V N #include <asm/arch/clock.h>
15dadf3137SMugunthan V N
16dadf3137SMugunthan V N DECLARE_GLOBAL_DATA_PTR;
17dadf3137SMugunthan V N
18dadf3137SMugunthan V N /* Timer register bits */
19dadf3137SMugunthan V N #define TCLR_START BIT(0) /* Start=1 */
20dadf3137SMugunthan V N #define TCLR_AUTO_RELOAD BIT(1) /* Auto reload */
21dadf3137SMugunthan V N #define TCLR_PRE_EN BIT(5) /* Pre-scaler enable */
22dadf3137SMugunthan V N #define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */
23dadf3137SMugunthan V N
24dadf3137SMugunthan V N #define TIMER_CLOCK (V_SCLK / (2 << CONFIG_SYS_PTV))
25dadf3137SMugunthan V N
26dadf3137SMugunthan V N struct omap_gptimer_regs {
27dadf3137SMugunthan V N unsigned int tidr; /* offset 0x00 */
28dadf3137SMugunthan V N unsigned char res1[12];
29dadf3137SMugunthan V N unsigned int tiocp_cfg; /* offset 0x10 */
30dadf3137SMugunthan V N unsigned char res2[12];
31dadf3137SMugunthan V N unsigned int tier; /* offset 0x20 */
32dadf3137SMugunthan V N unsigned int tistatr; /* offset 0x24 */
33dadf3137SMugunthan V N unsigned int tistat; /* offset 0x28 */
34dadf3137SMugunthan V N unsigned int tisr; /* offset 0x2c */
35dadf3137SMugunthan V N unsigned int tcicr; /* offset 0x30 */
36dadf3137SMugunthan V N unsigned int twer; /* offset 0x34 */
37dadf3137SMugunthan V N unsigned int tclr; /* offset 0x38 */
38dadf3137SMugunthan V N unsigned int tcrr; /* offset 0x3c */
39dadf3137SMugunthan V N unsigned int tldr; /* offset 0x40 */
40dadf3137SMugunthan V N unsigned int ttgr; /* offset 0x44 */
41dadf3137SMugunthan V N unsigned int twpc; /* offset 0x48 */
42dadf3137SMugunthan V N unsigned int tmar; /* offset 0x4c */
43dadf3137SMugunthan V N unsigned int tcar1; /* offset 0x50 */
44dadf3137SMugunthan V N unsigned int tscir; /* offset 0x54 */
45dadf3137SMugunthan V N unsigned int tcar2; /* offset 0x58 */
46dadf3137SMugunthan V N };
47dadf3137SMugunthan V N
48dadf3137SMugunthan V N /* Omap Timer Priv */
49dadf3137SMugunthan V N struct omap_timer_priv {
50dadf3137SMugunthan V N struct omap_gptimer_regs *regs;
51dadf3137SMugunthan V N };
52dadf3137SMugunthan V N
omap_timer_get_count(struct udevice * dev,u64 * count)53dadf3137SMugunthan V N static int omap_timer_get_count(struct udevice *dev, u64 *count)
54dadf3137SMugunthan V N {
55dadf3137SMugunthan V N struct omap_timer_priv *priv = dev_get_priv(dev);
56dadf3137SMugunthan V N
57dadf3137SMugunthan V N *count = readl(&priv->regs->tcrr);
58dadf3137SMugunthan V N
59dadf3137SMugunthan V N return 0;
60dadf3137SMugunthan V N }
61dadf3137SMugunthan V N
omap_timer_probe(struct udevice * dev)62dadf3137SMugunthan V N static int omap_timer_probe(struct udevice *dev)
63dadf3137SMugunthan V N {
64dadf3137SMugunthan V N struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
65dadf3137SMugunthan V N struct omap_timer_priv *priv = dev_get_priv(dev);
66dadf3137SMugunthan V N
67dadf3137SMugunthan V N uc_priv->clock_rate = TIMER_CLOCK;
68dadf3137SMugunthan V N
69dadf3137SMugunthan V N /* start the counter ticking up, reload value on overflow */
70dadf3137SMugunthan V N writel(0, &priv->regs->tldr);
71dadf3137SMugunthan V N /* enable timer */
72dadf3137SMugunthan V N writel((CONFIG_SYS_PTV << 2) | TCLR_PRE_EN | TCLR_AUTO_RELOAD |
73dadf3137SMugunthan V N TCLR_START, &priv->regs->tclr);
74dadf3137SMugunthan V N
75dadf3137SMugunthan V N return 0;
76dadf3137SMugunthan V N }
77dadf3137SMugunthan V N
omap_timer_ofdata_to_platdata(struct udevice * dev)78dadf3137SMugunthan V N static int omap_timer_ofdata_to_platdata(struct udevice *dev)
79dadf3137SMugunthan V N {
80dadf3137SMugunthan V N struct omap_timer_priv *priv = dev_get_priv(dev);
81dadf3137SMugunthan V N
82*a821c4afSSimon Glass priv->regs = map_physmem(devfdt_get_addr(dev),
83871ca263SLokesh Vutla sizeof(struct omap_gptimer_regs), MAP_NOCACHE);
84dadf3137SMugunthan V N
85dadf3137SMugunthan V N return 0;
86dadf3137SMugunthan V N }
87dadf3137SMugunthan V N
88dadf3137SMugunthan V N
89dadf3137SMugunthan V N static const struct timer_ops omap_timer_ops = {
90dadf3137SMugunthan V N .get_count = omap_timer_get_count,
91dadf3137SMugunthan V N };
92dadf3137SMugunthan V N
93dadf3137SMugunthan V N static const struct udevice_id omap_timer_ids[] = {
94dadf3137SMugunthan V N { .compatible = "ti,am335x-timer" },
95dadf3137SMugunthan V N { .compatible = "ti,am4372-timer" },
96dadf3137SMugunthan V N { .compatible = "ti,omap5430-timer" },
97dadf3137SMugunthan V N {}
98dadf3137SMugunthan V N };
99dadf3137SMugunthan V N
100dadf3137SMugunthan V N U_BOOT_DRIVER(omap_timer) = {
101dadf3137SMugunthan V N .name = "omap_timer",
102dadf3137SMugunthan V N .id = UCLASS_TIMER,
103dadf3137SMugunthan V N .of_match = omap_timer_ids,
104dadf3137SMugunthan V N .ofdata_to_platdata = omap_timer_ofdata_to_platdata,
105dadf3137SMugunthan V N .priv_auto_alloc_size = sizeof(struct omap_timer_priv),
106dadf3137SMugunthan V N .probe = omap_timer_probe,
107dadf3137SMugunthan V N .ops = &omap_timer_ops,
108dadf3137SMugunthan V N .flags = DM_FLAG_PRE_RELOC,
109dadf3137SMugunthan V N };
110