1*f5076f86Srick /* 2*f5076f86Srick * Andestech ATFTMR010 timer driver 3*f5076f86Srick * 4*f5076f86Srick * (C) Copyright 2016 5*f5076f86Srick * Rick Chen, NDS32 Software Engineering, rick@andestech.com 6*f5076f86Srick * 7*f5076f86Srick * SPDX-License-Identifier: GPL-2.0+ 8*f5076f86Srick */ 9*f5076f86Srick #include <common.h> 10*f5076f86Srick #include <dm.h> 11*f5076f86Srick #include <errno.h> 12*f5076f86Srick #include <timer.h> 13*f5076f86Srick #include <linux/io.h> 14*f5076f86Srick 15*f5076f86Srick DECLARE_GLOBAL_DATA_PTR; 16*f5076f86Srick 17*f5076f86Srick /* 18*f5076f86Srick * Timer Control Register 19*f5076f86Srick */ 20*f5076f86Srick #define T3_UPDOWN (1 << 11) 21*f5076f86Srick #define T2_UPDOWN (1 << 10) 22*f5076f86Srick #define T1_UPDOWN (1 << 9) 23*f5076f86Srick #define T3_OFENABLE (1 << 8) 24*f5076f86Srick #define T3_CLOCK (1 << 7) 25*f5076f86Srick #define T3_ENABLE (1 << 6) 26*f5076f86Srick #define T2_OFENABLE (1 << 5) 27*f5076f86Srick #define T2_CLOCK (1 << 4) 28*f5076f86Srick #define T2_ENABLE (1 << 3) 29*f5076f86Srick #define T1_OFENABLE (1 << 2) 30*f5076f86Srick #define T1_CLOCK (1 << 1) 31*f5076f86Srick #define T1_ENABLE (1 << 0) 32*f5076f86Srick 33*f5076f86Srick /* 34*f5076f86Srick * Timer Interrupt State & Mask Registers 35*f5076f86Srick */ 36*f5076f86Srick #define T3_OVERFLOW (1 << 8) 37*f5076f86Srick #define T3_MATCH2 (1 << 7) 38*f5076f86Srick #define T3_MATCH1 (1 << 6) 39*f5076f86Srick #define T2_OVERFLOW (1 << 5) 40*f5076f86Srick #define T2_MATCH2 (1 << 4) 41*f5076f86Srick #define T2_MATCH1 (1 << 3) 42*f5076f86Srick #define T1_OVERFLOW (1 << 2) 43*f5076f86Srick #define T1_MATCH2 (1 << 1) 44*f5076f86Srick #define T1_MATCH1 (1 << 0) 45*f5076f86Srick 46*f5076f86Srick struct atftmr_timer_regs { 47*f5076f86Srick u32 t1_counter; /* 0x00 */ 48*f5076f86Srick u32 t1_load; /* 0x04 */ 49*f5076f86Srick u32 t1_match1; /* 0x08 */ 50*f5076f86Srick u32 t1_match2; /* 0x0c */ 51*f5076f86Srick u32 t2_counter; /* 0x10 */ 52*f5076f86Srick u32 t2_load; /* 0x14 */ 53*f5076f86Srick u32 t2_match1; /* 0x18 */ 54*f5076f86Srick u32 t2_match2; /* 0x1c */ 55*f5076f86Srick u32 t3_counter; /* 0x20 */ 56*f5076f86Srick u32 t3_load; /* 0x24 */ 57*f5076f86Srick u32 t3_match1; /* 0x28 */ 58*f5076f86Srick u32 t3_match2; /* 0x2c */ 59*f5076f86Srick u32 cr; /* 0x30 */ 60*f5076f86Srick u32 int_state; /* 0x34 */ 61*f5076f86Srick u32 int_mask; /* 0x38 */ 62*f5076f86Srick }; 63*f5076f86Srick 64*f5076f86Srick struct atftmr_timer_platdata { 65*f5076f86Srick struct atftmr_timer_regs *regs; 66*f5076f86Srick }; 67*f5076f86Srick 68*f5076f86Srick static int atftmr_timer_get_count(struct udevice *dev, u64 *count) 69*f5076f86Srick { 70*f5076f86Srick struct atftmr_timer_platdata *plat = dev->platdata; 71*f5076f86Srick struct atftmr_timer_regs *const regs = plat->regs; 72*f5076f86Srick u32 val; 73*f5076f86Srick val = readl(®s->t3_counter); 74*f5076f86Srick *count = timer_conv_64(val); 75*f5076f86Srick return 0; 76*f5076f86Srick } 77*f5076f86Srick 78*f5076f86Srick static int atftmr_timer_probe(struct udevice *dev) 79*f5076f86Srick { 80*f5076f86Srick struct atftmr_timer_platdata *plat = dev->platdata; 81*f5076f86Srick struct atftmr_timer_regs *const regs = plat->regs; 82*f5076f86Srick u32 cr; 83*f5076f86Srick writel(0, ®s->t3_load); 84*f5076f86Srick writel(0, ®s->t3_counter); 85*f5076f86Srick writel(TIMER_LOAD_VAL, ®s->t3_match1); 86*f5076f86Srick writel(TIMER_LOAD_VAL, ®s->t3_match2); 87*f5076f86Srick /* disable interrupts */ 88*f5076f86Srick writel(T3_MATCH1|T3_MATCH2|T3_OVERFLOW , ®s->int_mask); 89*f5076f86Srick cr = readl(®s->cr); 90*f5076f86Srick cr |= (T3_ENABLE|T3_UPDOWN); 91*f5076f86Srick writel(cr, ®s->cr); 92*f5076f86Srick return 0; 93*f5076f86Srick } 94*f5076f86Srick 95*f5076f86Srick static int atftme_timer_ofdata_to_platdata(struct udevice *dev) 96*f5076f86Srick { 97*f5076f86Srick struct atftmr_timer_platdata *plat = dev_get_platdata(dev); 98*f5076f86Srick plat->regs = map_physmem(dev_get_addr(dev), 99*f5076f86Srick sizeof(struct atftmr_timer_regs), 100*f5076f86Srick MAP_NOCACHE); 101*f5076f86Srick return 0; 102*f5076f86Srick } 103*f5076f86Srick 104*f5076f86Srick static const struct timer_ops ag101p_timer_ops = { 105*f5076f86Srick .get_count = atftmr_timer_get_count, 106*f5076f86Srick }; 107*f5076f86Srick 108*f5076f86Srick static const struct udevice_id ag101p_timer_ids[] = { 109*f5076f86Srick { .compatible = "andestech,attmr010" }, 110*f5076f86Srick {} 111*f5076f86Srick }; 112*f5076f86Srick 113*f5076f86Srick U_BOOT_DRIVER(altera_timer) = { 114*f5076f86Srick .name = "ag101p_timer", 115*f5076f86Srick .id = UCLASS_TIMER, 116*f5076f86Srick .of_match = ag101p_timer_ids, 117*f5076f86Srick .ofdata_to_platdata = atftme_timer_ofdata_to_platdata, 118*f5076f86Srick .platdata_auto_alloc_size = sizeof(struct atftmr_timer_platdata), 119*f5076f86Srick .probe = atftmr_timer_probe, 120*f5076f86Srick .ops = &ag101p_timer_ops, 121*f5076f86Srick .flags = DM_FLAG_PRE_RELOC, 122*f5076f86Srick }; 123