1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6 #include <common.h> 7 #include <bitfield.h> 8 #include <thermal.h> 9 #include <dm.h> 10 #include <dm/pinctrl.h> 11 #include <div64.h> 12 #include <errno.h> 13 #include <syscon.h> 14 #include <asm/arch/clock.h> 15 #include <asm/arch/hardware.h> 16 #include <asm/io.h> 17 #include <dm/lists.h> 18 #include <clk.h> 19 #include <clk-uclass.h> 20 #include <reset.h> 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 /** 25 * If the temperature over a period of time High, 26 * the resulting TSHUT gave CRU module,let it reset the entire chip, 27 * or via GPIO give PMIC. 28 */ 29 enum tshut_mode { 30 TSHUT_MODE_CRU = 0, 31 TSHUT_MODE_GPIO, 32 }; 33 34 /** 35 * The system Temperature Sensors tshut(tshut) polarity 36 * the bit 8 is tshut polarity. 37 * 0: low active, 1: high active 38 */ 39 enum tshut_polarity { 40 TSHUT_LOW_ACTIVE = 0, 41 TSHUT_HIGH_ACTIVE, 42 }; 43 44 /** 45 * The conversion table has the adc value and temperature. 46 * ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table) 47 * ADC_INCREMENT: the adc value is incremental.(e.g. rk3368_code_table) 48 */ 49 enum adc_sort_mode { 50 ADC_DECREMENT = 0, 51 ADC_INCREMENT, 52 }; 53 54 #define SOC_MAX_SENSORS 2 55 56 #define TSADCV2_USER_CON 0x00 57 #define TSADCV2_AUTO_CON 0x04 58 #define TSADCV2_INT_EN 0x08 59 #define TSADCV2_INT_PD 0x0c 60 #define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04) 61 #define TSADCV2_COMP_INT(chn) (0x30 + (chn) * 0x04) 62 #define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04) 63 #define TSADCV2_HIGHT_INT_DEBOUNCE 0x60 64 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64 65 #define TSADCV2_AUTO_PERIOD 0x68 66 #define TSADCV2_AUTO_PERIOD_HT 0x6c 67 68 #define TSADCV2_AUTO_EN BIT(0) 69 #define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn)) 70 #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8) 71 72 #define TSADCV3_AUTO_Q_SEL_EN BIT(1) 73 74 #define TSADCV2_INT_SRC_EN(chn) BIT(chn) 75 #define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn)) 76 #define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn)) 77 78 #define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8) 79 #define TSADCV3_INT_PD_CLEAR_MASK ~BIT(16) 80 81 #define TSADCV2_DATA_MASK 0xfff 82 #define TSADCV3_DATA_MASK 0x3ff 83 84 #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4 85 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4 86 #define TSADCV2_AUTO_PERIOD_TIME 250 87 #define TSADCV2_AUTO_PERIOD_HT_TIME 50 88 #define TSADCV3_AUTO_PERIOD_TIME 1875 89 #define TSADCV3_AUTO_PERIOD_HT_TIME 1875 90 #define TSADCV5_AUTO_PERIOD_TIME 1622 /* 2.5ms */ 91 #define TSADCV5_AUTO_PERIOD_HT_TIME 1622 /* 2.5ms */ 92 93 #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */ 94 #define TSADCV5_USER_INTER_PD_SOC 0xfc0 /* 97us, at least 90us */ 95 96 #define GRF_SARADC_TESTBIT 0x0e644 97 #define GRF_TSADC_TESTBIT_L 0x0e648 98 #define GRF_TSADC_TESTBIT_H 0x0e64c 99 100 #define PX30_GRF_SOC_CON2 0x0408 101 102 #define RK3568_GRF_TSADC_CON 0x0600 103 #define RK3568_GRF_TSADC_ANA_REG0 (0x10001 << 0) 104 #define RK3568_GRF_TSADC_ANA_REG1 (0x10001 << 1) 105 #define RK3568_GRF_TSADC_ANA_REG2 (0x10001 << 2) 106 #define RK3568_GRF_TSADC_TSEN (0x10001 << 8) 107 108 #define GRF_SARADC_TESTBIT_ON (0x10001 << 2) 109 #define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2) 110 #define GRF_TSADC_VCM_EN_L (0x10001 << 7) 111 #define GRF_TSADC_VCM_EN_H (0x10001 << 7) 112 113 #define GRF_CON_TSADC_CH_INV (0x10001 << 1) 114 115 #define MIN_TEMP (-40000) 116 #define LOWEST_TEMP (-273000) 117 #define MAX_TEMP (125000) 118 #define MAX_ENV_TEMP (85000) 119 120 #define BASE (1024) 121 #define BASE_SHIFT (10) 122 #define START_DEBOUNCE_COUNT (100) 123 #define HIGHER_DEBOUNCE_TEMP (30000) 124 #define LOWER_DEBOUNCE_TEMP (15000) 125 126 /** 127 * struct tsadc_table - hold information about code and temp mapping 128 * @code: raw code from tsadc ip 129 * @temp: the mapping temperature 130 */ 131 132 struct tsadc_table { 133 unsigned long code; 134 int temp; 135 }; 136 137 struct chip_tsadc_table { 138 const struct tsadc_table *id; 139 unsigned int length; 140 u32 data_mask; 141 enum adc_sort_mode mode; 142 }; 143 144 enum sensor_id { 145 SENSOR_CPU = 0, 146 SENSOR_GPU, 147 }; 148 149 struct rockchip_tsadc_chip { 150 /* The sensor id of chip correspond to the ADC channel */ 151 int chn_id[SOC_MAX_SENSORS]; 152 int chn_num; 153 fdt_addr_t base; 154 fdt_addr_t grf; 155 156 /* The hardware-controlled tshut property */ 157 int tshut_temp; 158 enum tshut_mode tshut_mode; 159 enum tshut_polarity tshut_polarity; 160 161 void (*tsadc_control)(struct udevice *dev, bool enable); 162 void (*tsadc_init)(struct udevice *dev); 163 int (*tsadc_get_temp)(struct udevice *dev, int chn, 164 int *temp); 165 void (*irq_ack)(struct udevice *dev); 166 void (*set_alarm_temp)(struct udevice *dev, 167 int chn, int temp); 168 void (*set_tshut_temp)(struct udevice *dev, 169 int chn, int temp); 170 void (*set_tshut_mode)(struct udevice *dev, int chn, enum tshut_mode m); 171 struct chip_tsadc_table table; 172 }; 173 174 struct rockchip_thermal_priv { 175 void *base; 176 void *grf; 177 enum tshut_mode tshut_mode; 178 enum tshut_polarity tshut_polarity; 179 const struct rockchip_tsadc_chip *data; 180 }; 181 182 static const struct tsadc_table rk1808_code_table[] = { 183 {0, -40000}, 184 {3455, -40000}, 185 {3463, -35000}, 186 {3471, -30000}, 187 {3479, -25000}, 188 {3487, -20000}, 189 {3495, -15000}, 190 {3503, -10000}, 191 {3511, -5000}, 192 {3519, 0}, 193 {3527, 5000}, 194 {3535, 10000}, 195 {3543, 15000}, 196 {3551, 20000}, 197 {3559, 25000}, 198 {3567, 30000}, 199 {3576, 35000}, 200 {3584, 40000}, 201 {3592, 45000}, 202 {3600, 50000}, 203 {3609, 55000}, 204 {3617, 60000}, 205 {3625, 65000}, 206 {3633, 70000}, 207 {3642, 75000}, 208 {3650, 80000}, 209 {3659, 85000}, 210 {3667, 90000}, 211 {3675, 95000}, 212 {3684, 100000}, 213 {3692, 105000}, 214 {3701, 110000}, 215 {3709, 115000}, 216 {3718, 120000}, 217 {3726, 125000}, 218 {TSADCV2_DATA_MASK, 125000}, 219 }; 220 221 static const struct tsadc_table rk3228_code_table[] = { 222 {0, -40000}, 223 {588, -40000}, 224 {593, -35000}, 225 {598, -30000}, 226 {603, -25000}, 227 {608, -20000}, 228 {613, -15000}, 229 {618, -10000}, 230 {623, -5000}, 231 {629, 0}, 232 {634, 5000}, 233 {639, 10000}, 234 {644, 15000}, 235 {649, 20000}, 236 {654, 25000}, 237 {660, 30000}, 238 {665, 35000}, 239 {670, 40000}, 240 {675, 45000}, 241 {681, 50000}, 242 {686, 55000}, 243 {691, 60000}, 244 {696, 65000}, 245 {702, 70000}, 246 {707, 75000}, 247 {712, 80000}, 248 {717, 85000}, 249 {723, 90000}, 250 {728, 95000}, 251 {733, 100000}, 252 {738, 105000}, 253 {744, 110000}, 254 {749, 115000}, 255 {754, 120000}, 256 {760, 125000}, 257 {TSADCV2_DATA_MASK, 125000}, 258 }; 259 260 static const struct tsadc_table rk3288_code_table[] = { 261 {TSADCV2_DATA_MASK, -40000}, 262 {3800, -40000}, 263 {3792, -35000}, 264 {3783, -30000}, 265 {3774, -25000}, 266 {3765, -20000}, 267 {3756, -15000}, 268 {3747, -10000}, 269 {3737, -5000}, 270 {3728, 0}, 271 {3718, 5000}, 272 {3708, 10000}, 273 {3698, 15000}, 274 {3688, 20000}, 275 {3678, 25000}, 276 {3667, 30000}, 277 {3656, 35000}, 278 {3645, 40000}, 279 {3634, 45000}, 280 {3623, 50000}, 281 {3611, 55000}, 282 {3600, 60000}, 283 {3588, 65000}, 284 {3575, 70000}, 285 {3563, 75000}, 286 {3550, 80000}, 287 {3537, 85000}, 288 {3524, 90000}, 289 {3510, 95000}, 290 {3496, 100000}, 291 {3482, 105000}, 292 {3467, 110000}, 293 {3452, 115000}, 294 {3437, 120000}, 295 {3421, 125000}, 296 }; 297 298 static const struct tsadc_table rk3328_code_table[] = { 299 {0, -40000}, 300 {296, -40000}, 301 {304, -35000}, 302 {313, -30000}, 303 {331, -20000}, 304 {340, -15000}, 305 {349, -10000}, 306 {359, -5000}, 307 {368, 0}, 308 {378, 5000}, 309 {388, 10000}, 310 {398, 15000}, 311 {408, 20000}, 312 {418, 25000}, 313 {429, 30000}, 314 {440, 35000}, 315 {451, 40000}, 316 {462, 45000}, 317 {473, 50000}, 318 {485, 55000}, 319 {496, 60000}, 320 {508, 65000}, 321 {521, 70000}, 322 {533, 75000}, 323 {546, 80000}, 324 {559, 85000}, 325 {572, 90000}, 326 {586, 95000}, 327 {600, 100000}, 328 {614, 105000}, 329 {629, 110000}, 330 {644, 115000}, 331 {659, 120000}, 332 {675, 125000}, 333 {TSADCV2_DATA_MASK, 125000}, 334 }; 335 336 static const struct tsadc_table rk3368_code_table[] = { 337 {0, -40000}, 338 {106, -40000}, 339 {108, -35000}, 340 {110, -30000}, 341 {112, -25000}, 342 {114, -20000}, 343 {116, -15000}, 344 {118, -10000}, 345 {120, -5000}, 346 {122, 0}, 347 {124, 5000}, 348 {126, 10000}, 349 {128, 15000}, 350 {130, 20000}, 351 {132, 25000}, 352 {134, 30000}, 353 {136, 35000}, 354 {138, 40000}, 355 {140, 45000}, 356 {142, 50000}, 357 {144, 55000}, 358 {146, 60000}, 359 {148, 65000}, 360 {150, 70000}, 361 {152, 75000}, 362 {154, 80000}, 363 {156, 85000}, 364 {158, 90000}, 365 {160, 95000}, 366 {162, 100000}, 367 {163, 105000}, 368 {165, 110000}, 369 {167, 115000}, 370 {169, 120000}, 371 {171, 125000}, 372 {TSADCV3_DATA_MASK, 125000}, 373 }; 374 375 static const struct tsadc_table rk3399_code_table[] = { 376 {0, -40000}, 377 {402, -40000}, 378 {410, -35000}, 379 {419, -30000}, 380 {427, -25000}, 381 {436, -20000}, 382 {444, -15000}, 383 {453, -10000}, 384 {461, -5000}, 385 {470, 0}, 386 {478, 5000}, 387 {487, 10000}, 388 {496, 15000}, 389 {504, 20000}, 390 {513, 25000}, 391 {521, 30000}, 392 {530, 35000}, 393 {538, 40000}, 394 {547, 45000}, 395 {555, 50000}, 396 {564, 55000}, 397 {573, 60000}, 398 {581, 65000}, 399 {590, 70000}, 400 {599, 75000}, 401 {607, 80000}, 402 {616, 85000}, 403 {624, 90000}, 404 {633, 95000}, 405 {642, 100000}, 406 {650, 105000}, 407 {659, 110000}, 408 {668, 115000}, 409 {677, 120000}, 410 {685, 125000}, 411 {TSADCV3_DATA_MASK, 125000}, 412 }; 413 414 static const struct tsadc_table rk3568_code_table[] = { 415 {0, -40000}, 416 {1584, -40000}, 417 {1620, -35000}, 418 {1652, -30000}, 419 {1688, -25000}, 420 {1720, -20000}, 421 {1756, -15000}, 422 {1788, -10000}, 423 {1824, -5000}, 424 {1856, 0}, 425 {1892, 5000}, 426 {1924, 10000}, 427 {1956, 15000}, 428 {1992, 20000}, 429 {2024, 25000}, 430 {2060, 30000}, 431 {2092, 35000}, 432 {2128, 40000}, 433 {2160, 45000}, 434 {2196, 50000}, 435 {2228, 55000}, 436 {2264, 60000}, 437 {2300, 65000}, 438 {2332, 70000}, 439 {2368, 75000}, 440 {2400, 80000}, 441 {2436, 85000}, 442 {2468, 90000}, 443 {2500, 95000}, 444 {2536, 100000}, 445 {2572, 105000}, 446 {2604, 110000}, 447 {2636, 115000}, 448 {2672, 120000}, 449 {2704, 125000}, 450 {TSADCV2_DATA_MASK, 125000}, 451 }; 452 453 /* 454 * Struct used for matching a device 455 */ 456 struct of_device_id { 457 char compatible[32]; 458 const void *data; 459 }; 460 461 static int tsadc_code_to_temp(struct chip_tsadc_table *table, u32 code, 462 int *temp) 463 { 464 unsigned int low = 1; 465 unsigned int high = table->length - 1; 466 unsigned int mid = (low + high) / 2; 467 unsigned int num; 468 unsigned long denom; 469 470 switch (table->mode) { 471 case ADC_DECREMENT: 472 code &= table->data_mask; 473 if (code < table->id[high].code) 474 return -EAGAIN; /* Incorrect reading */ 475 476 while (low <= high) { 477 if (code >= table->id[mid].code && 478 code < table->id[mid - 1].code) 479 break; 480 else if (code < table->id[mid].code) 481 low = mid + 1; 482 else 483 high = mid - 1; 484 485 mid = (low + high) / 2; 486 } 487 break; 488 case ADC_INCREMENT: 489 code &= table->data_mask; 490 if (code < table->id[low].code) 491 return -EAGAIN; /* Incorrect reading */ 492 493 while (low <= high) { 494 if (code <= table->id[mid].code && 495 code > table->id[mid - 1].code) 496 break; 497 else if (code > table->id[mid].code) 498 low = mid + 1; 499 else 500 high = mid - 1; 501 502 mid = (low + high) / 2; 503 } 504 break; 505 default: 506 printf("%s: Invalid the conversion table mode=%d\n", 507 __func__, table->mode); 508 return -EINVAL; 509 } 510 511 /* 512 * The 5C granularity provided by the table is too much. Let's 513 * assume that the relationship between sensor readings and 514 * temperature between 2 table entries is linear and interpolate 515 * to produce less granular result. 516 */ 517 num = table->id[mid].temp - table->id[mid - 1].temp; 518 num *= abs(table->id[mid - 1].code - code); 519 denom = abs(table->id[mid - 1].code - table->id[mid].code); 520 *temp = table->id[mid - 1].temp + (num / denom); 521 522 return 0; 523 } 524 525 static u32 tsadc_temp_to_code_v2(struct chip_tsadc_table table, 526 int temp) 527 { 528 int high, low, mid; 529 u32 error = table.data_mask; 530 531 low = 0; 532 high = table.length - 1; 533 mid = (high + low) / 2; 534 535 /* Return mask code data when the temp is over table range */ 536 if (temp < table.id[low].temp || temp > table.id[high].temp) 537 goto exit; 538 539 while (low <= high) { 540 if (temp == table.id[mid].temp) 541 return table.id[mid].code; 542 else if (temp < table.id[mid].temp) 543 high = mid - 1; 544 else 545 low = mid + 1; 546 mid = (low + high) / 2; 547 } 548 549 exit: 550 pr_err("%s: Invalid conversion table: code=%d, temperature=%d\n", 551 __func__, error, temp); 552 553 return error; 554 } 555 556 static void tsadc_irq_ack_v2(struct udevice *dev) 557 { 558 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 559 u32 val; 560 561 val = readl(priv->base + TSADCV2_INT_PD); 562 writel(val & TSADCV2_INT_PD_CLEAR_MASK, priv->base + TSADCV2_INT_PD); 563 } 564 565 static void tsadc_irq_ack_v3(struct udevice *dev) 566 { 567 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 568 u32 val; 569 570 val = readl(priv->base + TSADCV2_INT_PD); 571 writel(val & TSADCV3_INT_PD_CLEAR_MASK, priv->base + TSADCV2_INT_PD); 572 } 573 574 static void tsadc_control_v3(struct udevice *dev, bool enable) 575 { 576 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 577 u32 val; 578 579 val = readl(priv->base + TSADCV2_AUTO_CON); 580 if (enable) 581 val |= TSADCV2_AUTO_EN | TSADCV3_AUTO_Q_SEL_EN; 582 else 583 val &= ~TSADCV2_AUTO_EN; 584 585 writel(val, priv->base + TSADCV2_AUTO_CON); 586 } 587 588 static void tsadc_control_v2(struct udevice *dev, bool enable) 589 { 590 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 591 u32 val; 592 593 val = readl(priv->base + TSADCV2_AUTO_CON); 594 if (enable) 595 val |= TSADCV2_AUTO_EN; 596 else 597 val &= ~TSADCV2_AUTO_EN; 598 599 writel(val, priv->base + TSADCV2_AUTO_CON); 600 } 601 602 static void tsadc_init_v2(struct udevice *dev) 603 { 604 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 605 606 writel(TSADCV2_AUTO_PERIOD_TIME, 607 priv->base + TSADCV2_AUTO_PERIOD); 608 writel(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, 609 priv->base + TSADCV2_HIGHT_INT_DEBOUNCE); 610 writel(TSADCV2_AUTO_PERIOD_HT_TIME, 611 priv->base + TSADCV2_AUTO_PERIOD_HT); 612 writel(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, 613 priv->base + TSADCV2_HIGHT_TSHUT_DEBOUNCE); 614 615 if (priv->tshut_polarity == TSHUT_HIGH_ACTIVE) 616 writel(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 617 priv->base + TSADCV2_AUTO_CON); 618 else 619 writel(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 620 priv->base + TSADCV2_AUTO_CON); 621 } 622 623 static void tsadc_init_v3(struct udevice *dev) 624 { 625 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 626 627 if (!IS_ERR(priv->grf)) { 628 writel(GRF_TSADC_VCM_EN_L, priv->grf + GRF_TSADC_TESTBIT_L); 629 writel(GRF_TSADC_VCM_EN_H, priv->grf + GRF_TSADC_TESTBIT_H); 630 631 udelay(100);/* The spec note says at least 15 us */ 632 writel(GRF_SARADC_TESTBIT_ON, priv->grf + GRF_SARADC_TESTBIT); 633 writel(GRF_TSADC_TESTBIT_H_ON, priv->grf + GRF_TSADC_TESTBIT_H); 634 udelay(200);/* The spec note says at least 90 us */ 635 } 636 tsadc_init_v2(dev); 637 } 638 639 static void __maybe_unused tsadc_init_v5(struct udevice *dev) 640 { 641 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 642 643 /* Set interleave value to workround ic time sync issue */ 644 writel(TSADCV2_USER_INTER_PD_SOC, priv->base + 645 TSADCV2_USER_CON); 646 tsadc_init_v2(dev); 647 } 648 649 static void tsadc_init_v4(struct udevice *dev) 650 { 651 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 652 653 tsadc_init_v2(dev); 654 if (!IS_ERR(priv->grf)) 655 writel(GRF_CON_TSADC_CH_INV, priv->grf + PX30_GRF_SOC_CON2); 656 } 657 658 static void tsadc_init_v7(struct udevice *dev) 659 { 660 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 661 662 writel(TSADCV5_USER_INTER_PD_SOC, 663 priv->base + TSADCV2_USER_CON); 664 writel(TSADCV5_AUTO_PERIOD_TIME, 665 priv->base + TSADCV2_AUTO_PERIOD); 666 writel(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, 667 priv->base + TSADCV2_HIGHT_INT_DEBOUNCE); 668 writel(TSADCV5_AUTO_PERIOD_HT_TIME, 669 priv->base + TSADCV2_AUTO_PERIOD_HT); 670 writel(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, 671 priv->base + TSADCV2_HIGHT_TSHUT_DEBOUNCE); 672 673 if (priv->tshut_polarity == TSHUT_HIGH_ACTIVE) 674 writel(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 675 priv->base + TSADCV2_AUTO_CON); 676 else 677 writel(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 678 priv->base + TSADCV2_AUTO_CON); 679 680 if (!IS_ERR(priv->grf)) { 681 writel(RK3568_GRF_TSADC_TSEN, 682 priv->grf + RK3568_GRF_TSADC_CON); 683 udelay(15); 684 writel(RK3568_GRF_TSADC_ANA_REG0, 685 priv->grf + RK3568_GRF_TSADC_CON); 686 writel(RK3568_GRF_TSADC_ANA_REG1, 687 priv->grf + RK3568_GRF_TSADC_CON); 688 writel(RK3568_GRF_TSADC_ANA_REG2, 689 priv->grf + RK3568_GRF_TSADC_CON); 690 udelay(200); 691 } 692 } 693 694 static int tsadc_get_temp_v2(struct udevice *dev, 695 int chn, int *temp) 696 { 697 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 698 struct chip_tsadc_table table = priv->data->table; 699 u32 val; 700 701 val = readl(priv->base + TSADCV2_DATA(chn)); 702 703 return tsadc_code_to_temp(&table, val, temp); 704 } 705 706 static int predict_temp(int temp) 707 { 708 /* 709 * The deviation of prediction. the temperature will not change rapidly, 710 * so this cov_q is small 711 */ 712 int cov_q = 18; 713 /* 714 * The deviation of tsadc's reading, deviation of tsadc is very big when 715 * abnormal temperature is get 716 */ 717 int cov_r = 542; 718 719 int gain; 720 int temp_mid; 721 int temp_now; 722 int prob_mid; 723 int prob_now; 724 static int temp_last = LOWEST_TEMP; 725 static int prob_last = 160; 726 static int bounding_cnt; 727 728 /* 729 * init temp_last with a more suitable value, which mostly equals to 730 * temp reading from tsadc, but not higher than MAX_ENV_TEMP. If the 731 * temp is higher than MAX_ENV_TEMP, it is assumed to be abnormal 732 * value and temp_last is adjusted to MAX_ENV_TEMP. 733 */ 734 if (temp_last == LOWEST_TEMP) 735 temp_last = min(temp, MAX_ENV_TEMP); 736 737 /* 738 * Before START_DEBOUNCE_COUNT's samples of temperature, we consider 739 * tsadc is stable, i.e. after that, the temperature may be not stable 740 * and may have abnormal reading, so we set a bounding temperature. If 741 * the reading from tsadc is too big, we set the delta temperature of 742 * DEBOUNCE_TEMP/3 comparing to the last temperature. 743 */ 744 745 if (bounding_cnt++ > START_DEBOUNCE_COUNT) { 746 bounding_cnt = START_DEBOUNCE_COUNT; 747 if (temp - temp_last > HIGHER_DEBOUNCE_TEMP) 748 temp = temp_last + HIGHER_DEBOUNCE_TEMP / 3; 749 if (temp_last - temp > LOWER_DEBOUNCE_TEMP) 750 temp = temp_last - LOWER_DEBOUNCE_TEMP / 3; 751 } 752 753 temp_mid = temp_last; 754 755 /* calculate the probability of this time's prediction */ 756 prob_mid = prob_last + cov_q; 757 758 /* calculate the Kalman Gain */ 759 gain = (prob_mid * BASE) / (prob_mid + cov_r); 760 761 /* calculate the prediction of temperature */ 762 temp_now = (temp_mid * BASE + gain * (temp - temp_mid)) >> BASE_SHIFT; 763 764 /* 765 * Base on this time's Kalman Gain, ajust our probability of prediction 766 * for next time calculation 767 */ 768 prob_now = ((BASE - gain) * prob_mid) >> BASE_SHIFT; 769 770 prob_last = prob_now; 771 temp_last = temp_now; 772 773 return temp_last; 774 } 775 776 static int tsadc_get_temp_v3(struct udevice *dev, 777 int chn, int *temp) 778 { 779 int ret; 780 781 ret = tsadc_get_temp_v2(dev, chn, temp); 782 if (!ret) 783 *temp = predict_temp(*temp); 784 785 return ret; 786 } 787 788 static void tsadc_alarm_temp_v2(struct udevice *dev, 789 int chn, int temp) 790 { 791 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 792 struct chip_tsadc_table table = priv->data->table; 793 u32 alarm_value, int_en; 794 795 alarm_value = tsadc_temp_to_code_v2(table, temp); 796 if (alarm_value == table.data_mask) 797 return; 798 799 writel(alarm_value, priv->base + TSADCV2_COMP_INT(chn)); 800 801 int_en = readl(priv->base + TSADCV2_INT_EN); 802 int_en |= TSADCV2_INT_SRC_EN(chn); 803 writel(int_en, priv->base + TSADCV2_INT_EN); 804 } 805 806 static void tsadc_tshut_temp_v2(struct udevice *dev, 807 int chn, int temp) 808 { 809 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 810 struct chip_tsadc_table table = priv->data->table; 811 u32 tshut_value, val; 812 813 tshut_value = tsadc_temp_to_code_v2(table, temp); 814 if (tshut_value == table.data_mask) 815 return; 816 817 writel(tshut_value, priv->base + TSADCV2_COMP_SHUT(chn)); 818 819 /* TSHUT will be valid */ 820 val = readl(priv->base + TSADCV2_AUTO_CON); 821 writel(val | TSADCV2_AUTO_SRC_EN(chn), priv->base + TSADCV2_AUTO_CON); 822 } 823 824 static void tsadc_tshut_mode_v2(struct udevice *dev, int chn, 825 enum tshut_mode mode) 826 { 827 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 828 u32 val; 829 830 val = readl(priv->base + TSADCV2_INT_EN); 831 if (mode == TSHUT_MODE_GPIO) { 832 val &= ~TSADCV2_SHUT_2CRU_SRC_EN(chn); 833 val |= TSADCV2_SHUT_2GPIO_SRC_EN(chn); 834 } else { 835 val &= ~TSADCV2_SHUT_2GPIO_SRC_EN(chn); 836 val |= TSADCV2_SHUT_2CRU_SRC_EN(chn); 837 } 838 839 writel(val, priv->base + TSADCV2_INT_EN); 840 } 841 842 int rockchip_thermal_get_temp(struct udevice *dev, int *temp) 843 { 844 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 845 846 priv->data->tsadc_get_temp(dev, 0, temp); 847 848 return 0; 849 } 850 851 static const struct dm_thermal_ops rockchip_thermal_ops = { 852 .get_temp = rockchip_thermal_get_temp, 853 }; 854 855 static int rockchip_thermal_probe(struct udevice *dev) 856 { 857 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 858 struct rockchip_tsadc_chip *tsadc; 859 int ret, i, shut_temp; 860 861 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 862 ret = clk_set_defaults(dev); 863 if (ret) 864 printf("%s clk_set_defaults failed %d\n", __func__, ret); 865 866 tsadc = (struct rockchip_tsadc_chip *)dev_get_driver_data(dev); 867 priv->data = tsadc; 868 869 priv->tshut_mode = dev_read_u32_default(dev, 870 "rockchip,hw-tshut-mode", 871 -1); 872 if (priv->tshut_mode < 0) 873 priv->tshut_mode = priv->data->tshut_mode; 874 875 priv->tshut_polarity = dev_read_u32_default(dev, 876 "rockchip,hw-tshut-polarity", 877 -1); 878 if (priv->tshut_polarity < 0) 879 priv->tshut_polarity = tsadc->tshut_polarity; 880 881 if (priv->tshut_mode == TSHUT_MODE_GPIO) 882 pinctrl_select_state(dev, "otpout"); 883 else 884 pinctrl_select_state(dev, "gpio"); 885 886 tsadc->tsadc_init(dev); 887 tsadc->irq_ack(dev); 888 889 shut_temp = dev_read_u32_default(dev, "rockchip,hw-tshut-temp", -1); 890 if (shut_temp < 0) 891 shut_temp = 120000; 892 893 for (i = 0; i < tsadc->chn_num; i++) { 894 tsadc->set_alarm_temp(dev, i, tsadc->tshut_temp); 895 tsadc->set_tshut_temp(dev, i, shut_temp); 896 if (priv->tshut_mode == TSHUT_MODE_GPIO) 897 tsadc->set_tshut_mode(dev, i, TSHUT_MODE_GPIO); 898 else 899 tsadc->set_tshut_mode(dev, i, TSHUT_MODE_CRU); 900 } 901 902 tsadc->tsadc_control(dev, true); 903 udelay(1000); 904 905 debug("tsadc probed successfully\n"); 906 907 return 0; 908 } 909 910 static int rockchip_thermal_ofdata_to_platdata(struct udevice *dev) 911 { 912 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 913 914 priv->base = dev_read_addr_ptr(dev); 915 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 916 917 return 0; 918 } 919 920 static const struct rockchip_tsadc_chip rk1808_tsadc_data = { 921 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 922 .chn_num = 1, /* one channel for tsadc */ 923 924 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 925 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 926 .tshut_temp = 95000, 927 928 .tsadc_init = tsadc_init_v2, 929 .tsadc_control = tsadc_control_v3, 930 .tsadc_get_temp = tsadc_get_temp_v2, 931 .irq_ack = tsadc_irq_ack_v3, 932 .set_alarm_temp = tsadc_alarm_temp_v2, 933 .set_tshut_temp = tsadc_tshut_temp_v2, 934 .set_tshut_mode = tsadc_tshut_mode_v2, 935 936 .table = { 937 .id = rk1808_code_table, 938 .length = ARRAY_SIZE(rk1808_code_table), 939 .data_mask = TSADCV2_DATA_MASK, 940 .mode = ADC_INCREMENT, 941 }, 942 }; 943 944 static const struct rockchip_tsadc_chip rk3228_tsadc_data = { 945 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 946 .chn_num = 1, /* one channel for tsadc */ 947 948 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 949 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 950 .tshut_temp = 95000, 951 952 .tsadc_init = tsadc_init_v2, 953 .tsadc_control = tsadc_control_v3, 954 .tsadc_get_temp = tsadc_get_temp_v2, 955 .irq_ack = tsadc_irq_ack_v3, 956 .set_alarm_temp = tsadc_alarm_temp_v2, 957 .set_tshut_temp = tsadc_tshut_temp_v2, 958 .set_tshut_mode = tsadc_tshut_mode_v2, 959 960 .table = { 961 .id = rk3228_code_table, 962 .length = ARRAY_SIZE(rk3228_code_table), 963 .data_mask = TSADCV3_DATA_MASK, 964 .mode = ADC_INCREMENT, 965 }, 966 }; 967 968 static const struct rockchip_tsadc_chip rk3288_tsadc_data = { 969 .chn_id[SENSOR_CPU] = 1, /* cpu sensor is channel 1 */ 970 .chn_id[SENSOR_GPU] = 2, /* gpu sensor is channel 2 */ 971 .chn_num = 2, /* two channels for tsadc */ 972 973 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 974 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 975 .tshut_temp = 95000, 976 977 .tsadc_init = tsadc_init_v2, 978 .tsadc_control = tsadc_control_v2, 979 .tsadc_get_temp = tsadc_get_temp_v3, 980 .irq_ack = tsadc_irq_ack_v2, 981 .set_alarm_temp = tsadc_alarm_temp_v2, 982 .set_tshut_temp = tsadc_tshut_temp_v2, 983 .set_tshut_mode = tsadc_tshut_mode_v2, 984 985 .table = { 986 .id = rk3288_code_table, 987 .length = ARRAY_SIZE(rk3288_code_table), 988 .data_mask = TSADCV2_DATA_MASK, 989 .mode = ADC_DECREMENT, 990 }, 991 }; 992 993 static const struct rockchip_tsadc_chip rk3308_tsadc_data = { 994 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 995 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 996 .chn_num = 2, /* 2 channels for tsadc */ 997 998 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ 999 .tshut_temp = 95000, 1000 1001 .tsadc_init = tsadc_init_v4, 1002 .tsadc_control = tsadc_control_v3, 1003 .tsadc_get_temp = tsadc_get_temp_v2, 1004 .irq_ack = tsadc_irq_ack_v3, 1005 .set_alarm_temp = tsadc_alarm_temp_v2, 1006 .set_tshut_temp = tsadc_tshut_temp_v2, 1007 .set_tshut_mode = tsadc_tshut_mode_v2, 1008 1009 .table = { 1010 .id = rk3328_code_table, 1011 .length = ARRAY_SIZE(rk3328_code_table), 1012 .data_mask = TSADCV2_DATA_MASK, 1013 .mode = ADC_INCREMENT, 1014 }, 1015 }; 1016 1017 static const struct rockchip_tsadc_chip px30_tsadc_data = { 1018 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1019 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1020 .chn_num = 2, /* 2 channels for tsadc */ 1021 1022 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ 1023 .tshut_temp = 95000, 1024 1025 .tsadc_init = tsadc_init_v4, 1026 .tsadc_control = tsadc_control_v3, 1027 .tsadc_get_temp = tsadc_get_temp_v2, 1028 .irq_ack = tsadc_irq_ack_v3, 1029 .set_alarm_temp = tsadc_alarm_temp_v2, 1030 .set_tshut_temp = tsadc_tshut_temp_v2, 1031 .set_tshut_mode = tsadc_tshut_mode_v2, 1032 1033 .table = { 1034 .id = rk3328_code_table, 1035 .length = ARRAY_SIZE(rk3328_code_table), 1036 .data_mask = TSADCV2_DATA_MASK, 1037 .mode = ADC_INCREMENT, 1038 }, 1039 }; 1040 1041 static const struct rockchip_tsadc_chip rk3328_tsadc_data = { 1042 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1043 .chn_num = 1, /* one channels for tsadc */ 1044 1045 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ 1046 .tshut_temp = 95000, 1047 1048 .tsadc_init = tsadc_init_v2, 1049 .tsadc_control = tsadc_control_v3, 1050 .tsadc_get_temp = tsadc_get_temp_v2, 1051 .irq_ack = tsadc_irq_ack_v3, 1052 .set_alarm_temp = tsadc_alarm_temp_v2, 1053 .set_tshut_temp = tsadc_tshut_temp_v2, 1054 .set_tshut_mode = tsadc_tshut_mode_v2, 1055 1056 .table = { 1057 .id = rk3328_code_table, 1058 .length = ARRAY_SIZE(rk3328_code_table), 1059 .data_mask = TSADCV2_DATA_MASK, 1060 .mode = ADC_INCREMENT, 1061 }, 1062 }; 1063 1064 static const struct rockchip_tsadc_chip rk3366_tsadc_data = { 1065 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1066 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1067 .chn_num = 2, /* two channels for tsadc */ 1068 1069 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1070 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1071 .tshut_temp = 95000, 1072 1073 .tsadc_init = tsadc_init_v3, 1074 .tsadc_control = tsadc_control_v3, 1075 .tsadc_get_temp = tsadc_get_temp_v2, 1076 .irq_ack = tsadc_irq_ack_v3, 1077 .set_alarm_temp = tsadc_alarm_temp_v2, 1078 .set_tshut_temp = tsadc_tshut_temp_v2, 1079 .set_tshut_mode = tsadc_tshut_mode_v2, 1080 1081 .table = { 1082 .id = rk3228_code_table, 1083 .length = ARRAY_SIZE(rk3228_code_table), 1084 .data_mask = TSADCV3_DATA_MASK, 1085 .mode = ADC_INCREMENT, 1086 }, 1087 }; 1088 1089 static const struct rockchip_tsadc_chip rk3368_tsadc_data = { 1090 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1091 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1092 .chn_num = 2, /* two channels for tsadc */ 1093 1094 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1095 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1096 .tshut_temp = 95000, 1097 1098 .tsadc_init = tsadc_init_v2, 1099 .tsadc_control = tsadc_control_v2, 1100 .tsadc_get_temp = tsadc_get_temp_v2, 1101 .irq_ack = tsadc_irq_ack_v2, 1102 .set_alarm_temp = tsadc_alarm_temp_v2, 1103 .set_tshut_temp = tsadc_tshut_temp_v2, 1104 .set_tshut_mode = tsadc_tshut_mode_v2, 1105 1106 .table = { 1107 .id = rk3368_code_table, 1108 .length = ARRAY_SIZE(rk3368_code_table), 1109 .data_mask = TSADCV3_DATA_MASK, 1110 .mode = ADC_INCREMENT, 1111 }, 1112 }; 1113 1114 static const struct rockchip_tsadc_chip rk3399_tsadc_data = { 1115 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1116 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1117 .chn_num = 2, /* two channels for tsadc */ 1118 1119 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1120 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1121 .tshut_temp = 95000, 1122 1123 .tsadc_init = tsadc_init_v3, 1124 .tsadc_control = tsadc_control_v3, 1125 .tsadc_get_temp = tsadc_get_temp_v2, 1126 .irq_ack = tsadc_irq_ack_v3, 1127 .set_alarm_temp = tsadc_alarm_temp_v2, 1128 .set_tshut_temp = tsadc_tshut_temp_v2, 1129 .set_tshut_mode = tsadc_tshut_mode_v2, 1130 1131 .table = { 1132 .id = rk3399_code_table, 1133 .length = ARRAY_SIZE(rk3399_code_table), 1134 .data_mask = TSADCV3_DATA_MASK, 1135 .mode = ADC_INCREMENT, 1136 }, 1137 }; 1138 1139 static const struct rockchip_tsadc_chip rk3568_tsadc_data = { 1140 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1141 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1142 .chn_num = 2, /* two channels for tsadc */ 1143 1144 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1145 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1146 .tshut_temp = 95000, 1147 1148 .tsadc_init = tsadc_init_v7, 1149 .tsadc_control = tsadc_control_v3, 1150 .tsadc_get_temp = tsadc_get_temp_v2, 1151 .irq_ack = tsadc_irq_ack_v3, 1152 .set_alarm_temp = tsadc_alarm_temp_v2, 1153 .set_tshut_temp = tsadc_tshut_temp_v2, 1154 .set_tshut_mode = tsadc_tshut_mode_v2, 1155 1156 .table = { 1157 .id = rk3568_code_table, 1158 .length = ARRAY_SIZE(rk3568_code_table), 1159 .data_mask = TSADCV2_DATA_MASK, 1160 .mode = ADC_INCREMENT, 1161 }, 1162 }; 1163 1164 static const struct udevice_id rockchip_thermal_match[] = { 1165 { 1166 .compatible = "rockchip,px30-tsadc", 1167 .data = (ulong)&px30_tsadc_data, 1168 }, 1169 { 1170 .compatible = "rockchip,rk1808-tsadc", 1171 .data = (ulong)&rk1808_tsadc_data, 1172 }, 1173 { 1174 .compatible = "rockchip,rk3228-tsadc", 1175 .data = (ulong)&rk3228_tsadc_data, 1176 }, 1177 { 1178 .compatible = "rockchip,rk3288-tsadc", 1179 .data = (ulong)&rk3288_tsadc_data, 1180 }, 1181 { 1182 .compatible = "rockchip,rk3308-tsadc", 1183 .data = (ulong)&rk3308_tsadc_data, 1184 }, 1185 { 1186 .compatible = "rockchip,rk3328-tsadc", 1187 .data = (ulong)&rk3328_tsadc_data, 1188 }, 1189 { 1190 .compatible = "rockchip,rk3366-tsadc", 1191 .data = (ulong)&rk3366_tsadc_data, 1192 }, 1193 { 1194 .compatible = "rockchip,rk3368-tsadc", 1195 .data = (ulong)&rk3368_tsadc_data, 1196 }, 1197 { 1198 .compatible = "rockchip,rk3399-tsadc", 1199 .data = (ulong)&rk3399_tsadc_data, 1200 }, 1201 { 1202 .compatible = "rockchip,rk3568-tsadc", 1203 .data = (ulong)&rk3568_tsadc_data, 1204 }, 1205 { /* end */ }, 1206 }; 1207 1208 U_BOOT_DRIVER(rockchip_thermal) = { 1209 .name = "rockchip_thermal", 1210 .id = UCLASS_THERMAL, 1211 .of_match = rockchip_thermal_match, 1212 .priv_auto_alloc_size = sizeof(struct rockchip_thermal_priv), 1213 .ofdata_to_platdata = rockchip_thermal_ofdata_to_platdata, 1214 .ops = &rockchip_thermal_ops, 1215 .probe = rockchip_thermal_probe, 1216 }; 1217