1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6 #include <common.h> 7 #include <bitfield.h> 8 #include <thermal.h> 9 #include <dm.h> 10 #include <dm/pinctrl.h> 11 #include <div64.h> 12 #include <errno.h> 13 #include <syscon.h> 14 #include <asm/arch/clock.h> 15 #include <asm/arch/hardware.h> 16 #include <asm/io.h> 17 #include <dm/lists.h> 18 #include <clk.h> 19 #include <clk-uclass.h> 20 #include <reset.h> 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 /** 25 * If the temperature over a period of time High, 26 * the resulting TSHUT gave CRU module,let it reset the entire chip, 27 * or via GPIO give PMIC. 28 */ 29 enum tshut_mode { 30 TSHUT_MODE_CRU = 0, 31 TSHUT_MODE_GPIO, 32 }; 33 34 /** 35 * The system Temperature Sensors tshut(tshut) polarity 36 * the bit 8 is tshut polarity. 37 * 0: low active, 1: high active 38 */ 39 enum tshut_polarity { 40 TSHUT_LOW_ACTIVE = 0, 41 TSHUT_HIGH_ACTIVE, 42 }; 43 44 /** 45 * The conversion table has the adc value and temperature. 46 * ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table) 47 * ADC_INCREMENT: the adc value is incremental.(e.g. rk3368_code_table) 48 */ 49 enum adc_sort_mode { 50 ADC_DECREMENT = 0, 51 ADC_INCREMENT, 52 }; 53 54 #define SOC_MAX_SENSORS 2 55 56 #define TSADCV2_USER_CON 0x00 57 #define TSADCV2_AUTO_CON 0x04 58 #define TSADCV2_INT_EN 0x08 59 #define TSADCV2_INT_PD 0x0c 60 #define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04) 61 #define TSADCV2_COMP_INT(chn) (0x30 + (chn) * 0x04) 62 #define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04) 63 #define TSADCV2_HIGHT_INT_DEBOUNCE 0x60 64 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64 65 #define TSADCV2_AUTO_PERIOD 0x68 66 #define TSADCV2_AUTO_PERIOD_HT 0x6c 67 68 #define TSADCV2_AUTO_EN BIT(0) 69 #define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn)) 70 #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8) 71 72 #define TSADCV3_AUTO_Q_SEL_EN BIT(1) 73 74 #define TSADCV2_INT_SRC_EN(chn) BIT(chn) 75 #define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn)) 76 #define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn)) 77 78 #define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8) 79 #define TSADCV3_INT_PD_CLEAR_MASK ~BIT(16) 80 81 #define TSADCV2_DATA_MASK 0xfff 82 #define TSADCV3_DATA_MASK 0x3ff 83 84 #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4 85 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4 86 #define TSADCV2_AUTO_PERIOD_TIME 250 87 #define TSADCV2_AUTO_PERIOD_HT_TIME 50 88 #define TSADCV3_AUTO_PERIOD_TIME 1875 89 #define TSADCV3_AUTO_PERIOD_HT_TIME 1875 90 91 #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */ 92 93 #define GRF_SARADC_TESTBIT 0x0e644 94 #define GRF_TSADC_TESTBIT_L 0x0e648 95 #define GRF_TSADC_TESTBIT_H 0x0e64c 96 97 #define PX30_GRF_SOC_CON2 0x0408 98 99 #define GRF_SARADC_TESTBIT_ON (0x10001 << 2) 100 #define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2) 101 #define GRF_TSADC_VCM_EN_L (0x10001 << 7) 102 #define GRF_TSADC_VCM_EN_H (0x10001 << 7) 103 104 #define GRF_CON_TSADC_CH_INV (0x10001 << 1) 105 106 #define MIN_TEMP (-40000) 107 #define LOWEST_TEMP (-273000) 108 #define MAX_TEMP (125000) 109 #define MAX_ENV_TEMP (85000) 110 111 #define BASE (1024) 112 #define BASE_SHIFT (10) 113 #define START_DEBOUNCE_COUNT (100) 114 #define HIGHER_DEBOUNCE_TEMP (30000) 115 #define LOWER_DEBOUNCE_TEMP (15000) 116 117 /** 118 * struct tsadc_table - hold information about code and temp mapping 119 * @code: raw code from tsadc ip 120 * @temp: the mapping temperature 121 */ 122 123 struct tsadc_table { 124 unsigned long code; 125 int temp; 126 }; 127 128 struct chip_tsadc_table { 129 const struct tsadc_table *id; 130 unsigned int length; 131 u32 data_mask; 132 enum adc_sort_mode mode; 133 }; 134 135 enum sensor_id { 136 SENSOR_CPU = 0, 137 SENSOR_GPU, 138 }; 139 140 struct rockchip_tsadc_chip { 141 /* The sensor id of chip correspond to the ADC channel */ 142 int chn_id[SOC_MAX_SENSORS]; 143 int chn_num; 144 fdt_addr_t base; 145 fdt_addr_t grf; 146 147 /* The hardware-controlled tshut property */ 148 int tshut_temp; 149 enum tshut_mode tshut_mode; 150 enum tshut_polarity tshut_polarity; 151 152 void (*tsadc_control)(struct udevice *dev, bool enable); 153 void (*tsadc_init)(struct udevice *dev); 154 int (*tsadc_get_temp)(struct udevice *dev, int chn, 155 int *temp); 156 void (*irq_ack)(struct udevice *dev); 157 void (*set_alarm_temp)(struct udevice *dev, 158 int chn, int temp); 159 void (*set_tshut_temp)(struct udevice *dev, 160 int chn, int temp); 161 void (*set_tshut_mode)(struct udevice *dev, int chn, enum tshut_mode m); 162 struct chip_tsadc_table table; 163 }; 164 165 struct rockchip_thermal_priv { 166 void *base; 167 void *grf; 168 enum tshut_mode tshut_mode; 169 enum tshut_polarity tshut_polarity; 170 const struct rockchip_tsadc_chip *data; 171 }; 172 173 static const struct tsadc_table rk1808_code_table[] = { 174 {0, -40000}, 175 {3455, -40000}, 176 {3463, -35000}, 177 {3471, -30000}, 178 {3479, -25000}, 179 {3487, -20000}, 180 {3495, -15000}, 181 {3503, -10000}, 182 {3511, -5000}, 183 {3519, 0}, 184 {3527, 5000}, 185 {3535, 10000}, 186 {3543, 15000}, 187 {3551, 20000}, 188 {3559, 25000}, 189 {3567, 30000}, 190 {3576, 35000}, 191 {3584, 40000}, 192 {3592, 45000}, 193 {3600, 50000}, 194 {3609, 55000}, 195 {3617, 60000}, 196 {3625, 65000}, 197 {3633, 70000}, 198 {3642, 75000}, 199 {3650, 80000}, 200 {3659, 85000}, 201 {3667, 90000}, 202 {3675, 95000}, 203 {3684, 100000}, 204 {3692, 105000}, 205 {3701, 110000}, 206 {3709, 115000}, 207 {3718, 120000}, 208 {3726, 125000}, 209 {TSADCV2_DATA_MASK, 125000}, 210 }; 211 212 static const struct tsadc_table rk3228_code_table[] = { 213 {0, -40000}, 214 {588, -40000}, 215 {593, -35000}, 216 {598, -30000}, 217 {603, -25000}, 218 {608, -20000}, 219 {613, -15000}, 220 {618, -10000}, 221 {623, -5000}, 222 {629, 0}, 223 {634, 5000}, 224 {639, 10000}, 225 {644, 15000}, 226 {649, 20000}, 227 {654, 25000}, 228 {660, 30000}, 229 {665, 35000}, 230 {670, 40000}, 231 {675, 45000}, 232 {681, 50000}, 233 {686, 55000}, 234 {691, 60000}, 235 {696, 65000}, 236 {702, 70000}, 237 {707, 75000}, 238 {712, 80000}, 239 {717, 85000}, 240 {723, 90000}, 241 {728, 95000}, 242 {733, 100000}, 243 {738, 105000}, 244 {744, 110000}, 245 {749, 115000}, 246 {754, 120000}, 247 {760, 125000}, 248 {TSADCV2_DATA_MASK, 125000}, 249 }; 250 251 static const struct tsadc_table rk3288_code_table[] = { 252 {TSADCV2_DATA_MASK, -40000}, 253 {3800, -40000}, 254 {3792, -35000}, 255 {3783, -30000}, 256 {3774, -25000}, 257 {3765, -20000}, 258 {3756, -15000}, 259 {3747, -10000}, 260 {3737, -5000}, 261 {3728, 0}, 262 {3718, 5000}, 263 {3708, 10000}, 264 {3698, 15000}, 265 {3688, 20000}, 266 {3678, 25000}, 267 {3667, 30000}, 268 {3656, 35000}, 269 {3645, 40000}, 270 {3634, 45000}, 271 {3623, 50000}, 272 {3611, 55000}, 273 {3600, 60000}, 274 {3588, 65000}, 275 {3575, 70000}, 276 {3563, 75000}, 277 {3550, 80000}, 278 {3537, 85000}, 279 {3524, 90000}, 280 {3510, 95000}, 281 {3496, 100000}, 282 {3482, 105000}, 283 {3467, 110000}, 284 {3452, 115000}, 285 {3437, 120000}, 286 {3421, 125000}, 287 }; 288 289 static const struct tsadc_table rk3328_code_table[] = { 290 {0, -40000}, 291 {296, -40000}, 292 {304, -35000}, 293 {313, -30000}, 294 {331, -20000}, 295 {340, -15000}, 296 {349, -10000}, 297 {359, -5000}, 298 {368, 0}, 299 {378, 5000}, 300 {388, 10000}, 301 {398, 15000}, 302 {408, 20000}, 303 {418, 25000}, 304 {429, 30000}, 305 {440, 35000}, 306 {451, 40000}, 307 {462, 45000}, 308 {473, 50000}, 309 {485, 55000}, 310 {496, 60000}, 311 {508, 65000}, 312 {521, 70000}, 313 {533, 75000}, 314 {546, 80000}, 315 {559, 85000}, 316 {572, 90000}, 317 {586, 95000}, 318 {600, 100000}, 319 {614, 105000}, 320 {629, 110000}, 321 {644, 115000}, 322 {659, 120000}, 323 {675, 125000}, 324 {TSADCV2_DATA_MASK, 125000}, 325 }; 326 327 static const struct tsadc_table rk3368_code_table[] = { 328 {0, -40000}, 329 {106, -40000}, 330 {108, -35000}, 331 {110, -30000}, 332 {112, -25000}, 333 {114, -20000}, 334 {116, -15000}, 335 {118, -10000}, 336 {120, -5000}, 337 {122, 0}, 338 {124, 5000}, 339 {126, 10000}, 340 {128, 15000}, 341 {130, 20000}, 342 {132, 25000}, 343 {134, 30000}, 344 {136, 35000}, 345 {138, 40000}, 346 {140, 45000}, 347 {142, 50000}, 348 {144, 55000}, 349 {146, 60000}, 350 {148, 65000}, 351 {150, 70000}, 352 {152, 75000}, 353 {154, 80000}, 354 {156, 85000}, 355 {158, 90000}, 356 {160, 95000}, 357 {162, 100000}, 358 {163, 105000}, 359 {165, 110000}, 360 {167, 115000}, 361 {169, 120000}, 362 {171, 125000}, 363 {TSADCV3_DATA_MASK, 125000}, 364 }; 365 366 static const struct tsadc_table rk3399_code_table[] = { 367 {0, -40000}, 368 {402, -40000}, 369 {410, -35000}, 370 {419, -30000}, 371 {427, -25000}, 372 {436, -20000}, 373 {444, -15000}, 374 {453, -10000}, 375 {461, -5000}, 376 {470, 0}, 377 {478, 5000}, 378 {487, 10000}, 379 {496, 15000}, 380 {504, 20000}, 381 {513, 25000}, 382 {521, 30000}, 383 {530, 35000}, 384 {538, 40000}, 385 {547, 45000}, 386 {555, 50000}, 387 {564, 55000}, 388 {573, 60000}, 389 {581, 65000}, 390 {590, 70000}, 391 {599, 75000}, 392 {607, 80000}, 393 {616, 85000}, 394 {624, 90000}, 395 {633, 95000}, 396 {642, 100000}, 397 {650, 105000}, 398 {659, 110000}, 399 {668, 115000}, 400 {677, 120000}, 401 {685, 125000}, 402 {TSADCV3_DATA_MASK, 125000}, 403 }; 404 405 /* 406 * Struct used for matching a device 407 */ 408 struct of_device_id { 409 char compatible[32]; 410 const void *data; 411 }; 412 413 static int tsadc_code_to_temp(struct chip_tsadc_table *table, u32 code, 414 int *temp) 415 { 416 unsigned int low = 1; 417 unsigned int high = table->length - 1; 418 unsigned int mid = (low + high) / 2; 419 unsigned int num; 420 unsigned long denom; 421 422 switch (table->mode) { 423 case ADC_DECREMENT: 424 code &= table->data_mask; 425 if (code < table->id[high].code) 426 return -EAGAIN; /* Incorrect reading */ 427 428 while (low <= high) { 429 if (code >= table->id[mid].code && 430 code < table->id[mid - 1].code) 431 break; 432 else if (code < table->id[mid].code) 433 low = mid + 1; 434 else 435 high = mid - 1; 436 437 mid = (low + high) / 2; 438 } 439 break; 440 case ADC_INCREMENT: 441 code &= table->data_mask; 442 if (code < table->id[low].code) 443 return -EAGAIN; /* Incorrect reading */ 444 445 while (low <= high) { 446 if (code <= table->id[mid].code && 447 code > table->id[mid - 1].code) 448 break; 449 else if (code > table->id[mid].code) 450 low = mid + 1; 451 else 452 high = mid - 1; 453 454 mid = (low + high) / 2; 455 } 456 break; 457 default: 458 printf("%s: Invalid the conversion table mode=%d\n", 459 __func__, table->mode); 460 return -EINVAL; 461 } 462 463 /* 464 * The 5C granularity provided by the table is too much. Let's 465 * assume that the relationship between sensor readings and 466 * temperature between 2 table entries is linear and interpolate 467 * to produce less granular result. 468 */ 469 num = table->id[mid].temp - table->id[mid - 1].temp; 470 num *= abs(table->id[mid - 1].code - code); 471 denom = abs(table->id[mid - 1].code - table->id[mid].code); 472 *temp = table->id[mid - 1].temp + (num / denom); 473 474 return 0; 475 } 476 477 static u32 tsadc_temp_to_code_v2(struct chip_tsadc_table table, 478 int temp) 479 { 480 int high, low, mid; 481 u32 error = table.data_mask; 482 483 low = 0; 484 high = table.length - 1; 485 mid = (high + low) / 2; 486 487 /* Return mask code data when the temp is over table range */ 488 if (temp < table.id[low].temp || temp > table.id[high].temp) 489 goto exit; 490 491 while (low <= high) { 492 if (temp == table.id[mid].temp) 493 return table.id[mid].code; 494 else if (temp < table.id[mid].temp) 495 high = mid - 1; 496 else 497 low = mid + 1; 498 mid = (low + high) / 2; 499 } 500 501 exit: 502 pr_err("%s: Invalid conversion table: code=%d, temperature=%d\n", 503 __func__, error, temp); 504 505 return error; 506 } 507 508 static void tsadc_irq_ack_v2(struct udevice *dev) 509 { 510 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 511 u32 val; 512 513 val = readl(priv->base + TSADCV2_INT_PD); 514 writel(val & TSADCV2_INT_PD_CLEAR_MASK, priv->base + TSADCV2_INT_PD); 515 } 516 517 static void tsadc_irq_ack_v3(struct udevice *dev) 518 { 519 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 520 u32 val; 521 522 val = readl(priv->base + TSADCV2_INT_PD); 523 writel(val & TSADCV3_INT_PD_CLEAR_MASK, priv->base + TSADCV2_INT_PD); 524 } 525 526 static void tsadc_control_v3(struct udevice *dev, bool enable) 527 { 528 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 529 u32 val; 530 531 val = readl(priv->base + TSADCV2_AUTO_CON); 532 if (enable) 533 val |= TSADCV2_AUTO_EN | TSADCV3_AUTO_Q_SEL_EN; 534 else 535 val &= ~TSADCV2_AUTO_EN; 536 537 writel(val, priv->base + TSADCV2_AUTO_CON); 538 } 539 540 static void tsadc_control_v2(struct udevice *dev, bool enable) 541 { 542 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 543 u32 val; 544 545 val = readl(priv->base + TSADCV2_AUTO_CON); 546 if (enable) 547 val |= TSADCV2_AUTO_EN; 548 else 549 val &= ~TSADCV2_AUTO_EN; 550 551 writel(val, priv->base + TSADCV2_AUTO_CON); 552 } 553 554 static void tsadc_init_v2(struct udevice *dev) 555 { 556 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 557 558 writel(TSADCV2_AUTO_PERIOD_TIME, 559 priv->base + TSADCV2_AUTO_PERIOD); 560 writel(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, 561 priv->base + TSADCV2_HIGHT_INT_DEBOUNCE); 562 writel(TSADCV2_AUTO_PERIOD_HT_TIME, 563 priv->base + TSADCV2_AUTO_PERIOD_HT); 564 writel(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, 565 priv->base + TSADCV2_HIGHT_TSHUT_DEBOUNCE); 566 567 if (priv->tshut_polarity == TSHUT_HIGH_ACTIVE) 568 writel(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 569 priv->base + TSADCV2_AUTO_CON); 570 else 571 writel(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 572 priv->base + TSADCV2_AUTO_CON); 573 } 574 575 static void tsadc_init_v3(struct udevice *dev) 576 { 577 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 578 579 if (!IS_ERR(priv->grf)) { 580 writel(GRF_TSADC_VCM_EN_L, priv->grf + GRF_TSADC_TESTBIT_L); 581 writel(GRF_TSADC_VCM_EN_H, priv->grf + GRF_TSADC_TESTBIT_H); 582 583 udelay(100);/* The spec note says at least 15 us */ 584 writel(GRF_SARADC_TESTBIT_ON, priv->grf + GRF_SARADC_TESTBIT); 585 writel(GRF_TSADC_TESTBIT_H_ON, priv->grf + GRF_TSADC_TESTBIT_H); 586 udelay(200);/* The spec note says at least 90 us */ 587 } 588 tsadc_init_v2(dev); 589 } 590 591 static void __maybe_unused tsadc_init_v5(struct udevice *dev) 592 { 593 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 594 595 /* Set interleave value to workround ic time sync issue */ 596 writel(TSADCV2_USER_INTER_PD_SOC, priv->base + 597 TSADCV2_USER_CON); 598 tsadc_init_v2(dev); 599 } 600 601 static void tsadc_init_v4(struct udevice *dev) 602 { 603 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 604 605 tsadc_init_v2(dev); 606 if (!IS_ERR(priv->grf)) 607 writel(GRF_CON_TSADC_CH_INV, priv->grf + PX30_GRF_SOC_CON2); 608 } 609 610 static int tsadc_get_temp_v2(struct udevice *dev, 611 int chn, int *temp) 612 { 613 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 614 struct chip_tsadc_table table = priv->data->table; 615 u32 val; 616 617 val = readl(priv->base + TSADCV2_DATA(chn)); 618 619 return tsadc_code_to_temp(&table, val, temp); 620 } 621 622 static int predict_temp(int temp) 623 { 624 /* 625 * The deviation of prediction. the temperature will not change rapidly, 626 * so this cov_q is small 627 */ 628 int cov_q = 18; 629 /* 630 * The deviation of tsadc's reading, deviation of tsadc is very big when 631 * abnormal temperature is get 632 */ 633 int cov_r = 542; 634 635 int gain; 636 int temp_mid; 637 int temp_now; 638 int prob_mid; 639 int prob_now; 640 static int temp_last = LOWEST_TEMP; 641 static int prob_last = 160; 642 static int bounding_cnt; 643 644 /* 645 * init temp_last with a more suitable value, which mostly equals to 646 * temp reading from tsadc, but not higher than MAX_ENV_TEMP. If the 647 * temp is higher than MAX_ENV_TEMP, it is assumed to be abnormal 648 * value and temp_last is adjusted to MAX_ENV_TEMP. 649 */ 650 if (temp_last == LOWEST_TEMP) 651 temp_last = min(temp, MAX_ENV_TEMP); 652 653 /* 654 * Before START_DEBOUNCE_COUNT's samples of temperature, we consider 655 * tsadc is stable, i.e. after that, the temperature may be not stable 656 * and may have abnormal reading, so we set a bounding temperature. If 657 * the reading from tsadc is too big, we set the delta temperature of 658 * DEBOUNCE_TEMP/3 comparing to the last temperature. 659 */ 660 661 if (bounding_cnt++ > START_DEBOUNCE_COUNT) { 662 bounding_cnt = START_DEBOUNCE_COUNT; 663 if (temp - temp_last > HIGHER_DEBOUNCE_TEMP) 664 temp = temp_last + HIGHER_DEBOUNCE_TEMP / 3; 665 if (temp_last - temp > LOWER_DEBOUNCE_TEMP) 666 temp = temp_last - LOWER_DEBOUNCE_TEMP / 3; 667 } 668 669 temp_mid = temp_last; 670 671 /* calculate the probability of this time's prediction */ 672 prob_mid = prob_last + cov_q; 673 674 /* calculate the Kalman Gain */ 675 gain = (prob_mid * BASE) / (prob_mid + cov_r); 676 677 /* calculate the prediction of temperature */ 678 temp_now = (temp_mid * BASE + gain * (temp - temp_mid)) >> BASE_SHIFT; 679 680 /* 681 * Base on this time's Kalman Gain, ajust our probability of prediction 682 * for next time calculation 683 */ 684 prob_now = ((BASE - gain) * prob_mid) >> BASE_SHIFT; 685 686 prob_last = prob_now; 687 temp_last = temp_now; 688 689 return temp_last; 690 } 691 692 static int tsadc_get_temp_v3(struct udevice *dev, 693 int chn, int *temp) 694 { 695 int ret; 696 697 ret = tsadc_get_temp_v2(dev, chn, temp); 698 if (!ret) 699 *temp = predict_temp(*temp); 700 701 return ret; 702 } 703 704 static void tsadc_alarm_temp_v2(struct udevice *dev, 705 int chn, int temp) 706 { 707 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 708 struct chip_tsadc_table table = priv->data->table; 709 u32 alarm_value, int_en; 710 711 alarm_value = tsadc_temp_to_code_v2(table, temp); 712 if (alarm_value == table.data_mask) 713 return; 714 715 writel(alarm_value, priv->base + TSADCV2_COMP_INT(chn)); 716 717 int_en = readl(priv->base + TSADCV2_INT_EN); 718 int_en |= TSADCV2_INT_SRC_EN(chn); 719 writel(int_en, priv->base + TSADCV2_INT_EN); 720 } 721 722 static void tsadc_tshut_temp_v2(struct udevice *dev, 723 int chn, int temp) 724 { 725 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 726 struct chip_tsadc_table table = priv->data->table; 727 u32 tshut_value, val; 728 729 tshut_value = tsadc_temp_to_code_v2(table, temp); 730 if (tshut_value == table.data_mask) 731 return; 732 733 writel(tshut_value, priv->base + TSADCV2_COMP_SHUT(chn)); 734 735 /* TSHUT will be valid */ 736 val = readl(priv->base + TSADCV2_AUTO_CON); 737 writel(val | TSADCV2_AUTO_SRC_EN(chn), priv->base + TSADCV2_AUTO_CON); 738 } 739 740 static void tsadc_tshut_mode_v2(struct udevice *dev, int chn, 741 enum tshut_mode mode) 742 { 743 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 744 u32 val; 745 746 val = readl(priv->base + TSADCV2_INT_EN); 747 if (mode == TSHUT_MODE_GPIO) { 748 val &= ~TSADCV2_SHUT_2CRU_SRC_EN(chn); 749 val |= TSADCV2_SHUT_2GPIO_SRC_EN(chn); 750 } else { 751 val &= ~TSADCV2_SHUT_2GPIO_SRC_EN(chn); 752 val |= TSADCV2_SHUT_2CRU_SRC_EN(chn); 753 } 754 755 writel(val, priv->base + TSADCV2_INT_EN); 756 } 757 758 int rockchip_thermal_get_temp(struct udevice *dev, int *temp) 759 { 760 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 761 762 priv->data->tsadc_get_temp(dev, 0, temp); 763 764 return 0; 765 } 766 767 static const struct dm_thermal_ops rockchip_thermal_ops = { 768 .get_temp = rockchip_thermal_get_temp, 769 }; 770 771 static int rockchip_thermal_probe(struct udevice *dev) 772 { 773 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 774 struct rockchip_tsadc_chip *tsadc; 775 int ret, i, shut_temp; 776 777 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 778 ret = clk_set_defaults(dev); 779 if (ret) 780 printf("%s clk_set_defaults failed %d\n", __func__, ret); 781 782 tsadc = (struct rockchip_tsadc_chip *)dev_get_driver_data(dev); 783 priv->data = tsadc; 784 785 priv->tshut_mode = dev_read_u32_default(dev, 786 "rockchip,hw-tshut-mode", 787 -1); 788 if (priv->tshut_mode < 0) 789 priv->tshut_mode = priv->data->tshut_mode; 790 791 priv->tshut_polarity = dev_read_u32_default(dev, 792 "rockchip,hw-tshut-polarity", 793 -1); 794 if (priv->tshut_polarity < 0) 795 priv->tshut_polarity = tsadc->tshut_polarity; 796 797 if (priv->tshut_mode == TSHUT_MODE_GPIO) 798 pinctrl_select_state(dev, "otpout"); 799 else 800 pinctrl_select_state(dev, "gpio"); 801 802 tsadc->tsadc_init(dev); 803 tsadc->irq_ack(dev); 804 805 shut_temp = dev_read_u32_default(dev, "rockchip,hw-tshut-temp", -1); 806 if (shut_temp < 0) 807 shut_temp = 120000; 808 809 for (i = 0; i < tsadc->chn_num; i++) { 810 tsadc->set_alarm_temp(dev, i, tsadc->tshut_temp); 811 tsadc->set_tshut_temp(dev, i, shut_temp); 812 if (priv->tshut_mode == TSHUT_MODE_GPIO) 813 tsadc->set_tshut_mode(dev, i, TSHUT_MODE_GPIO); 814 else 815 tsadc->set_tshut_mode(dev, i, TSHUT_MODE_CRU); 816 } 817 818 tsadc->tsadc_control(dev, true); 819 udelay(1000); 820 821 debug("tsadc probed successfully\n"); 822 823 return 0; 824 } 825 826 static int rockchip_thermal_ofdata_to_platdata(struct udevice *dev) 827 { 828 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 829 830 priv->base = dev_read_addr_ptr(dev); 831 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 832 833 return 0; 834 } 835 836 static const struct rockchip_tsadc_chip rk1808_tsadc_data = { 837 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 838 .chn_num = 1, /* one channel for tsadc */ 839 840 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 841 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 842 .tshut_temp = 95000, 843 844 .tsadc_init = tsadc_init_v2, 845 .tsadc_control = tsadc_control_v3, 846 .tsadc_get_temp = tsadc_get_temp_v2, 847 .irq_ack = tsadc_irq_ack_v3, 848 .set_alarm_temp = tsadc_alarm_temp_v2, 849 .set_tshut_temp = tsadc_tshut_temp_v2, 850 .set_tshut_mode = tsadc_tshut_mode_v2, 851 852 .table = { 853 .id = rk1808_code_table, 854 .length = ARRAY_SIZE(rk1808_code_table), 855 .data_mask = TSADCV2_DATA_MASK, 856 .mode = ADC_INCREMENT, 857 }, 858 }; 859 860 static const struct rockchip_tsadc_chip rk3228_tsadc_data = { 861 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 862 .chn_num = 1, /* one channel for tsadc */ 863 864 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 865 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 866 .tshut_temp = 95000, 867 868 .tsadc_init = tsadc_init_v2, 869 .tsadc_control = tsadc_control_v3, 870 .tsadc_get_temp = tsadc_get_temp_v2, 871 .irq_ack = tsadc_irq_ack_v3, 872 .set_alarm_temp = tsadc_alarm_temp_v2, 873 .set_tshut_temp = tsadc_tshut_temp_v2, 874 .set_tshut_mode = tsadc_tshut_mode_v2, 875 876 .table = { 877 .id = rk3228_code_table, 878 .length = ARRAY_SIZE(rk3228_code_table), 879 .data_mask = TSADCV3_DATA_MASK, 880 .mode = ADC_INCREMENT, 881 }, 882 }; 883 884 static const struct rockchip_tsadc_chip rk3288_tsadc_data = { 885 .chn_id[SENSOR_CPU] = 1, /* cpu sensor is channel 1 */ 886 .chn_id[SENSOR_GPU] = 2, /* gpu sensor is channel 2 */ 887 .chn_num = 2, /* two channels for tsadc */ 888 889 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 890 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 891 .tshut_temp = 95000, 892 893 .tsadc_init = tsadc_init_v2, 894 .tsadc_control = tsadc_control_v2, 895 .tsadc_get_temp = tsadc_get_temp_v3, 896 .irq_ack = tsadc_irq_ack_v2, 897 .set_alarm_temp = tsadc_alarm_temp_v2, 898 .set_tshut_temp = tsadc_tshut_temp_v2, 899 .set_tshut_mode = tsadc_tshut_mode_v2, 900 901 .table = { 902 .id = rk3288_code_table, 903 .length = ARRAY_SIZE(rk3288_code_table), 904 .data_mask = TSADCV2_DATA_MASK, 905 .mode = ADC_DECREMENT, 906 }, 907 }; 908 909 static const struct rockchip_tsadc_chip rk3308_tsadc_data = { 910 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 911 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 912 .chn_num = 2, /* 2 channels for tsadc */ 913 914 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ 915 .tshut_temp = 95000, 916 917 .tsadc_init = tsadc_init_v4, 918 .tsadc_control = tsadc_control_v3, 919 .tsadc_get_temp = tsadc_get_temp_v2, 920 .irq_ack = tsadc_irq_ack_v3, 921 .set_alarm_temp = tsadc_alarm_temp_v2, 922 .set_tshut_temp = tsadc_tshut_temp_v2, 923 .set_tshut_mode = tsadc_tshut_mode_v2, 924 925 .table = { 926 .id = rk3328_code_table, 927 .length = ARRAY_SIZE(rk3328_code_table), 928 .data_mask = TSADCV2_DATA_MASK, 929 .mode = ADC_INCREMENT, 930 }, 931 }; 932 933 static const struct rockchip_tsadc_chip px30_tsadc_data = { 934 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 935 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 936 .chn_num = 2, /* 2 channels for tsadc */ 937 938 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ 939 .tshut_temp = 95000, 940 941 .tsadc_init = tsadc_init_v4, 942 .tsadc_control = tsadc_control_v3, 943 .tsadc_get_temp = tsadc_get_temp_v2, 944 .irq_ack = tsadc_irq_ack_v3, 945 .set_alarm_temp = tsadc_alarm_temp_v2, 946 .set_tshut_temp = tsadc_tshut_temp_v2, 947 .set_tshut_mode = tsadc_tshut_mode_v2, 948 949 .table = { 950 .id = rk3328_code_table, 951 .length = ARRAY_SIZE(rk3328_code_table), 952 .data_mask = TSADCV2_DATA_MASK, 953 .mode = ADC_INCREMENT, 954 }, 955 }; 956 957 static const struct rockchip_tsadc_chip rk3328_tsadc_data = { 958 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 959 .chn_num = 1, /* one channels for tsadc */ 960 961 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ 962 .tshut_temp = 95000, 963 964 .tsadc_init = tsadc_init_v2, 965 .tsadc_control = tsadc_control_v3, 966 .tsadc_get_temp = tsadc_get_temp_v2, 967 .irq_ack = tsadc_irq_ack_v3, 968 .set_alarm_temp = tsadc_alarm_temp_v2, 969 .set_tshut_temp = tsadc_tshut_temp_v2, 970 .set_tshut_mode = tsadc_tshut_mode_v2, 971 972 .table = { 973 .id = rk3328_code_table, 974 .length = ARRAY_SIZE(rk3328_code_table), 975 .data_mask = TSADCV2_DATA_MASK, 976 .mode = ADC_INCREMENT, 977 }, 978 }; 979 980 static const struct rockchip_tsadc_chip rk3366_tsadc_data = { 981 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 982 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 983 .chn_num = 2, /* two channels for tsadc */ 984 985 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 986 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 987 .tshut_temp = 95000, 988 989 .tsadc_init = tsadc_init_v3, 990 .tsadc_control = tsadc_control_v3, 991 .tsadc_get_temp = tsadc_get_temp_v2, 992 .irq_ack = tsadc_irq_ack_v3, 993 .set_alarm_temp = tsadc_alarm_temp_v2, 994 .set_tshut_temp = tsadc_tshut_temp_v2, 995 .set_tshut_mode = tsadc_tshut_mode_v2, 996 997 .table = { 998 .id = rk3228_code_table, 999 .length = ARRAY_SIZE(rk3228_code_table), 1000 .data_mask = TSADCV3_DATA_MASK, 1001 .mode = ADC_INCREMENT, 1002 }, 1003 }; 1004 1005 static const struct rockchip_tsadc_chip rk3368_tsadc_data = { 1006 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1007 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1008 .chn_num = 2, /* two channels for tsadc */ 1009 1010 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1011 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1012 .tshut_temp = 95000, 1013 1014 .tsadc_init = tsadc_init_v2, 1015 .tsadc_control = tsadc_control_v2, 1016 .tsadc_get_temp = tsadc_get_temp_v2, 1017 .irq_ack = tsadc_irq_ack_v2, 1018 .set_alarm_temp = tsadc_alarm_temp_v2, 1019 .set_tshut_temp = tsadc_tshut_temp_v2, 1020 .set_tshut_mode = tsadc_tshut_mode_v2, 1021 1022 .table = { 1023 .id = rk3368_code_table, 1024 .length = ARRAY_SIZE(rk3368_code_table), 1025 .data_mask = TSADCV3_DATA_MASK, 1026 .mode = ADC_INCREMENT, 1027 }, 1028 }; 1029 1030 static const struct rockchip_tsadc_chip rk3399_tsadc_data = { 1031 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1032 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1033 .chn_num = 2, /* two channels for tsadc */ 1034 1035 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1036 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1037 .tshut_temp = 95000, 1038 1039 .tsadc_init = tsadc_init_v3, 1040 .tsadc_control = tsadc_control_v3, 1041 .tsadc_get_temp = tsadc_get_temp_v2, 1042 .irq_ack = tsadc_irq_ack_v3, 1043 .set_alarm_temp = tsadc_alarm_temp_v2, 1044 .set_tshut_temp = tsadc_tshut_temp_v2, 1045 .set_tshut_mode = tsadc_tshut_mode_v2, 1046 1047 .table = { 1048 .id = rk3399_code_table, 1049 .length = ARRAY_SIZE(rk3399_code_table), 1050 .data_mask = TSADCV3_DATA_MASK, 1051 .mode = ADC_INCREMENT, 1052 }, 1053 }; 1054 1055 static const struct udevice_id rockchip_thermal_match[] = { 1056 { 1057 .compatible = "rockchip,px30-tsadc", 1058 .data = (ulong)&px30_tsadc_data, 1059 }, 1060 { 1061 .compatible = "rockchip,rk1808-tsadc", 1062 .data = (ulong)&rk1808_tsadc_data, 1063 }, 1064 { 1065 .compatible = "rockchip,rk3228-tsadc", 1066 .data = (ulong)&rk3228_tsadc_data, 1067 }, 1068 { 1069 .compatible = "rockchip,rk3288-tsadc", 1070 .data = (ulong)&rk3288_tsadc_data, 1071 }, 1072 { 1073 .compatible = "rockchip,rk3308-tsadc", 1074 .data = (ulong)&rk3308_tsadc_data, 1075 }, 1076 { 1077 .compatible = "rockchip,rk3328-tsadc", 1078 .data = (ulong)&rk3328_tsadc_data, 1079 }, 1080 { 1081 .compatible = "rockchip,rk3366-tsadc", 1082 .data = (ulong)&rk3366_tsadc_data, 1083 }, 1084 { 1085 .compatible = "rockchip,rk3368-tsadc", 1086 .data = (ulong)&rk3368_tsadc_data, 1087 }, 1088 { 1089 .compatible = "rockchip,rk3399-tsadc", 1090 .data = (ulong)&rk3399_tsadc_data, 1091 }, 1092 { /* end */ }, 1093 }; 1094 1095 U_BOOT_DRIVER(rockchip_thermal) = { 1096 .name = "rockchip_thermal", 1097 .id = UCLASS_THERMAL, 1098 .of_match = rockchip_thermal_match, 1099 .priv_auto_alloc_size = sizeof(struct rockchip_thermal_priv), 1100 .ofdata_to_platdata = rockchip_thermal_ofdata_to_platdata, 1101 .ops = &rockchip_thermal_ops, 1102 .probe = rockchip_thermal_probe, 1103 }; 1104