1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6 #include <common.h> 7 #include <bitfield.h> 8 #include <thermal.h> 9 #include <dm.h> 10 #include <dm/pinctrl.h> 11 #include <div64.h> 12 #include <errno.h> 13 #include <syscon.h> 14 #include <asm/arch/clock.h> 15 #include <asm/arch/cpu.h> 16 #include <asm/arch/hardware.h> 17 #include <asm/io.h> 18 #include <dm/lists.h> 19 #include <clk.h> 20 #include <clk-uclass.h> 21 #include <reset.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 /** 26 * If the temperature over a period of time High, 27 * the resulting TSHUT gave CRU module,let it reset the entire chip, 28 * or via GPIO give PMIC. 29 */ 30 enum tshut_mode { 31 TSHUT_MODE_CRU = 0, 32 TSHUT_MODE_GPIO, 33 }; 34 35 /** 36 * The system Temperature Sensors tshut(tshut) polarity 37 * the bit 8 is tshut polarity. 38 * 0: low active, 1: high active 39 */ 40 enum tshut_polarity { 41 TSHUT_LOW_ACTIVE = 0, 42 TSHUT_HIGH_ACTIVE, 43 }; 44 45 /** 46 * The conversion table has the adc value and temperature. 47 * ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table) 48 * ADC_INCREMENT: the adc value is incremental.(e.g. rk3368_code_table) 49 */ 50 enum adc_sort_mode { 51 ADC_DECREMENT = 0, 52 ADC_INCREMENT, 53 }; 54 55 #define SOC_MAX_SENSORS 7 56 57 #define TSADCV2_USER_CON 0x00 58 #define TSADCV2_AUTO_CON 0x04 59 #define TSADCV2_INT_EN 0x08 60 #define TSADCV2_INT_PD 0x0c 61 #define TSADCV3_AUTO_SRC_CON 0x0c 62 #define TSADCV3_HT_INT_EN 0x14 63 #define TSADCV3_HSHUT_GPIO_INT_EN 0x18 64 #define TSADCV3_HSHUT_CRU_INT_EN 0x1c 65 #define TSADCV3_INT_PD 0x24 66 #define TSADCV3_HSHUT_PD 0x28 67 #define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04) 68 #define TSADCV2_COMP_INT(chn) (0x30 + (chn) * 0x04) 69 #define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04) 70 #define TSADCV3_DATA(chn) (0x2c + (chn) * 0x04) 71 #define TSADCV3_COMP_INT(chn) (0x6c + (chn) * 0x04) 72 #define TSADCV3_COMP_SHUT(chn) (0x10c + (chn) * 0x04) 73 #define TSADCV2_HIGHT_INT_DEBOUNCE 0x60 74 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64 75 #define TSADCV3_HIGHT_INT_DEBOUNCE 0x14c 76 #define TSADCV3_HIGHT_TSHUT_DEBOUNCE 0x150 77 #define TSADCV2_AUTO_PERIOD 0x68 78 #define TSADCV2_AUTO_PERIOD_HT 0x6c 79 #define TSADCV3_AUTO_PERIOD 0x154 80 #define TSADCV3_AUTO_PERIOD_HT 0x158 81 #define TSADCV3_Q_MAX 0x210 82 83 #define TSADCV2_AUTO_EN BIT(0) 84 #define TSADCV2_AUTO_EN_MASK BIT(16) 85 #define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn)) 86 #define TSADCV3_AUTO_SRC_EN(chn) BIT(chn) 87 #define TSADCV3_AUTO_SRC_EN_MASK(chn) BIT(16 + (chn)) 88 #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8) 89 #define TSADCV2_AUTO_TSHUT_POLARITY_MASK BIT(24) 90 91 #define TSADCV3_AUTO_Q_SEL_EN BIT(1) 92 #define TSADCV3_AUTO_Q_SEL_EN_MASK BIT(17) 93 94 #define TSADCV2_INT_SRC_EN(chn) BIT(chn) 95 #define TSADCV2_INT_SRC_EN_MASK(chn) BIT(16 + (chn)) 96 #define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn)) 97 #define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn)) 98 99 #define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8) 100 #define TSADCV3_INT_PD_CLEAR_MASK ~BIT(16) 101 #define TSADCV4_INT_PD_CLEAR_MASK 0xffffffff 102 103 #define TSADCV2_DATA_MASK 0xfff 104 #define TSADCV3_DATA_MASK 0x3ff 105 #define TSADCV4_DATA_MASK 0x1ff 106 #define TSADCV5_DATA_MASK 0x7ff 107 108 #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4 109 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4 110 #define TSADCV2_AUTO_PERIOD_TIME 250 111 #define TSADCV2_AUTO_PERIOD_HT_TIME 50 112 #define TSADCV3_AUTO_PERIOD_TIME 1875 113 #define TSADCV3_AUTO_PERIOD_HT_TIME 1875 114 #define TSADCV5_AUTO_PERIOD_TIME 1622 /* 2.5ms */ 115 #define TSADCV5_AUTO_PERIOD_HT_TIME 1622 /* 2.5ms */ 116 #define TSADCV6_AUTO_PERIOD_TIME 5000 /* 2.5ms */ 117 #define TSADCV6_AUTO_PERIOD_HT_TIME 5000 /* 2.5ms */ 118 #define TSADCV7_AUTO_PERIOD_TIME 3000 /* 2.5ms */ 119 #define TSADCV7_AUTO_PERIOD_HT_TIME 3000 /* 2.5ms */ 120 #define TSADCV3_Q_MAX_VAL 0x7ff /* 11bit 2047 */ 121 122 #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */ 123 #define TSADCV5_USER_INTER_PD_SOC 0xfc0 /* 97us, at least 90us */ 124 125 #define GRF_SARADC_TESTBIT 0x0e644 126 #define GRF_TSADC_TESTBIT_L 0x0e648 127 #define GRF_TSADC_TESTBIT_H 0x0e64c 128 129 #define PX30_GRF_SOC_CON0 0x0400 130 #define PX30_GRF_SOC_CON2 0x0408 131 132 #define RK3568_GRF_TSADC_CON 0x0600 133 #define RK3528_GRF_TSADC_CON 0x40030 134 #define RK3568_GRF_TSADC_ANA_REG0 (0x10001 << 0) 135 #define RK3568_GRF_TSADC_ANA_REG1 (0x10001 << 1) 136 #define RK3568_GRF_TSADC_ANA_REG2 (0x10001 << 2) 137 #define RK3568_GRF_TSADC_TSEN (0x10001 << 8) 138 139 #define GRF_SARADC_TESTBIT_ON (0x10001 << 2) 140 #define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2) 141 #define GRF_TSADC_VCM_EN_L (0x10001 << 7) 142 #define GRF_TSADC_VCM_EN_H (0x10001 << 7) 143 144 #define GRF_CON_TSADC_CH_INV (0x10001 << 1) 145 #define PX30S_TSADC_TDC_MODE (0x10001 << 4) 146 147 #define MIN_TEMP (-40000) 148 #define LOWEST_TEMP (-273000) 149 #define MAX_TEMP (125000) 150 #define MAX_ENV_TEMP (85000) 151 152 #define BASE (1024) 153 #define BASE_SHIFT (10) 154 #define START_DEBOUNCE_COUNT (100) 155 #define HIGHER_DEBOUNCE_TEMP (30000) 156 #define LOWER_DEBOUNCE_TEMP (15000) 157 158 /** 159 * struct tsadc_table - hold information about code and temp mapping 160 * @code: raw code from tsadc ip 161 * @temp: the mapping temperature 162 */ 163 164 struct tsadc_table { 165 unsigned long code; 166 int temp; 167 }; 168 169 struct chip_tsadc_table { 170 const struct tsadc_table *id; 171 unsigned int length; 172 u32 data_mask; 173 /* Tsadc is linear, using linear parameters */ 174 int knum; 175 int bnum; 176 enum adc_sort_mode mode; 177 }; 178 179 enum sensor_id { 180 SENSOR_CPU = 0, 181 SENSOR_GPU, 182 }; 183 184 struct rockchip_tsadc_chip { 185 /* The sensor id of chip correspond to the ADC channel */ 186 int chn_id[SOC_MAX_SENSORS]; 187 int chn_num; 188 fdt_addr_t base; 189 fdt_addr_t grf; 190 191 /* The hardware-controlled tshut property */ 192 int tshut_temp; 193 enum tshut_mode tshut_mode; 194 enum tshut_polarity tshut_polarity; 195 196 void (*tsadc_control)(struct udevice *dev, bool enable); 197 void (*tsadc_init)(struct udevice *dev); 198 int (*tsadc_get_temp)(struct udevice *dev, int chn, 199 int *temp); 200 void (*irq_ack)(struct udevice *dev); 201 void (*set_alarm_temp)(struct udevice *dev, 202 int chn, int temp); 203 void (*set_tshut_temp)(struct udevice *dev, 204 int chn, int temp); 205 void (*set_tshut_mode)(struct udevice *dev, int chn, enum tshut_mode m); 206 struct chip_tsadc_table table; 207 }; 208 209 struct rockchip_thermal_priv { 210 void *base; 211 void *grf; 212 enum tshut_mode tshut_mode; 213 enum tshut_polarity tshut_polarity; 214 const struct rockchip_tsadc_chip *data; 215 }; 216 217 static const struct tsadc_table rk1808_code_table[] = { 218 {0, -40000}, 219 {3455, -40000}, 220 {3463, -35000}, 221 {3471, -30000}, 222 {3479, -25000}, 223 {3487, -20000}, 224 {3495, -15000}, 225 {3503, -10000}, 226 {3511, -5000}, 227 {3519, 0}, 228 {3527, 5000}, 229 {3535, 10000}, 230 {3543, 15000}, 231 {3551, 20000}, 232 {3559, 25000}, 233 {3567, 30000}, 234 {3576, 35000}, 235 {3584, 40000}, 236 {3592, 45000}, 237 {3600, 50000}, 238 {3609, 55000}, 239 {3617, 60000}, 240 {3625, 65000}, 241 {3633, 70000}, 242 {3642, 75000}, 243 {3650, 80000}, 244 {3659, 85000}, 245 {3667, 90000}, 246 {3675, 95000}, 247 {3684, 100000}, 248 {3692, 105000}, 249 {3701, 110000}, 250 {3709, 115000}, 251 {3718, 120000}, 252 {3726, 125000}, 253 {TSADCV2_DATA_MASK, 125000}, 254 }; 255 256 static const struct tsadc_table rk3228_code_table[] = { 257 {0, -40000}, 258 {588, -40000}, 259 {593, -35000}, 260 {598, -30000}, 261 {603, -25000}, 262 {608, -20000}, 263 {613, -15000}, 264 {618, -10000}, 265 {623, -5000}, 266 {629, 0}, 267 {634, 5000}, 268 {639, 10000}, 269 {644, 15000}, 270 {649, 20000}, 271 {654, 25000}, 272 {660, 30000}, 273 {665, 35000}, 274 {670, 40000}, 275 {675, 45000}, 276 {681, 50000}, 277 {686, 55000}, 278 {691, 60000}, 279 {696, 65000}, 280 {702, 70000}, 281 {707, 75000}, 282 {712, 80000}, 283 {717, 85000}, 284 {723, 90000}, 285 {728, 95000}, 286 {733, 100000}, 287 {738, 105000}, 288 {744, 110000}, 289 {749, 115000}, 290 {754, 120000}, 291 {760, 125000}, 292 {TSADCV2_DATA_MASK, 125000}, 293 }; 294 295 static const struct tsadc_table rk3288_code_table[] = { 296 {TSADCV2_DATA_MASK, -40000}, 297 {3800, -40000}, 298 {3792, -35000}, 299 {3783, -30000}, 300 {3774, -25000}, 301 {3765, -20000}, 302 {3756, -15000}, 303 {3747, -10000}, 304 {3737, -5000}, 305 {3728, 0}, 306 {3718, 5000}, 307 {3708, 10000}, 308 {3698, 15000}, 309 {3688, 20000}, 310 {3678, 25000}, 311 {3667, 30000}, 312 {3656, 35000}, 313 {3645, 40000}, 314 {3634, 45000}, 315 {3623, 50000}, 316 {3611, 55000}, 317 {3600, 60000}, 318 {3588, 65000}, 319 {3575, 70000}, 320 {3563, 75000}, 321 {3550, 80000}, 322 {3537, 85000}, 323 {3524, 90000}, 324 {3510, 95000}, 325 {3496, 100000}, 326 {3482, 105000}, 327 {3467, 110000}, 328 {3452, 115000}, 329 {3437, 120000}, 330 {3421, 125000}, 331 }; 332 333 static const struct tsadc_table rk3328_code_table[] = { 334 {0, -40000}, 335 {296, -40000}, 336 {304, -35000}, 337 {313, -30000}, 338 {331, -20000}, 339 {340, -15000}, 340 {349, -10000}, 341 {359, -5000}, 342 {368, 0}, 343 {378, 5000}, 344 {388, 10000}, 345 {398, 15000}, 346 {408, 20000}, 347 {418, 25000}, 348 {429, 30000}, 349 {440, 35000}, 350 {451, 40000}, 351 {462, 45000}, 352 {473, 50000}, 353 {485, 55000}, 354 {496, 60000}, 355 {508, 65000}, 356 {521, 70000}, 357 {533, 75000}, 358 {546, 80000}, 359 {559, 85000}, 360 {572, 90000}, 361 {586, 95000}, 362 {600, 100000}, 363 {614, 105000}, 364 {629, 110000}, 365 {644, 115000}, 366 {659, 120000}, 367 {675, 125000}, 368 {TSADCV2_DATA_MASK, 125000}, 369 }; 370 371 static const struct tsadc_table rk3368_code_table[] = { 372 {0, -40000}, 373 {106, -40000}, 374 {108, -35000}, 375 {110, -30000}, 376 {112, -25000}, 377 {114, -20000}, 378 {116, -15000}, 379 {118, -10000}, 380 {120, -5000}, 381 {122, 0}, 382 {124, 5000}, 383 {126, 10000}, 384 {128, 15000}, 385 {130, 20000}, 386 {132, 25000}, 387 {134, 30000}, 388 {136, 35000}, 389 {138, 40000}, 390 {140, 45000}, 391 {142, 50000}, 392 {144, 55000}, 393 {146, 60000}, 394 {148, 65000}, 395 {150, 70000}, 396 {152, 75000}, 397 {154, 80000}, 398 {156, 85000}, 399 {158, 90000}, 400 {160, 95000}, 401 {162, 100000}, 402 {163, 105000}, 403 {165, 110000}, 404 {167, 115000}, 405 {169, 120000}, 406 {171, 125000}, 407 {TSADCV3_DATA_MASK, 125000}, 408 }; 409 410 static const struct tsadc_table rk3399_code_table[] = { 411 {0, -40000}, 412 {402, -40000}, 413 {410, -35000}, 414 {419, -30000}, 415 {427, -25000}, 416 {436, -20000}, 417 {444, -15000}, 418 {453, -10000}, 419 {461, -5000}, 420 {470, 0}, 421 {478, 5000}, 422 {487, 10000}, 423 {496, 15000}, 424 {504, 20000}, 425 {513, 25000}, 426 {521, 30000}, 427 {530, 35000}, 428 {538, 40000}, 429 {547, 45000}, 430 {555, 50000}, 431 {564, 55000}, 432 {573, 60000}, 433 {581, 65000}, 434 {590, 70000}, 435 {599, 75000}, 436 {607, 80000}, 437 {616, 85000}, 438 {624, 90000}, 439 {633, 95000}, 440 {642, 100000}, 441 {650, 105000}, 442 {659, 110000}, 443 {668, 115000}, 444 {677, 120000}, 445 {685, 125000}, 446 {TSADCV3_DATA_MASK, 125000}, 447 }; 448 449 static const struct tsadc_table rk3528_code_table[] = { 450 {0, -40000}, 451 {1419, -40000}, 452 {1427, -35000}, 453 {1435, -30000}, 454 {1443, -25000}, 455 {1452, -20000}, 456 {1460, -15000}, 457 {1468, -10000}, 458 {1477, -5000}, 459 {1486, 0}, 460 {1494, 5000}, 461 {1502, 10000}, 462 {1510, 15000}, 463 {1519, 20000}, 464 {1527, 25000}, 465 {1535, 30000}, 466 {1544, 35000}, 467 {1552, 40000}, 468 {1561, 45000}, 469 {1569, 50000}, 470 {1578, 55000}, 471 {1586, 60000}, 472 {1594, 65000}, 473 {1603, 70000}, 474 {1612, 75000}, 475 {1620, 80000}, 476 {1628, 85000}, 477 {1637, 90000}, 478 {1646, 95000}, 479 {1654, 100000}, 480 {1662, 105000}, 481 {1671, 110000}, 482 {1679, 115000}, 483 {1688, 120000}, 484 {1696, 125000}, 485 {TSADCV5_DATA_MASK, 125000}, 486 }; 487 488 static const struct tsadc_table rk3568_code_table[] = { 489 {0, -40000}, 490 {1584, -40000}, 491 {1620, -35000}, 492 {1652, -30000}, 493 {1688, -25000}, 494 {1720, -20000}, 495 {1756, -15000}, 496 {1788, -10000}, 497 {1824, -5000}, 498 {1856, 0}, 499 {1892, 5000}, 500 {1924, 10000}, 501 {1956, 15000}, 502 {1992, 20000}, 503 {2024, 25000}, 504 {2060, 30000}, 505 {2092, 35000}, 506 {2128, 40000}, 507 {2160, 45000}, 508 {2196, 50000}, 509 {2228, 55000}, 510 {2264, 60000}, 511 {2300, 65000}, 512 {2332, 70000}, 513 {2368, 75000}, 514 {2400, 80000}, 515 {2436, 85000}, 516 {2468, 90000}, 517 {2500, 95000}, 518 {2536, 100000}, 519 {2572, 105000}, 520 {2604, 110000}, 521 {2636, 115000}, 522 {2672, 120000}, 523 {2704, 125000}, 524 {TSADCV2_DATA_MASK, 125000}, 525 }; 526 527 static const struct tsadc_table rk3588_code_table[] = { 528 {0, -40000}, 529 {215, -40000}, 530 {285, 25000}, 531 {350, 85000}, 532 {395, 125000}, 533 {TSADCV4_DATA_MASK, 125000}, 534 }; 535 536 /* 537 * Struct used for matching a device 538 */ 539 struct of_device_id { 540 char compatible[32]; 541 const void *data; 542 }; 543 544 static int tsadc_code_to_temp(struct chip_tsadc_table *table, u32 code, 545 int *temp) 546 { 547 unsigned int low = 1; 548 unsigned int high = table->length - 1; 549 unsigned int mid = (low + high) / 2; 550 unsigned int num; 551 unsigned long denom; 552 553 if (table->knum) { 554 *temp = (((int)code - table->bnum) * 10000 / table->knum) * 100; 555 if (*temp < MIN_TEMP || *temp > MAX_TEMP) 556 return -EAGAIN; 557 return 0; 558 } 559 560 switch (table->mode) { 561 case ADC_DECREMENT: 562 code &= table->data_mask; 563 if (code < table->id[high].code) 564 return -EAGAIN; /* Incorrect reading */ 565 566 while (low <= high) { 567 if (code >= table->id[mid].code && 568 code < table->id[mid - 1].code) 569 break; 570 else if (code < table->id[mid].code) 571 low = mid + 1; 572 else 573 high = mid - 1; 574 575 mid = (low + high) / 2; 576 } 577 break; 578 case ADC_INCREMENT: 579 code &= table->data_mask; 580 if (code < table->id[low].code) 581 return -EAGAIN; /* Incorrect reading */ 582 583 while (low <= high) { 584 if (code <= table->id[mid].code && 585 code > table->id[mid - 1].code) 586 break; 587 else if (code > table->id[mid].code) 588 low = mid + 1; 589 else 590 high = mid - 1; 591 592 mid = (low + high) / 2; 593 } 594 break; 595 default: 596 printf("%s: Invalid the conversion table mode=%d\n", 597 __func__, table->mode); 598 return -EINVAL; 599 } 600 601 /* 602 * The 5C granularity provided by the table is too much. Let's 603 * assume that the relationship between sensor readings and 604 * temperature between 2 table entries is linear and interpolate 605 * to produce less granular result. 606 */ 607 num = table->id[mid].temp - table->id[mid - 1].temp; 608 num *= abs(table->id[mid - 1].code - code); 609 denom = abs(table->id[mid - 1].code - table->id[mid].code); 610 *temp = table->id[mid - 1].temp + (num / denom); 611 612 return 0; 613 } 614 615 static u32 tsadc_temp_to_code_v2(struct chip_tsadc_table table, 616 int temp) 617 { 618 int high, low, mid; 619 unsigned long num; 620 unsigned int denom; 621 u32 error = table.data_mask; 622 623 if (table.knum) 624 return (((temp / 1000) * table.knum) / 1000 + table.bnum); 625 626 low = 0; 627 high = table.length - 1; 628 mid = (high + low) / 2; 629 630 /* Return mask code data when the temp is over table range */ 631 if (temp < table.id[low].temp || temp > table.id[high].temp) 632 goto exit; 633 634 while (low <= high) { 635 if (temp == table.id[mid].temp) 636 return table.id[mid].code; 637 else if (temp < table.id[mid].temp) 638 high = mid - 1; 639 else 640 low = mid + 1; 641 mid = (low + high) / 2; 642 } 643 644 num = abs(table.id[mid + 1].code - table.id[mid].code); 645 num *= temp - table.id[mid].temp; 646 denom = table.id[mid + 1].temp - table.id[mid].temp; 647 648 switch (table.mode) { 649 case ADC_DECREMENT: 650 return table.id[mid].code - (num / denom); 651 case ADC_INCREMENT: 652 return table.id[mid].code + (num / denom); 653 default: 654 pr_err("%s: unknown table mode: %d\n", __func__, table.mode); 655 return error; 656 } 657 658 exit: 659 pr_err("%s: Invalid conversion table: code=%d, temperature=%d\n", 660 __func__, error, temp); 661 662 return error; 663 } 664 665 static void tsadc_irq_ack_v2(struct udevice *dev) 666 { 667 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 668 u32 val; 669 670 val = readl(priv->base + TSADCV2_INT_PD); 671 writel(val & TSADCV2_INT_PD_CLEAR_MASK, priv->base + TSADCV2_INT_PD); 672 } 673 674 static void tsadc_irq_ack_v3(struct udevice *dev) 675 { 676 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 677 u32 val; 678 679 val = readl(priv->base + TSADCV2_INT_PD); 680 writel(val & TSADCV3_INT_PD_CLEAR_MASK, priv->base + TSADCV2_INT_PD); 681 } 682 683 static void tsadc_irq_ack_v4(struct udevice *dev) 684 { 685 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 686 u32 val; 687 688 val = readl(priv->base + TSADCV3_INT_PD); 689 writel(val & TSADCV4_INT_PD_CLEAR_MASK, priv->base + TSADCV3_INT_PD); 690 val = readl(priv->base + TSADCV3_HSHUT_PD); 691 writel(val & TSADCV3_INT_PD_CLEAR_MASK, priv->base + TSADCV3_HSHUT_PD); 692 } 693 694 static void tsadc_control_v2(struct udevice *dev, bool enable) 695 { 696 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 697 u32 val; 698 699 val = readl(priv->base + TSADCV2_AUTO_CON); 700 if (enable) 701 val |= TSADCV2_AUTO_EN; 702 else 703 val &= ~TSADCV2_AUTO_EN; 704 705 writel(val, priv->base + TSADCV2_AUTO_CON); 706 } 707 708 static void tsadc_control_v3(struct udevice *dev, bool enable) 709 { 710 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 711 u32 val; 712 713 val = readl(priv->base + TSADCV2_AUTO_CON); 714 if (enable) 715 val |= TSADCV2_AUTO_EN | TSADCV3_AUTO_Q_SEL_EN; 716 else 717 val &= ~TSADCV2_AUTO_EN; 718 719 writel(val, priv->base + TSADCV2_AUTO_CON); 720 } 721 722 static void tsadc_control_v4(struct udevice *dev, bool enable) 723 { 724 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 725 u32 val; 726 727 if (enable) 728 val = TSADCV2_AUTO_EN | TSADCV2_AUTO_EN_MASK; 729 else 730 val = TSADCV2_AUTO_EN_MASK; 731 732 writel(val, priv->base + TSADCV2_AUTO_CON); 733 } 734 735 static void tsadc_init_v2(struct udevice *dev) 736 { 737 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 738 739 writel(TSADCV2_AUTO_PERIOD_TIME, 740 priv->base + TSADCV2_AUTO_PERIOD); 741 writel(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, 742 priv->base + TSADCV2_HIGHT_INT_DEBOUNCE); 743 writel(TSADCV2_AUTO_PERIOD_HT_TIME, 744 priv->base + TSADCV2_AUTO_PERIOD_HT); 745 writel(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, 746 priv->base + TSADCV2_HIGHT_TSHUT_DEBOUNCE); 747 748 if (priv->tshut_polarity == TSHUT_HIGH_ACTIVE) 749 writel(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 750 priv->base + TSADCV2_AUTO_CON); 751 else 752 writel(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 753 priv->base + TSADCV2_AUTO_CON); 754 } 755 756 static void tsadc_init_v3(struct udevice *dev) 757 { 758 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 759 760 if (!IS_ERR(priv->grf)) { 761 writel(GRF_TSADC_VCM_EN_L, priv->grf + GRF_TSADC_TESTBIT_L); 762 writel(GRF_TSADC_VCM_EN_H, priv->grf + GRF_TSADC_TESTBIT_H); 763 764 udelay(100);/* The spec note says at least 15 us */ 765 writel(GRF_SARADC_TESTBIT_ON, priv->grf + GRF_SARADC_TESTBIT); 766 writel(GRF_TSADC_TESTBIT_H_ON, priv->grf + GRF_TSADC_TESTBIT_H); 767 udelay(200);/* The spec note says at least 90 us */ 768 } 769 tsadc_init_v2(dev); 770 } 771 772 static void __maybe_unused tsadc_init_v5(struct udevice *dev) 773 { 774 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 775 776 /* Set interleave value to workround ic time sync issue */ 777 writel(TSADCV2_USER_INTER_PD_SOC, priv->base + 778 TSADCV2_USER_CON); 779 tsadc_init_v2(dev); 780 } 781 782 static void tsadc_init_v4(struct udevice *dev) 783 { 784 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 785 786 tsadc_init_v2(dev); 787 if (!IS_ERR(priv->grf)) 788 writel(GRF_CON_TSADC_CH_INV, priv->grf + PX30_GRF_SOC_CON2); 789 } 790 791 static void tsadc_init_v7(struct udevice *dev) 792 { 793 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 794 795 writel(TSADCV5_USER_INTER_PD_SOC, 796 priv->base + TSADCV2_USER_CON); 797 writel(TSADCV5_AUTO_PERIOD_TIME, 798 priv->base + TSADCV2_AUTO_PERIOD); 799 writel(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, 800 priv->base + TSADCV2_HIGHT_INT_DEBOUNCE); 801 writel(TSADCV5_AUTO_PERIOD_HT_TIME, 802 priv->base + TSADCV2_AUTO_PERIOD_HT); 803 writel(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, 804 priv->base + TSADCV2_HIGHT_TSHUT_DEBOUNCE); 805 806 if (priv->tshut_polarity == TSHUT_HIGH_ACTIVE) 807 writel(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 808 priv->base + TSADCV2_AUTO_CON); 809 else 810 writel(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 811 priv->base + TSADCV2_AUTO_CON); 812 813 if (!IS_ERR(priv->grf)) { 814 writel(RK3568_GRF_TSADC_TSEN, 815 priv->grf + RK3568_GRF_TSADC_CON); 816 udelay(15); 817 writel(RK3568_GRF_TSADC_ANA_REG0, 818 priv->grf + RK3568_GRF_TSADC_CON); 819 writel(RK3568_GRF_TSADC_ANA_REG1, 820 priv->grf + RK3568_GRF_TSADC_CON); 821 writel(RK3568_GRF_TSADC_ANA_REG2, 822 priv->grf + RK3568_GRF_TSADC_CON); 823 udelay(200); 824 } 825 } 826 827 static void tsadc_init_v8(struct udevice *dev) 828 { 829 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 830 831 writel(TSADCV6_AUTO_PERIOD_TIME, priv->base + TSADCV3_AUTO_PERIOD); 832 writel(TSADCV6_AUTO_PERIOD_HT_TIME, 833 priv->base + TSADCV3_AUTO_PERIOD_HT); 834 writel(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, 835 priv->base + TSADCV3_HIGHT_INT_DEBOUNCE); 836 writel(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, 837 priv->base + TSADCV3_HIGHT_TSHUT_DEBOUNCE); 838 839 if (priv->tshut_polarity == TSHUT_HIGH_ACTIVE) 840 writel(TSADCV2_AUTO_TSHUT_POLARITY_HIGH | 841 TSADCV2_AUTO_TSHUT_POLARITY_MASK, 842 priv->base + TSADCV2_AUTO_CON); 843 else 844 writel(TSADCV2_AUTO_TSHUT_POLARITY_MASK, 845 priv->base + TSADCV2_AUTO_CON); 846 }; 847 848 static void tsadc_init_v9(struct udevice *dev) 849 { 850 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 851 852 tsadc_init_v2(dev); 853 if (!IS_ERR(priv->grf)) 854 writel(PX30S_TSADC_TDC_MODE, priv->grf + PX30_GRF_SOC_CON0); 855 } 856 857 static void tsadc_init_v11(struct udevice *dev) 858 { 859 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 860 861 writel(TSADCV7_AUTO_PERIOD_TIME, priv->base + TSADCV3_AUTO_PERIOD); 862 writel(TSADCV7_AUTO_PERIOD_HT_TIME, 863 priv->base + TSADCV3_AUTO_PERIOD_HT); 864 writel(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, 865 priv->base + TSADCV3_HIGHT_INT_DEBOUNCE); 866 writel(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, 867 priv->base + TSADCV3_HIGHT_TSHUT_DEBOUNCE); 868 writel(TSADCV3_Q_MAX_VAL, priv->base + TSADCV3_Q_MAX); 869 writel(TSADCV3_AUTO_Q_SEL_EN | TSADCV3_AUTO_Q_SEL_EN_MASK, 870 priv->base + TSADCV2_AUTO_CON); 871 872 if (priv->tshut_polarity == TSHUT_HIGH_ACTIVE) 873 writel(TSADCV2_AUTO_TSHUT_POLARITY_HIGH | 874 TSADCV2_AUTO_TSHUT_POLARITY_MASK, 875 priv->base + TSADCV2_AUTO_CON); 876 else 877 writel(TSADCV2_AUTO_TSHUT_POLARITY_MASK, 878 priv->base + TSADCV2_AUTO_CON); 879 880 if (!IS_ERR(priv->grf)) { 881 writel(RK3568_GRF_TSADC_TSEN, 882 priv->grf + RK3528_GRF_TSADC_CON); 883 udelay(15); 884 writel(RK3568_GRF_TSADC_ANA_REG0, 885 priv->grf + RK3528_GRF_TSADC_CON); 886 writel(RK3568_GRF_TSADC_ANA_REG1, 887 priv->grf + RK3528_GRF_TSADC_CON); 888 writel(RK3568_GRF_TSADC_ANA_REG2, 889 priv->grf + RK3528_GRF_TSADC_CON); 890 udelay(200); 891 } 892 } 893 894 static int tsadc_get_temp_v2(struct udevice *dev, 895 int chn, int *temp) 896 { 897 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 898 struct chip_tsadc_table table = priv->data->table; 899 u32 val; 900 901 val = readl(priv->base + TSADCV2_DATA(chn)); 902 903 return tsadc_code_to_temp(&table, val, temp); 904 } 905 906 static int predict_temp(int temp) 907 { 908 /* 909 * The deviation of prediction. the temperature will not change rapidly, 910 * so this cov_q is small 911 */ 912 int cov_q = 18; 913 /* 914 * The deviation of tsadc's reading, deviation of tsadc is very big when 915 * abnormal temperature is get 916 */ 917 int cov_r = 542; 918 919 int gain; 920 int temp_mid; 921 int temp_now; 922 int prob_mid; 923 int prob_now; 924 static int temp_last = LOWEST_TEMP; 925 static int prob_last = 160; 926 static int bounding_cnt; 927 928 /* 929 * init temp_last with a more suitable value, which mostly equals to 930 * temp reading from tsadc, but not higher than MAX_ENV_TEMP. If the 931 * temp is higher than MAX_ENV_TEMP, it is assumed to be abnormal 932 * value and temp_last is adjusted to MAX_ENV_TEMP. 933 */ 934 if (temp_last == LOWEST_TEMP) 935 temp_last = min(temp, MAX_ENV_TEMP); 936 937 /* 938 * Before START_DEBOUNCE_COUNT's samples of temperature, we consider 939 * tsadc is stable, i.e. after that, the temperature may be not stable 940 * and may have abnormal reading, so we set a bounding temperature. If 941 * the reading from tsadc is too big, we set the delta temperature of 942 * DEBOUNCE_TEMP/3 comparing to the last temperature. 943 */ 944 945 if (bounding_cnt++ > START_DEBOUNCE_COUNT) { 946 bounding_cnt = START_DEBOUNCE_COUNT; 947 if (temp - temp_last > HIGHER_DEBOUNCE_TEMP) 948 temp = temp_last + HIGHER_DEBOUNCE_TEMP / 3; 949 if (temp_last - temp > LOWER_DEBOUNCE_TEMP) 950 temp = temp_last - LOWER_DEBOUNCE_TEMP / 3; 951 } 952 953 temp_mid = temp_last; 954 955 /* calculate the probability of this time's prediction */ 956 prob_mid = prob_last + cov_q; 957 958 /* calculate the Kalman Gain */ 959 gain = (prob_mid * BASE) / (prob_mid + cov_r); 960 961 /* calculate the prediction of temperature */ 962 temp_now = (temp_mid * BASE + gain * (temp - temp_mid)) >> BASE_SHIFT; 963 964 /* 965 * Base on this time's Kalman Gain, ajust our probability of prediction 966 * for next time calculation 967 */ 968 prob_now = ((BASE - gain) * prob_mid) >> BASE_SHIFT; 969 970 prob_last = prob_now; 971 temp_last = temp_now; 972 973 return temp_last; 974 } 975 976 static int tsadc_get_temp_v3(struct udevice *dev, 977 int chn, int *temp) 978 { 979 int ret; 980 981 ret = tsadc_get_temp_v2(dev, chn, temp); 982 if (!ret) 983 *temp = predict_temp(*temp); 984 985 return ret; 986 } 987 988 static int tsadc_get_temp_v4(struct udevice *dev, int chn, int *temp) 989 { 990 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 991 struct chip_tsadc_table table = priv->data->table; 992 u32 val; 993 994 val = readl(priv->base + TSADCV3_DATA(chn)); 995 996 return tsadc_code_to_temp(&table, val, temp); 997 } 998 999 static void tsadc_alarm_temp_v2(struct udevice *dev, 1000 int chn, int temp) 1001 { 1002 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 1003 struct chip_tsadc_table table = priv->data->table; 1004 u32 alarm_value, int_en; 1005 1006 alarm_value = tsadc_temp_to_code_v2(table, temp); 1007 if (alarm_value == table.data_mask) 1008 return; 1009 1010 writel(alarm_value, priv->base + TSADCV2_COMP_INT(chn)); 1011 1012 int_en = readl(priv->base + TSADCV2_INT_EN); 1013 int_en |= TSADCV2_INT_SRC_EN(chn); 1014 writel(int_en, priv->base + TSADCV2_INT_EN); 1015 } 1016 1017 static void tsadc_alarm_temp_v3(struct udevice *dev, int chn, int temp) 1018 { 1019 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 1020 struct chip_tsadc_table table = priv->data->table; 1021 u32 alarm_value; 1022 1023 alarm_value = tsadc_temp_to_code_v2(table, temp); 1024 if (alarm_value == table.data_mask) 1025 return; 1026 1027 writel(alarm_value, priv->base + TSADCV3_COMP_INT(chn)); 1028 writel(TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn), 1029 priv->base + TSADCV3_HT_INT_EN); 1030 } 1031 1032 static void tsadc_tshut_temp_v2(struct udevice *dev, 1033 int chn, int temp) 1034 { 1035 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 1036 struct chip_tsadc_table table = priv->data->table; 1037 u32 tshut_value, val; 1038 1039 tshut_value = tsadc_temp_to_code_v2(table, temp); 1040 if (tshut_value == table.data_mask) 1041 return; 1042 1043 writel(tshut_value, priv->base + TSADCV2_COMP_SHUT(chn)); 1044 1045 /* TSHUT will be valid */ 1046 val = readl(priv->base + TSADCV2_AUTO_CON); 1047 writel(val | TSADCV2_AUTO_SRC_EN(chn), priv->base + TSADCV2_AUTO_CON); 1048 } 1049 1050 static void tsadc_tshut_temp_v3(struct udevice *dev, int chn, int temp) 1051 { 1052 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 1053 struct chip_tsadc_table table = priv->data->table; 1054 u32 tshut_value; 1055 1056 tshut_value = tsadc_temp_to_code_v2(table, temp); 1057 if (tshut_value == table.data_mask) 1058 return; 1059 1060 writel(tshut_value, priv->base + TSADCV3_COMP_SHUT(chn)); 1061 writel(TSADCV3_AUTO_SRC_EN(chn) | TSADCV3_AUTO_SRC_EN_MASK(chn), 1062 priv->base + TSADCV3_AUTO_SRC_CON); 1063 } 1064 1065 static void tsadc_tshut_mode_v2(struct udevice *dev, int chn, 1066 enum tshut_mode mode) 1067 { 1068 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 1069 u32 val; 1070 1071 val = readl(priv->base + TSADCV2_INT_EN); 1072 if (mode == TSHUT_MODE_GPIO) { 1073 val &= ~TSADCV2_SHUT_2CRU_SRC_EN(chn); 1074 val |= TSADCV2_SHUT_2GPIO_SRC_EN(chn); 1075 } else { 1076 val &= ~TSADCV2_SHUT_2GPIO_SRC_EN(chn); 1077 val |= TSADCV2_SHUT_2CRU_SRC_EN(chn); 1078 } 1079 1080 writel(val, priv->base + TSADCV2_INT_EN); 1081 } 1082 1083 static void tsadc_tshut_mode_v4(struct udevice *dev, int chn, 1084 enum tshut_mode mode) 1085 { 1086 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 1087 u32 val_gpio, val_cru; 1088 1089 if (mode == TSHUT_MODE_GPIO) { 1090 val_gpio = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn); 1091 val_cru = TSADCV2_INT_SRC_EN_MASK(chn); 1092 } else { 1093 val_cru = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn); 1094 val_gpio = TSADCV2_INT_SRC_EN_MASK(chn); 1095 } 1096 writel(val_gpio, priv->base + TSADCV3_HSHUT_GPIO_INT_EN); 1097 writel(val_cru, priv->base + TSADCV3_HSHUT_CRU_INT_EN); 1098 } 1099 1100 int rockchip_thermal_get_temp(struct udevice *dev, int *temp) 1101 { 1102 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 1103 1104 priv->data->tsadc_get_temp(dev, 0, temp); 1105 1106 return 0; 1107 } 1108 1109 static const struct dm_thermal_ops rockchip_thermal_ops = { 1110 .get_temp = rockchip_thermal_get_temp, 1111 }; 1112 1113 static const struct rockchip_tsadc_chip px30s_tsadc_data = { 1114 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1115 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1116 .chn_num = 2, /* 2 channels for tsadc */ 1117 1118 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ 1119 .tshut_temp = 95000, 1120 1121 .tsadc_init = tsadc_init_v9, 1122 .tsadc_control = tsadc_control_v2, 1123 .tsadc_get_temp = tsadc_get_temp_v2, 1124 .irq_ack = tsadc_irq_ack_v3, 1125 .set_alarm_temp = tsadc_alarm_temp_v2, 1126 .set_tshut_temp = tsadc_tshut_temp_v2, 1127 .set_tshut_mode = tsadc_tshut_mode_v2, 1128 1129 .table = { 1130 .knum = 2699, 1131 .bnum = 2796, 1132 .data_mask = TSADCV2_DATA_MASK, 1133 .mode = ADC_INCREMENT, 1134 }, 1135 }; 1136 1137 static const struct rockchip_tsadc_chip rk3308bs_tsadc_data = { 1138 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1139 .chn_num = 1, /* 1 channels for tsadc */ 1140 1141 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ 1142 .tshut_temp = 95000, 1143 1144 .tsadc_init = tsadc_init_v2, 1145 .tsadc_control = tsadc_control_v2, 1146 .tsadc_get_temp = tsadc_get_temp_v2, 1147 .irq_ack = tsadc_irq_ack_v3, 1148 .set_alarm_temp = tsadc_alarm_temp_v2, 1149 .set_tshut_temp = tsadc_tshut_temp_v2, 1150 .set_tshut_mode = tsadc_tshut_mode_v2, 1151 1152 .table = { 1153 .knum = 2699, 1154 .bnum = 2796, 1155 .data_mask = TSADCV2_DATA_MASK, 1156 .mode = ADC_INCREMENT, 1157 }, 1158 }; 1159 1160 static int rockchip_thermal_probe(struct udevice *dev) 1161 { 1162 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 1163 struct rockchip_tsadc_chip *tsadc; 1164 struct clk clk; 1165 int ret, i, shut_temp; 1166 1167 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 1168 ret = clk_set_defaults(dev); 1169 if (ret) 1170 printf("%s clk_set_defaults failed %d\n", __func__, ret); 1171 1172 if (soc_is_rk3308bs() || soc_is_px30s()) { 1173 ret = clk_get_by_name(dev, "tsadc", &clk); 1174 if (ret) { 1175 printf("%s get tsadc clk fail\n", __func__); 1176 return -EINVAL; 1177 } 1178 ret = clk_set_rate(&clk, 4000000); 1179 if (ret < 0) { 1180 printf("%s: failed to set tsadc clk rate for %s\n", 1181 __func__, dev_read_name(dev)); 1182 return -EINVAL; 1183 } 1184 } 1185 if (soc_is_rk3308bs()) 1186 tsadc = (struct rockchip_tsadc_chip *)&rk3308bs_tsadc_data; 1187 else if (soc_is_px30s()) 1188 tsadc = (struct rockchip_tsadc_chip *)&px30s_tsadc_data; 1189 else 1190 tsadc = (struct rockchip_tsadc_chip *)dev_get_driver_data(dev); 1191 1192 priv->data = tsadc; 1193 1194 priv->tshut_mode = dev_read_u32_default(dev, 1195 "rockchip,hw-tshut-mode", 1196 -1); 1197 if (priv->tshut_mode < 0) 1198 priv->tshut_mode = priv->data->tshut_mode; 1199 1200 priv->tshut_polarity = dev_read_u32_default(dev, 1201 "rockchip,hw-tshut-polarity", 1202 -1); 1203 if (priv->tshut_polarity < 0) 1204 priv->tshut_polarity = tsadc->tshut_polarity; 1205 1206 if (priv->tshut_mode == TSHUT_MODE_GPIO) 1207 pinctrl_select_state(dev, "otpout"); 1208 else if (soc_is_rk3308()) 1209 pinctrl_select_state(dev, "gpio"); 1210 1211 tsadc->tsadc_init(dev); 1212 tsadc->irq_ack(dev); 1213 1214 shut_temp = dev_read_u32_default(dev, "rockchip,hw-tshut-temp", -1); 1215 if (shut_temp < 0) 1216 shut_temp = 120000; 1217 1218 for (i = 0; i < tsadc->chn_num; i++) { 1219 tsadc->set_alarm_temp(dev, i, tsadc->tshut_temp); 1220 tsadc->set_tshut_temp(dev, i, shut_temp); 1221 if (priv->tshut_mode == TSHUT_MODE_GPIO) 1222 tsadc->set_tshut_mode(dev, i, TSHUT_MODE_GPIO); 1223 else 1224 tsadc->set_tshut_mode(dev, i, TSHUT_MODE_CRU); 1225 } 1226 1227 tsadc->tsadc_control(dev, true); 1228 if (soc_is_rk3308bs() || soc_is_px30s()) 1229 mdelay(3); 1230 else 1231 udelay(1000); 1232 1233 debug("tsadc probed successfully\n"); 1234 1235 return 0; 1236 } 1237 1238 static int rockchip_thermal_ofdata_to_platdata(struct udevice *dev) 1239 { 1240 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 1241 1242 priv->base = dev_read_addr_ptr(dev); 1243 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1244 1245 return 0; 1246 } 1247 1248 static const struct rockchip_tsadc_chip rk1808_tsadc_data = { 1249 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1250 .chn_num = 1, /* one channel for tsadc */ 1251 1252 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1253 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1254 .tshut_temp = 95000, 1255 1256 .tsadc_init = tsadc_init_v2, 1257 .tsadc_control = tsadc_control_v3, 1258 .tsadc_get_temp = tsadc_get_temp_v2, 1259 .irq_ack = tsadc_irq_ack_v3, 1260 .set_alarm_temp = tsadc_alarm_temp_v2, 1261 .set_tshut_temp = tsadc_tshut_temp_v2, 1262 .set_tshut_mode = tsadc_tshut_mode_v2, 1263 1264 .table = { 1265 .id = rk1808_code_table, 1266 .length = ARRAY_SIZE(rk1808_code_table), 1267 .data_mask = TSADCV2_DATA_MASK, 1268 .mode = ADC_INCREMENT, 1269 }, 1270 }; 1271 1272 static const struct rockchip_tsadc_chip rk3228_tsadc_data = { 1273 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1274 .chn_num = 1, /* one channel for tsadc */ 1275 1276 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1277 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1278 .tshut_temp = 95000, 1279 1280 .tsadc_init = tsadc_init_v2, 1281 .tsadc_control = tsadc_control_v3, 1282 .tsadc_get_temp = tsadc_get_temp_v2, 1283 .irq_ack = tsadc_irq_ack_v3, 1284 .set_alarm_temp = tsadc_alarm_temp_v2, 1285 .set_tshut_temp = tsadc_tshut_temp_v2, 1286 .set_tshut_mode = tsadc_tshut_mode_v2, 1287 1288 .table = { 1289 .id = rk3228_code_table, 1290 .length = ARRAY_SIZE(rk3228_code_table), 1291 .data_mask = TSADCV3_DATA_MASK, 1292 .mode = ADC_INCREMENT, 1293 }, 1294 }; 1295 1296 static const struct rockchip_tsadc_chip rk3288_tsadc_data = { 1297 .chn_id[SENSOR_CPU] = 1, /* cpu sensor is channel 1 */ 1298 .chn_id[SENSOR_GPU] = 2, /* gpu sensor is channel 2 */ 1299 .chn_num = 2, /* two channels for tsadc */ 1300 1301 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1302 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1303 .tshut_temp = 95000, 1304 1305 .tsadc_init = tsadc_init_v2, 1306 .tsadc_control = tsadc_control_v2, 1307 .tsadc_get_temp = tsadc_get_temp_v3, 1308 .irq_ack = tsadc_irq_ack_v2, 1309 .set_alarm_temp = tsadc_alarm_temp_v2, 1310 .set_tshut_temp = tsadc_tshut_temp_v2, 1311 .set_tshut_mode = tsadc_tshut_mode_v2, 1312 1313 .table = { 1314 .id = rk3288_code_table, 1315 .length = ARRAY_SIZE(rk3288_code_table), 1316 .data_mask = TSADCV2_DATA_MASK, 1317 .mode = ADC_DECREMENT, 1318 }, 1319 }; 1320 1321 static const struct rockchip_tsadc_chip rk3308_tsadc_data = { 1322 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1323 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1324 .chn_num = 2, /* 2 channels for tsadc */ 1325 1326 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ 1327 .tshut_temp = 95000, 1328 1329 .tsadc_init = tsadc_init_v4, 1330 .tsadc_control = tsadc_control_v3, 1331 .tsadc_get_temp = tsadc_get_temp_v2, 1332 .irq_ack = tsadc_irq_ack_v3, 1333 .set_alarm_temp = tsadc_alarm_temp_v2, 1334 .set_tshut_temp = tsadc_tshut_temp_v2, 1335 .set_tshut_mode = tsadc_tshut_mode_v2, 1336 1337 .table = { 1338 .id = rk3328_code_table, 1339 .length = ARRAY_SIZE(rk3328_code_table), 1340 .data_mask = TSADCV2_DATA_MASK, 1341 .mode = ADC_INCREMENT, 1342 }, 1343 }; 1344 1345 static const struct rockchip_tsadc_chip px30_tsadc_data = { 1346 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1347 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1348 .chn_num = 2, /* 2 channels for tsadc */ 1349 1350 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ 1351 .tshut_temp = 95000, 1352 1353 .tsadc_init = tsadc_init_v4, 1354 .tsadc_control = tsadc_control_v3, 1355 .tsadc_get_temp = tsadc_get_temp_v2, 1356 .irq_ack = tsadc_irq_ack_v3, 1357 .set_alarm_temp = tsadc_alarm_temp_v2, 1358 .set_tshut_temp = tsadc_tshut_temp_v2, 1359 .set_tshut_mode = tsadc_tshut_mode_v2, 1360 1361 .table = { 1362 .id = rk3328_code_table, 1363 .length = ARRAY_SIZE(rk3328_code_table), 1364 .data_mask = TSADCV2_DATA_MASK, 1365 .mode = ADC_INCREMENT, 1366 }, 1367 }; 1368 1369 static const struct rockchip_tsadc_chip rk3328_tsadc_data = { 1370 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1371 .chn_num = 1, /* one channels for tsadc */ 1372 1373 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ 1374 .tshut_temp = 95000, 1375 1376 .tsadc_init = tsadc_init_v2, 1377 .tsadc_control = tsadc_control_v3, 1378 .tsadc_get_temp = tsadc_get_temp_v2, 1379 .irq_ack = tsadc_irq_ack_v3, 1380 .set_alarm_temp = tsadc_alarm_temp_v2, 1381 .set_tshut_temp = tsadc_tshut_temp_v2, 1382 .set_tshut_mode = tsadc_tshut_mode_v2, 1383 1384 .table = { 1385 .id = rk3328_code_table, 1386 .length = ARRAY_SIZE(rk3328_code_table), 1387 .data_mask = TSADCV2_DATA_MASK, 1388 .mode = ADC_INCREMENT, 1389 }, 1390 }; 1391 1392 static const struct rockchip_tsadc_chip rk3366_tsadc_data = { 1393 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1394 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1395 .chn_num = 2, /* two channels for tsadc */ 1396 1397 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1398 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1399 .tshut_temp = 95000, 1400 1401 .tsadc_init = tsadc_init_v3, 1402 .tsadc_control = tsadc_control_v3, 1403 .tsadc_get_temp = tsadc_get_temp_v2, 1404 .irq_ack = tsadc_irq_ack_v3, 1405 .set_alarm_temp = tsadc_alarm_temp_v2, 1406 .set_tshut_temp = tsadc_tshut_temp_v2, 1407 .set_tshut_mode = tsadc_tshut_mode_v2, 1408 1409 .table = { 1410 .id = rk3228_code_table, 1411 .length = ARRAY_SIZE(rk3228_code_table), 1412 .data_mask = TSADCV3_DATA_MASK, 1413 .mode = ADC_INCREMENT, 1414 }, 1415 }; 1416 1417 static const struct rockchip_tsadc_chip rk3368_tsadc_data = { 1418 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1419 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1420 .chn_num = 2, /* two channels for tsadc */ 1421 1422 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1423 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1424 .tshut_temp = 95000, 1425 1426 .tsadc_init = tsadc_init_v2, 1427 .tsadc_control = tsadc_control_v2, 1428 .tsadc_get_temp = tsadc_get_temp_v2, 1429 .irq_ack = tsadc_irq_ack_v2, 1430 .set_alarm_temp = tsadc_alarm_temp_v2, 1431 .set_tshut_temp = tsadc_tshut_temp_v2, 1432 .set_tshut_mode = tsadc_tshut_mode_v2, 1433 1434 .table = { 1435 .id = rk3368_code_table, 1436 .length = ARRAY_SIZE(rk3368_code_table), 1437 .data_mask = TSADCV3_DATA_MASK, 1438 .mode = ADC_INCREMENT, 1439 }, 1440 }; 1441 1442 static const struct rockchip_tsadc_chip rk3399_tsadc_data = { 1443 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1444 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1445 .chn_num = 2, /* two channels for tsadc */ 1446 1447 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1448 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1449 .tshut_temp = 95000, 1450 1451 .tsadc_init = tsadc_init_v3, 1452 .tsadc_control = tsadc_control_v3, 1453 .tsadc_get_temp = tsadc_get_temp_v2, 1454 .irq_ack = tsadc_irq_ack_v3, 1455 .set_alarm_temp = tsadc_alarm_temp_v2, 1456 .set_tshut_temp = tsadc_tshut_temp_v2, 1457 .set_tshut_mode = tsadc_tshut_mode_v2, 1458 1459 .table = { 1460 .id = rk3399_code_table, 1461 .length = ARRAY_SIZE(rk3399_code_table), 1462 .data_mask = TSADCV3_DATA_MASK, 1463 .mode = ADC_INCREMENT, 1464 }, 1465 }; 1466 1467 static const struct rockchip_tsadc_chip rk3528_tsadc_data = { 1468 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1469 .chn_num = 1, /* one channels for tsadc */ 1470 1471 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via GPIO give PMIC */ 1472 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1473 .tshut_temp = 95000, 1474 1475 .tsadc_init = tsadc_init_v11, 1476 .tsadc_control = tsadc_control_v4, 1477 .tsadc_get_temp = tsadc_get_temp_v4, 1478 .irq_ack = tsadc_irq_ack_v4, 1479 .set_alarm_temp = tsadc_alarm_temp_v3, 1480 .set_tshut_temp = tsadc_tshut_temp_v3, 1481 .set_tshut_mode = tsadc_tshut_mode_v4, 1482 1483 .table = { 1484 .id = rk3528_code_table, 1485 .length = ARRAY_SIZE(rk3528_code_table), 1486 .data_mask = TSADCV2_DATA_MASK, 1487 .mode = ADC_INCREMENT, 1488 }, 1489 }; 1490 1491 static const struct rockchip_tsadc_chip rk3568_tsadc_data = { 1492 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1493 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1494 .chn_num = 2, /* two channels for tsadc */ 1495 1496 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1497 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1498 .tshut_temp = 95000, 1499 1500 .tsadc_init = tsadc_init_v7, 1501 .tsadc_control = tsadc_control_v3, 1502 .tsadc_get_temp = tsadc_get_temp_v2, 1503 .irq_ack = tsadc_irq_ack_v3, 1504 .set_alarm_temp = tsadc_alarm_temp_v2, 1505 .set_tshut_temp = tsadc_tshut_temp_v2, 1506 .set_tshut_mode = tsadc_tshut_mode_v2, 1507 1508 .table = { 1509 .id = rk3568_code_table, 1510 .length = ARRAY_SIZE(rk3568_code_table), 1511 .data_mask = TSADCV2_DATA_MASK, 1512 .mode = ADC_INCREMENT, 1513 }, 1514 }; 1515 1516 static const struct rockchip_tsadc_chip rk3588_tsadc_data = { 1517 /* top, big_core0, big_core1, little_core, center, gpu, npu */ 1518 .chn_id = {0, 1, 2, 3, 4, 5, 6}, 1519 .chn_num = 7, /* seven channels for tsadc */ 1520 1521 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1522 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1523 .tshut_temp = 95000, 1524 1525 .tsadc_init = tsadc_init_v8, 1526 .tsadc_control = tsadc_control_v4, 1527 .tsadc_get_temp = tsadc_get_temp_v4, 1528 .irq_ack = tsadc_irq_ack_v4, 1529 .set_alarm_temp = tsadc_alarm_temp_v3, 1530 .set_tshut_temp = tsadc_tshut_temp_v3, 1531 .set_tshut_mode = tsadc_tshut_mode_v4, 1532 1533 .table = { 1534 .id = rk3588_code_table, 1535 .length = ARRAY_SIZE(rk3588_code_table), 1536 .data_mask = TSADCV4_DATA_MASK, 1537 .mode = ADC_INCREMENT, 1538 }, 1539 }; 1540 1541 static const struct udevice_id rockchip_thermal_match[] = { 1542 { 1543 .compatible = "rockchip,px30-tsadc", 1544 .data = (ulong)&px30_tsadc_data, 1545 }, 1546 { 1547 .compatible = "rockchip,px30s-tsadc", 1548 .data = (ulong)&px30s_tsadc_data, 1549 }, 1550 { 1551 .compatible = "rockchip,rk1808-tsadc", 1552 .data = (ulong)&rk1808_tsadc_data, 1553 }, 1554 { 1555 .compatible = "rockchip,rk3228-tsadc", 1556 .data = (ulong)&rk3228_tsadc_data, 1557 }, 1558 { 1559 .compatible = "rockchip,rk3288-tsadc", 1560 .data = (ulong)&rk3288_tsadc_data, 1561 }, 1562 { 1563 .compatible = "rockchip,rk3308-tsadc", 1564 .data = (ulong)&rk3308_tsadc_data, 1565 }, 1566 { 1567 .compatible = "rockchip,rk3308bs-tsadc", 1568 .data = (ulong)&rk3308bs_tsadc_data, 1569 }, 1570 { 1571 .compatible = "rockchip,rk3328-tsadc", 1572 .data = (ulong)&rk3328_tsadc_data, 1573 }, 1574 { 1575 .compatible = "rockchip,rk3366-tsadc", 1576 .data = (ulong)&rk3366_tsadc_data, 1577 }, 1578 { 1579 .compatible = "rockchip,rk3368-tsadc", 1580 .data = (ulong)&rk3368_tsadc_data, 1581 }, 1582 { 1583 .compatible = "rockchip,rk3399-tsadc", 1584 .data = (ulong)&rk3399_tsadc_data, 1585 }, 1586 { 1587 .compatible = "rockchip,rk3528-tsadc", 1588 .data = (ulong)&rk3528_tsadc_data, 1589 }, 1590 { 1591 .compatible = "rockchip,rk3568-tsadc", 1592 .data = (ulong)&rk3568_tsadc_data, 1593 }, 1594 { 1595 .compatible = "rockchip,rk3588-tsadc", 1596 .data = (ulong)&rk3588_tsadc_data, 1597 }, 1598 { /* end */ }, 1599 }; 1600 1601 U_BOOT_DRIVER(rockchip_thermal) = { 1602 .name = "rockchip_thermal", 1603 .id = UCLASS_THERMAL, 1604 .of_match = rockchip_thermal_match, 1605 .priv_auto_alloc_size = sizeof(struct rockchip_thermal_priv), 1606 .ofdata_to_platdata = rockchip_thermal_ofdata_to_platdata, 1607 .ops = &rockchip_thermal_ops, 1608 .probe = rockchip_thermal_probe, 1609 }; 1610