1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6 #include <common.h> 7 #include <bitfield.h> 8 #include <thermal.h> 9 #include <dm.h> 10 #include <dm/pinctrl.h> 11 #include <div64.h> 12 #include <errno.h> 13 #include <syscon.h> 14 #include <asm/arch/clock.h> 15 #include <asm/arch/cpu.h> 16 #include <asm/arch/hardware.h> 17 #include <asm/io.h> 18 #include <dm/lists.h> 19 #include <clk.h> 20 #include <clk-uclass.h> 21 #include <reset.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 /** 26 * If the temperature over a period of time High, 27 * the resulting TSHUT gave CRU module,let it reset the entire chip, 28 * or via GPIO give PMIC. 29 */ 30 enum tshut_mode { 31 TSHUT_MODE_CRU = 0, 32 TSHUT_MODE_GPIO, 33 }; 34 35 /** 36 * The system Temperature Sensors tshut(tshut) polarity 37 * the bit 8 is tshut polarity. 38 * 0: low active, 1: high active 39 */ 40 enum tshut_polarity { 41 TSHUT_LOW_ACTIVE = 0, 42 TSHUT_HIGH_ACTIVE, 43 }; 44 45 /** 46 * The conversion table has the adc value and temperature. 47 * ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table) 48 * ADC_INCREMENT: the adc value is incremental.(e.g. rk3368_code_table) 49 */ 50 enum adc_sort_mode { 51 ADC_DECREMENT = 0, 52 ADC_INCREMENT, 53 }; 54 55 #define SOC_MAX_SENSORS 7 56 57 #define TSADCV2_USER_CON 0x00 58 #define TSADCV2_AUTO_CON 0x04 59 #define TSADCV2_INT_EN 0x08 60 #define TSADCV2_INT_PD 0x0c 61 #define TSADCV3_AUTO_SRC_CON 0x0c 62 #define TSADCV3_HT_INT_EN 0x14 63 #define TSADCV3_HSHUT_GPIO_INT_EN 0x18 64 #define TSADCV3_HSHUT_CRU_INT_EN 0x1c 65 #define TSADCV3_INT_PD 0x24 66 #define TSADCV3_HSHUT_PD 0x28 67 #define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04) 68 #define TSADCV2_COMP_INT(chn) (0x30 + (chn) * 0x04) 69 #define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04) 70 #define TSADCV3_DATA(chn) (0x2c + (chn) * 0x04) 71 #define TSADCV3_COMP_INT(chn) (0x6c + (chn) * 0x04) 72 #define TSADCV3_COMP_SHUT(chn) (0x10c + (chn) * 0x04) 73 #define TSADCV2_HIGHT_INT_DEBOUNCE 0x60 74 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64 75 #define TSADCV3_HIGHT_INT_DEBOUNCE 0x14c 76 #define TSADCV3_HIGHT_TSHUT_DEBOUNCE 0x150 77 #define TSADCV2_AUTO_PERIOD 0x68 78 #define TSADCV2_AUTO_PERIOD_HT 0x6c 79 #define TSADCV3_AUTO_PERIOD 0x154 80 #define TSADCV3_AUTO_PERIOD_HT 0x158 81 82 #define TSADCV2_AUTO_EN BIT(0) 83 #define TSADCV2_AUTO_EN_MASK BIT(16) 84 #define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn)) 85 #define TSADCV3_AUTO_SRC_EN(chn) BIT(chn) 86 #define TSADCV3_AUTO_SRC_EN_MASK(chn) BIT(16 + (chn)) 87 #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8) 88 #define TSADCV2_AUTO_TSHUT_POLARITY_MASK BIT(24) 89 90 #define TSADCV3_AUTO_Q_SEL_EN BIT(1) 91 92 #define TSADCV2_INT_SRC_EN(chn) BIT(chn) 93 #define TSADCV2_INT_SRC_EN_MASK(chn) BIT(16 + (chn)) 94 #define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn)) 95 #define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn)) 96 97 #define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8) 98 #define TSADCV3_INT_PD_CLEAR_MASK ~BIT(16) 99 #define TSADCV4_INT_PD_CLEAR_MASK 0xffffffff 100 101 #define TSADCV2_DATA_MASK 0xfff 102 #define TSADCV3_DATA_MASK 0x3ff 103 #define TSADCV4_DATA_MASK 0x1ff 104 105 #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4 106 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4 107 #define TSADCV2_AUTO_PERIOD_TIME 250 108 #define TSADCV2_AUTO_PERIOD_HT_TIME 50 109 #define TSADCV3_AUTO_PERIOD_TIME 1875 110 #define TSADCV3_AUTO_PERIOD_HT_TIME 1875 111 #define TSADCV5_AUTO_PERIOD_TIME 1622 /* 2.5ms */ 112 #define TSADCV5_AUTO_PERIOD_HT_TIME 1622 /* 2.5ms */ 113 #define TSADCV6_AUTO_PERIOD_TIME 5000 /* 2.5ms */ 114 #define TSADCV6_AUTO_PERIOD_HT_TIME 5000 /* 2.5ms */ 115 116 #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */ 117 #define TSADCV5_USER_INTER_PD_SOC 0xfc0 /* 97us, at least 90us */ 118 119 #define GRF_SARADC_TESTBIT 0x0e644 120 #define GRF_TSADC_TESTBIT_L 0x0e648 121 #define GRF_TSADC_TESTBIT_H 0x0e64c 122 123 #define PX30_GRF_SOC_CON0 0x0400 124 #define PX30_GRF_SOC_CON2 0x0408 125 126 #define RK3568_GRF_TSADC_CON 0x0600 127 #define RK3568_GRF_TSADC_ANA_REG0 (0x10001 << 0) 128 #define RK3568_GRF_TSADC_ANA_REG1 (0x10001 << 1) 129 #define RK3568_GRF_TSADC_ANA_REG2 (0x10001 << 2) 130 #define RK3568_GRF_TSADC_TSEN (0x10001 << 8) 131 132 #define GRF_SARADC_TESTBIT_ON (0x10001 << 2) 133 #define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2) 134 #define GRF_TSADC_VCM_EN_L (0x10001 << 7) 135 #define GRF_TSADC_VCM_EN_H (0x10001 << 7) 136 137 #define GRF_CON_TSADC_CH_INV (0x10001 << 1) 138 #define PX30S_TSADC_TDC_MODE (0x10001 << 4) 139 140 #define MIN_TEMP (-40000) 141 #define LOWEST_TEMP (-273000) 142 #define MAX_TEMP (125000) 143 #define MAX_ENV_TEMP (85000) 144 145 #define BASE (1024) 146 #define BASE_SHIFT (10) 147 #define START_DEBOUNCE_COUNT (100) 148 #define HIGHER_DEBOUNCE_TEMP (30000) 149 #define LOWER_DEBOUNCE_TEMP (15000) 150 151 /** 152 * struct tsadc_table - hold information about code and temp mapping 153 * @code: raw code from tsadc ip 154 * @temp: the mapping temperature 155 */ 156 157 struct tsadc_table { 158 unsigned long code; 159 int temp; 160 }; 161 162 struct chip_tsadc_table { 163 const struct tsadc_table *id; 164 unsigned int length; 165 u32 data_mask; 166 /* Tsadc is linear, using linear parameters */ 167 int knum; 168 int bnum; 169 enum adc_sort_mode mode; 170 }; 171 172 enum sensor_id { 173 SENSOR_CPU = 0, 174 SENSOR_GPU, 175 }; 176 177 struct rockchip_tsadc_chip { 178 /* The sensor id of chip correspond to the ADC channel */ 179 int chn_id[SOC_MAX_SENSORS]; 180 int chn_num; 181 fdt_addr_t base; 182 fdt_addr_t grf; 183 184 /* The hardware-controlled tshut property */ 185 int tshut_temp; 186 enum tshut_mode tshut_mode; 187 enum tshut_polarity tshut_polarity; 188 189 void (*tsadc_control)(struct udevice *dev, bool enable); 190 void (*tsadc_init)(struct udevice *dev); 191 int (*tsadc_get_temp)(struct udevice *dev, int chn, 192 int *temp); 193 void (*irq_ack)(struct udevice *dev); 194 void (*set_alarm_temp)(struct udevice *dev, 195 int chn, int temp); 196 void (*set_tshut_temp)(struct udevice *dev, 197 int chn, int temp); 198 void (*set_tshut_mode)(struct udevice *dev, int chn, enum tshut_mode m); 199 struct chip_tsadc_table table; 200 }; 201 202 struct rockchip_thermal_priv { 203 void *base; 204 void *grf; 205 enum tshut_mode tshut_mode; 206 enum tshut_polarity tshut_polarity; 207 const struct rockchip_tsadc_chip *data; 208 }; 209 210 static const struct tsadc_table rk1808_code_table[] = { 211 {0, -40000}, 212 {3455, -40000}, 213 {3463, -35000}, 214 {3471, -30000}, 215 {3479, -25000}, 216 {3487, -20000}, 217 {3495, -15000}, 218 {3503, -10000}, 219 {3511, -5000}, 220 {3519, 0}, 221 {3527, 5000}, 222 {3535, 10000}, 223 {3543, 15000}, 224 {3551, 20000}, 225 {3559, 25000}, 226 {3567, 30000}, 227 {3576, 35000}, 228 {3584, 40000}, 229 {3592, 45000}, 230 {3600, 50000}, 231 {3609, 55000}, 232 {3617, 60000}, 233 {3625, 65000}, 234 {3633, 70000}, 235 {3642, 75000}, 236 {3650, 80000}, 237 {3659, 85000}, 238 {3667, 90000}, 239 {3675, 95000}, 240 {3684, 100000}, 241 {3692, 105000}, 242 {3701, 110000}, 243 {3709, 115000}, 244 {3718, 120000}, 245 {3726, 125000}, 246 {TSADCV2_DATA_MASK, 125000}, 247 }; 248 249 static const struct tsadc_table rk3228_code_table[] = { 250 {0, -40000}, 251 {588, -40000}, 252 {593, -35000}, 253 {598, -30000}, 254 {603, -25000}, 255 {608, -20000}, 256 {613, -15000}, 257 {618, -10000}, 258 {623, -5000}, 259 {629, 0}, 260 {634, 5000}, 261 {639, 10000}, 262 {644, 15000}, 263 {649, 20000}, 264 {654, 25000}, 265 {660, 30000}, 266 {665, 35000}, 267 {670, 40000}, 268 {675, 45000}, 269 {681, 50000}, 270 {686, 55000}, 271 {691, 60000}, 272 {696, 65000}, 273 {702, 70000}, 274 {707, 75000}, 275 {712, 80000}, 276 {717, 85000}, 277 {723, 90000}, 278 {728, 95000}, 279 {733, 100000}, 280 {738, 105000}, 281 {744, 110000}, 282 {749, 115000}, 283 {754, 120000}, 284 {760, 125000}, 285 {TSADCV2_DATA_MASK, 125000}, 286 }; 287 288 static const struct tsadc_table rk3288_code_table[] = { 289 {TSADCV2_DATA_MASK, -40000}, 290 {3800, -40000}, 291 {3792, -35000}, 292 {3783, -30000}, 293 {3774, -25000}, 294 {3765, -20000}, 295 {3756, -15000}, 296 {3747, -10000}, 297 {3737, -5000}, 298 {3728, 0}, 299 {3718, 5000}, 300 {3708, 10000}, 301 {3698, 15000}, 302 {3688, 20000}, 303 {3678, 25000}, 304 {3667, 30000}, 305 {3656, 35000}, 306 {3645, 40000}, 307 {3634, 45000}, 308 {3623, 50000}, 309 {3611, 55000}, 310 {3600, 60000}, 311 {3588, 65000}, 312 {3575, 70000}, 313 {3563, 75000}, 314 {3550, 80000}, 315 {3537, 85000}, 316 {3524, 90000}, 317 {3510, 95000}, 318 {3496, 100000}, 319 {3482, 105000}, 320 {3467, 110000}, 321 {3452, 115000}, 322 {3437, 120000}, 323 {3421, 125000}, 324 }; 325 326 static const struct tsadc_table rk3328_code_table[] = { 327 {0, -40000}, 328 {296, -40000}, 329 {304, -35000}, 330 {313, -30000}, 331 {331, -20000}, 332 {340, -15000}, 333 {349, -10000}, 334 {359, -5000}, 335 {368, 0}, 336 {378, 5000}, 337 {388, 10000}, 338 {398, 15000}, 339 {408, 20000}, 340 {418, 25000}, 341 {429, 30000}, 342 {440, 35000}, 343 {451, 40000}, 344 {462, 45000}, 345 {473, 50000}, 346 {485, 55000}, 347 {496, 60000}, 348 {508, 65000}, 349 {521, 70000}, 350 {533, 75000}, 351 {546, 80000}, 352 {559, 85000}, 353 {572, 90000}, 354 {586, 95000}, 355 {600, 100000}, 356 {614, 105000}, 357 {629, 110000}, 358 {644, 115000}, 359 {659, 120000}, 360 {675, 125000}, 361 {TSADCV2_DATA_MASK, 125000}, 362 }; 363 364 static const struct tsadc_table rk3368_code_table[] = { 365 {0, -40000}, 366 {106, -40000}, 367 {108, -35000}, 368 {110, -30000}, 369 {112, -25000}, 370 {114, -20000}, 371 {116, -15000}, 372 {118, -10000}, 373 {120, -5000}, 374 {122, 0}, 375 {124, 5000}, 376 {126, 10000}, 377 {128, 15000}, 378 {130, 20000}, 379 {132, 25000}, 380 {134, 30000}, 381 {136, 35000}, 382 {138, 40000}, 383 {140, 45000}, 384 {142, 50000}, 385 {144, 55000}, 386 {146, 60000}, 387 {148, 65000}, 388 {150, 70000}, 389 {152, 75000}, 390 {154, 80000}, 391 {156, 85000}, 392 {158, 90000}, 393 {160, 95000}, 394 {162, 100000}, 395 {163, 105000}, 396 {165, 110000}, 397 {167, 115000}, 398 {169, 120000}, 399 {171, 125000}, 400 {TSADCV3_DATA_MASK, 125000}, 401 }; 402 403 static const struct tsadc_table rk3399_code_table[] = { 404 {0, -40000}, 405 {402, -40000}, 406 {410, -35000}, 407 {419, -30000}, 408 {427, -25000}, 409 {436, -20000}, 410 {444, -15000}, 411 {453, -10000}, 412 {461, -5000}, 413 {470, 0}, 414 {478, 5000}, 415 {487, 10000}, 416 {496, 15000}, 417 {504, 20000}, 418 {513, 25000}, 419 {521, 30000}, 420 {530, 35000}, 421 {538, 40000}, 422 {547, 45000}, 423 {555, 50000}, 424 {564, 55000}, 425 {573, 60000}, 426 {581, 65000}, 427 {590, 70000}, 428 {599, 75000}, 429 {607, 80000}, 430 {616, 85000}, 431 {624, 90000}, 432 {633, 95000}, 433 {642, 100000}, 434 {650, 105000}, 435 {659, 110000}, 436 {668, 115000}, 437 {677, 120000}, 438 {685, 125000}, 439 {TSADCV3_DATA_MASK, 125000}, 440 }; 441 442 static const struct tsadc_table rk3568_code_table[] = { 443 {0, -40000}, 444 {1584, -40000}, 445 {1620, -35000}, 446 {1652, -30000}, 447 {1688, -25000}, 448 {1720, -20000}, 449 {1756, -15000}, 450 {1788, -10000}, 451 {1824, -5000}, 452 {1856, 0}, 453 {1892, 5000}, 454 {1924, 10000}, 455 {1956, 15000}, 456 {1992, 20000}, 457 {2024, 25000}, 458 {2060, 30000}, 459 {2092, 35000}, 460 {2128, 40000}, 461 {2160, 45000}, 462 {2196, 50000}, 463 {2228, 55000}, 464 {2264, 60000}, 465 {2300, 65000}, 466 {2332, 70000}, 467 {2368, 75000}, 468 {2400, 80000}, 469 {2436, 85000}, 470 {2468, 90000}, 471 {2500, 95000}, 472 {2536, 100000}, 473 {2572, 105000}, 474 {2604, 110000}, 475 {2636, 115000}, 476 {2672, 120000}, 477 {2704, 125000}, 478 {TSADCV2_DATA_MASK, 125000}, 479 }; 480 481 static const struct tsadc_table rk3588_code_table[] = { 482 {0, -40000}, 483 {215, -40000}, 484 {285, 25000}, 485 {350, 85000}, 486 {395, 125000}, 487 {TSADCV4_DATA_MASK, 125000}, 488 }; 489 490 /* 491 * Struct used for matching a device 492 */ 493 struct of_device_id { 494 char compatible[32]; 495 const void *data; 496 }; 497 498 static int tsadc_code_to_temp(struct chip_tsadc_table *table, u32 code, 499 int *temp) 500 { 501 unsigned int low = 1; 502 unsigned int high = table->length - 1; 503 unsigned int mid = (low + high) / 2; 504 unsigned int num; 505 unsigned long denom; 506 507 if (table->knum) { 508 *temp = (((int)code - table->bnum) * 10000 / table->knum) * 100; 509 if (*temp < MIN_TEMP || *temp > MAX_TEMP) 510 return -EAGAIN; 511 return 0; 512 } 513 514 switch (table->mode) { 515 case ADC_DECREMENT: 516 code &= table->data_mask; 517 if (code < table->id[high].code) 518 return -EAGAIN; /* Incorrect reading */ 519 520 while (low <= high) { 521 if (code >= table->id[mid].code && 522 code < table->id[mid - 1].code) 523 break; 524 else if (code < table->id[mid].code) 525 low = mid + 1; 526 else 527 high = mid - 1; 528 529 mid = (low + high) / 2; 530 } 531 break; 532 case ADC_INCREMENT: 533 code &= table->data_mask; 534 if (code < table->id[low].code) 535 return -EAGAIN; /* Incorrect reading */ 536 537 while (low <= high) { 538 if (code <= table->id[mid].code && 539 code > table->id[mid - 1].code) 540 break; 541 else if (code > table->id[mid].code) 542 low = mid + 1; 543 else 544 high = mid - 1; 545 546 mid = (low + high) / 2; 547 } 548 break; 549 default: 550 printf("%s: Invalid the conversion table mode=%d\n", 551 __func__, table->mode); 552 return -EINVAL; 553 } 554 555 /* 556 * The 5C granularity provided by the table is too much. Let's 557 * assume that the relationship between sensor readings and 558 * temperature between 2 table entries is linear and interpolate 559 * to produce less granular result. 560 */ 561 num = table->id[mid].temp - table->id[mid - 1].temp; 562 num *= abs(table->id[mid - 1].code - code); 563 denom = abs(table->id[mid - 1].code - table->id[mid].code); 564 *temp = table->id[mid - 1].temp + (num / denom); 565 566 return 0; 567 } 568 569 static u32 tsadc_temp_to_code_v2(struct chip_tsadc_table table, 570 int temp) 571 { 572 int high, low, mid; 573 unsigned long num; 574 unsigned int denom; 575 u32 error = table.data_mask; 576 577 if (table.knum) 578 return (((temp / 1000) * table.knum) / 1000 + table.bnum); 579 580 low = 0; 581 high = table.length - 1; 582 mid = (high + low) / 2; 583 584 /* Return mask code data when the temp is over table range */ 585 if (temp < table.id[low].temp || temp > table.id[high].temp) 586 goto exit; 587 588 while (low <= high) { 589 if (temp == table.id[mid].temp) 590 return table.id[mid].code; 591 else if (temp < table.id[mid].temp) 592 high = mid - 1; 593 else 594 low = mid + 1; 595 mid = (low + high) / 2; 596 } 597 598 num = abs(table.id[mid + 1].code - table.id[mid].code); 599 num *= temp - table.id[mid].temp; 600 denom = table.id[mid + 1].temp - table.id[mid].temp; 601 602 switch (table.mode) { 603 case ADC_DECREMENT: 604 return table.id[mid].code - (num / denom); 605 case ADC_INCREMENT: 606 return table.id[mid].code + (num / denom); 607 default: 608 pr_err("%s: unknown table mode: %d\n", __func__, table.mode); 609 return error; 610 } 611 612 exit: 613 pr_err("%s: Invalid conversion table: code=%d, temperature=%d\n", 614 __func__, error, temp); 615 616 return error; 617 } 618 619 static void tsadc_irq_ack_v2(struct udevice *dev) 620 { 621 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 622 u32 val; 623 624 val = readl(priv->base + TSADCV2_INT_PD); 625 writel(val & TSADCV2_INT_PD_CLEAR_MASK, priv->base + TSADCV2_INT_PD); 626 } 627 628 static void tsadc_irq_ack_v3(struct udevice *dev) 629 { 630 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 631 u32 val; 632 633 val = readl(priv->base + TSADCV2_INT_PD); 634 writel(val & TSADCV3_INT_PD_CLEAR_MASK, priv->base + TSADCV2_INT_PD); 635 } 636 637 static void tsadc_irq_ack_v4(struct udevice *dev) 638 { 639 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 640 u32 val; 641 642 val = readl(priv->base + TSADCV3_INT_PD); 643 writel(val & TSADCV4_INT_PD_CLEAR_MASK, priv->base + TSADCV3_INT_PD); 644 val = readl(priv->base + TSADCV3_HSHUT_PD); 645 writel(val & TSADCV3_INT_PD_CLEAR_MASK, priv->base + TSADCV3_HSHUT_PD); 646 } 647 648 static void tsadc_control_v2(struct udevice *dev, bool enable) 649 { 650 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 651 u32 val; 652 653 val = readl(priv->base + TSADCV2_AUTO_CON); 654 if (enable) 655 val |= TSADCV2_AUTO_EN; 656 else 657 val &= ~TSADCV2_AUTO_EN; 658 659 writel(val, priv->base + TSADCV2_AUTO_CON); 660 } 661 662 static void tsadc_control_v3(struct udevice *dev, bool enable) 663 { 664 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 665 u32 val; 666 667 val = readl(priv->base + TSADCV2_AUTO_CON); 668 if (enable) 669 val |= TSADCV2_AUTO_EN | TSADCV3_AUTO_Q_SEL_EN; 670 else 671 val &= ~TSADCV2_AUTO_EN; 672 673 writel(val, priv->base + TSADCV2_AUTO_CON); 674 } 675 676 static void tsadc_control_v4(struct udevice *dev, bool enable) 677 { 678 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 679 u32 val; 680 681 if (enable) 682 val = TSADCV2_AUTO_EN | TSADCV2_AUTO_EN_MASK; 683 else 684 val = TSADCV2_AUTO_EN_MASK; 685 686 writel(val, priv->base + TSADCV2_AUTO_CON); 687 } 688 689 static void tsadc_init_v2(struct udevice *dev) 690 { 691 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 692 693 writel(TSADCV2_AUTO_PERIOD_TIME, 694 priv->base + TSADCV2_AUTO_PERIOD); 695 writel(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, 696 priv->base + TSADCV2_HIGHT_INT_DEBOUNCE); 697 writel(TSADCV2_AUTO_PERIOD_HT_TIME, 698 priv->base + TSADCV2_AUTO_PERIOD_HT); 699 writel(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, 700 priv->base + TSADCV2_HIGHT_TSHUT_DEBOUNCE); 701 702 if (priv->tshut_polarity == TSHUT_HIGH_ACTIVE) 703 writel(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 704 priv->base + TSADCV2_AUTO_CON); 705 else 706 writel(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 707 priv->base + TSADCV2_AUTO_CON); 708 } 709 710 static void tsadc_init_v3(struct udevice *dev) 711 { 712 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 713 714 if (!IS_ERR(priv->grf)) { 715 writel(GRF_TSADC_VCM_EN_L, priv->grf + GRF_TSADC_TESTBIT_L); 716 writel(GRF_TSADC_VCM_EN_H, priv->grf + GRF_TSADC_TESTBIT_H); 717 718 udelay(100);/* The spec note says at least 15 us */ 719 writel(GRF_SARADC_TESTBIT_ON, priv->grf + GRF_SARADC_TESTBIT); 720 writel(GRF_TSADC_TESTBIT_H_ON, priv->grf + GRF_TSADC_TESTBIT_H); 721 udelay(200);/* The spec note says at least 90 us */ 722 } 723 tsadc_init_v2(dev); 724 } 725 726 static void __maybe_unused tsadc_init_v5(struct udevice *dev) 727 { 728 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 729 730 /* Set interleave value to workround ic time sync issue */ 731 writel(TSADCV2_USER_INTER_PD_SOC, priv->base + 732 TSADCV2_USER_CON); 733 tsadc_init_v2(dev); 734 } 735 736 static void tsadc_init_v4(struct udevice *dev) 737 { 738 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 739 740 tsadc_init_v2(dev); 741 if (!IS_ERR(priv->grf)) 742 writel(GRF_CON_TSADC_CH_INV, priv->grf + PX30_GRF_SOC_CON2); 743 } 744 745 static void tsadc_init_v7(struct udevice *dev) 746 { 747 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 748 749 writel(TSADCV5_USER_INTER_PD_SOC, 750 priv->base + TSADCV2_USER_CON); 751 writel(TSADCV5_AUTO_PERIOD_TIME, 752 priv->base + TSADCV2_AUTO_PERIOD); 753 writel(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, 754 priv->base + TSADCV2_HIGHT_INT_DEBOUNCE); 755 writel(TSADCV5_AUTO_PERIOD_HT_TIME, 756 priv->base + TSADCV2_AUTO_PERIOD_HT); 757 writel(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, 758 priv->base + TSADCV2_HIGHT_TSHUT_DEBOUNCE); 759 760 if (priv->tshut_polarity == TSHUT_HIGH_ACTIVE) 761 writel(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 762 priv->base + TSADCV2_AUTO_CON); 763 else 764 writel(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 765 priv->base + TSADCV2_AUTO_CON); 766 767 if (!IS_ERR(priv->grf)) { 768 writel(RK3568_GRF_TSADC_TSEN, 769 priv->grf + RK3568_GRF_TSADC_CON); 770 udelay(15); 771 writel(RK3568_GRF_TSADC_ANA_REG0, 772 priv->grf + RK3568_GRF_TSADC_CON); 773 writel(RK3568_GRF_TSADC_ANA_REG1, 774 priv->grf + RK3568_GRF_TSADC_CON); 775 writel(RK3568_GRF_TSADC_ANA_REG2, 776 priv->grf + RK3568_GRF_TSADC_CON); 777 udelay(200); 778 } 779 } 780 781 static void tsadc_init_v8(struct udevice *dev) 782 { 783 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 784 785 writel(TSADCV6_AUTO_PERIOD_TIME, priv->base + TSADCV3_AUTO_PERIOD); 786 writel(TSADCV6_AUTO_PERIOD_HT_TIME, 787 priv->base + TSADCV3_AUTO_PERIOD_HT); 788 writel(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, 789 priv->base + TSADCV3_HIGHT_INT_DEBOUNCE); 790 writel(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, 791 priv->base + TSADCV3_HIGHT_TSHUT_DEBOUNCE); 792 793 if (priv->tshut_polarity == TSHUT_HIGH_ACTIVE) 794 writel(TSADCV2_AUTO_TSHUT_POLARITY_HIGH | 795 TSADCV2_AUTO_TSHUT_POLARITY_MASK, 796 priv->base + TSADCV2_AUTO_CON); 797 else 798 writel(TSADCV2_AUTO_TSHUT_POLARITY_MASK, 799 priv->base + TSADCV2_AUTO_CON); 800 }; 801 802 static void tsadc_init_v9(struct udevice *dev) 803 { 804 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 805 806 tsadc_init_v2(dev); 807 if (!IS_ERR(priv->grf)) 808 writel(PX30S_TSADC_TDC_MODE, priv->grf + PX30_GRF_SOC_CON0); 809 } 810 811 static int tsadc_get_temp_v2(struct udevice *dev, 812 int chn, int *temp) 813 { 814 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 815 struct chip_tsadc_table table = priv->data->table; 816 u32 val; 817 818 val = readl(priv->base + TSADCV2_DATA(chn)); 819 820 return tsadc_code_to_temp(&table, val, temp); 821 } 822 823 static int predict_temp(int temp) 824 { 825 /* 826 * The deviation of prediction. the temperature will not change rapidly, 827 * so this cov_q is small 828 */ 829 int cov_q = 18; 830 /* 831 * The deviation of tsadc's reading, deviation of tsadc is very big when 832 * abnormal temperature is get 833 */ 834 int cov_r = 542; 835 836 int gain; 837 int temp_mid; 838 int temp_now; 839 int prob_mid; 840 int prob_now; 841 static int temp_last = LOWEST_TEMP; 842 static int prob_last = 160; 843 static int bounding_cnt; 844 845 /* 846 * init temp_last with a more suitable value, which mostly equals to 847 * temp reading from tsadc, but not higher than MAX_ENV_TEMP. If the 848 * temp is higher than MAX_ENV_TEMP, it is assumed to be abnormal 849 * value and temp_last is adjusted to MAX_ENV_TEMP. 850 */ 851 if (temp_last == LOWEST_TEMP) 852 temp_last = min(temp, MAX_ENV_TEMP); 853 854 /* 855 * Before START_DEBOUNCE_COUNT's samples of temperature, we consider 856 * tsadc is stable, i.e. after that, the temperature may be not stable 857 * and may have abnormal reading, so we set a bounding temperature. If 858 * the reading from tsadc is too big, we set the delta temperature of 859 * DEBOUNCE_TEMP/3 comparing to the last temperature. 860 */ 861 862 if (bounding_cnt++ > START_DEBOUNCE_COUNT) { 863 bounding_cnt = START_DEBOUNCE_COUNT; 864 if (temp - temp_last > HIGHER_DEBOUNCE_TEMP) 865 temp = temp_last + HIGHER_DEBOUNCE_TEMP / 3; 866 if (temp_last - temp > LOWER_DEBOUNCE_TEMP) 867 temp = temp_last - LOWER_DEBOUNCE_TEMP / 3; 868 } 869 870 temp_mid = temp_last; 871 872 /* calculate the probability of this time's prediction */ 873 prob_mid = prob_last + cov_q; 874 875 /* calculate the Kalman Gain */ 876 gain = (prob_mid * BASE) / (prob_mid + cov_r); 877 878 /* calculate the prediction of temperature */ 879 temp_now = (temp_mid * BASE + gain * (temp - temp_mid)) >> BASE_SHIFT; 880 881 /* 882 * Base on this time's Kalman Gain, ajust our probability of prediction 883 * for next time calculation 884 */ 885 prob_now = ((BASE - gain) * prob_mid) >> BASE_SHIFT; 886 887 prob_last = prob_now; 888 temp_last = temp_now; 889 890 return temp_last; 891 } 892 893 static int tsadc_get_temp_v3(struct udevice *dev, 894 int chn, int *temp) 895 { 896 int ret; 897 898 ret = tsadc_get_temp_v2(dev, chn, temp); 899 if (!ret) 900 *temp = predict_temp(*temp); 901 902 return ret; 903 } 904 905 static int tsadc_get_temp_v4(struct udevice *dev, int chn, int *temp) 906 { 907 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 908 struct chip_tsadc_table table = priv->data->table; 909 u32 val; 910 911 val = readl(priv->base + TSADCV3_DATA(chn)); 912 913 return tsadc_code_to_temp(&table, val, temp); 914 } 915 916 static void tsadc_alarm_temp_v2(struct udevice *dev, 917 int chn, int temp) 918 { 919 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 920 struct chip_tsadc_table table = priv->data->table; 921 u32 alarm_value, int_en; 922 923 alarm_value = tsadc_temp_to_code_v2(table, temp); 924 if (alarm_value == table.data_mask) 925 return; 926 927 writel(alarm_value, priv->base + TSADCV2_COMP_INT(chn)); 928 929 int_en = readl(priv->base + TSADCV2_INT_EN); 930 int_en |= TSADCV2_INT_SRC_EN(chn); 931 writel(int_en, priv->base + TSADCV2_INT_EN); 932 } 933 934 static void tsadc_alarm_temp_v3(struct udevice *dev, int chn, int temp) 935 { 936 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 937 struct chip_tsadc_table table = priv->data->table; 938 u32 alarm_value; 939 940 alarm_value = tsadc_temp_to_code_v2(table, temp); 941 if (alarm_value == table.data_mask) 942 return; 943 944 writel(alarm_value, priv->base + TSADCV3_COMP_INT(chn)); 945 writel(TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn), 946 priv->base + TSADCV3_HT_INT_EN); 947 } 948 949 static void tsadc_tshut_temp_v2(struct udevice *dev, 950 int chn, int temp) 951 { 952 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 953 struct chip_tsadc_table table = priv->data->table; 954 u32 tshut_value, val; 955 956 tshut_value = tsadc_temp_to_code_v2(table, temp); 957 if (tshut_value == table.data_mask) 958 return; 959 960 writel(tshut_value, priv->base + TSADCV2_COMP_SHUT(chn)); 961 962 /* TSHUT will be valid */ 963 val = readl(priv->base + TSADCV2_AUTO_CON); 964 writel(val | TSADCV2_AUTO_SRC_EN(chn), priv->base + TSADCV2_AUTO_CON); 965 } 966 967 static void tsadc_tshut_temp_v3(struct udevice *dev, int chn, int temp) 968 { 969 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 970 struct chip_tsadc_table table = priv->data->table; 971 u32 tshut_value; 972 973 tshut_value = tsadc_temp_to_code_v2(table, temp); 974 if (tshut_value == table.data_mask) 975 return; 976 977 writel(tshut_value, priv->base + TSADCV3_COMP_SHUT(chn)); 978 writel(TSADCV3_AUTO_SRC_EN(chn) | TSADCV3_AUTO_SRC_EN_MASK(chn), 979 priv->base + TSADCV3_AUTO_SRC_CON); 980 } 981 982 static void tsadc_tshut_mode_v2(struct udevice *dev, int chn, 983 enum tshut_mode mode) 984 { 985 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 986 u32 val; 987 988 val = readl(priv->base + TSADCV2_INT_EN); 989 if (mode == TSHUT_MODE_GPIO) { 990 val &= ~TSADCV2_SHUT_2CRU_SRC_EN(chn); 991 val |= TSADCV2_SHUT_2GPIO_SRC_EN(chn); 992 } else { 993 val &= ~TSADCV2_SHUT_2GPIO_SRC_EN(chn); 994 val |= TSADCV2_SHUT_2CRU_SRC_EN(chn); 995 } 996 997 writel(val, priv->base + TSADCV2_INT_EN); 998 } 999 1000 static void tsadc_tshut_mode_v4(struct udevice *dev, int chn, 1001 enum tshut_mode mode) 1002 { 1003 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 1004 u32 val_gpio, val_cru; 1005 1006 if (mode == TSHUT_MODE_GPIO) { 1007 val_gpio = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn); 1008 val_cru = TSADCV2_INT_SRC_EN_MASK(chn); 1009 } else { 1010 val_cru = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn); 1011 val_gpio = TSADCV2_INT_SRC_EN_MASK(chn); 1012 } 1013 writel(val_gpio, priv->base + TSADCV3_HSHUT_GPIO_INT_EN); 1014 writel(val_cru, priv->base + TSADCV3_HSHUT_CRU_INT_EN); 1015 } 1016 1017 int rockchip_thermal_get_temp(struct udevice *dev, int *temp) 1018 { 1019 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 1020 1021 priv->data->tsadc_get_temp(dev, 0, temp); 1022 1023 return 0; 1024 } 1025 1026 static const struct dm_thermal_ops rockchip_thermal_ops = { 1027 .get_temp = rockchip_thermal_get_temp, 1028 }; 1029 1030 static const struct rockchip_tsadc_chip px30s_tsadc_data = { 1031 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1032 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1033 .chn_num = 2, /* 2 channels for tsadc */ 1034 1035 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ 1036 .tshut_temp = 95000, 1037 1038 .tsadc_init = tsadc_init_v9, 1039 .tsadc_control = tsadc_control_v2, 1040 .tsadc_get_temp = tsadc_get_temp_v2, 1041 .irq_ack = tsadc_irq_ack_v3, 1042 .set_alarm_temp = tsadc_alarm_temp_v2, 1043 .set_tshut_temp = tsadc_tshut_temp_v2, 1044 .set_tshut_mode = tsadc_tshut_mode_v2, 1045 1046 .table = { 1047 .knum = 2699, 1048 .bnum = 2796, 1049 .data_mask = TSADCV2_DATA_MASK, 1050 .mode = ADC_INCREMENT, 1051 }, 1052 }; 1053 1054 static const struct rockchip_tsadc_chip rk3308bs_tsadc_data = { 1055 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1056 .chn_num = 1, /* 1 channels for tsadc */ 1057 1058 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ 1059 .tshut_temp = 95000, 1060 1061 .tsadc_init = tsadc_init_v2, 1062 .tsadc_control = tsadc_control_v2, 1063 .tsadc_get_temp = tsadc_get_temp_v2, 1064 .irq_ack = tsadc_irq_ack_v3, 1065 .set_alarm_temp = tsadc_alarm_temp_v2, 1066 .set_tshut_temp = tsadc_tshut_temp_v2, 1067 .set_tshut_mode = tsadc_tshut_mode_v2, 1068 1069 .table = { 1070 .knum = 2699, 1071 .bnum = 2796, 1072 .data_mask = TSADCV2_DATA_MASK, 1073 .mode = ADC_INCREMENT, 1074 }, 1075 }; 1076 1077 static int rockchip_thermal_probe(struct udevice *dev) 1078 { 1079 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 1080 struct rockchip_tsadc_chip *tsadc; 1081 struct clk clk; 1082 int ret, i, shut_temp; 1083 1084 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 1085 ret = clk_set_defaults(dev); 1086 if (ret) 1087 printf("%s clk_set_defaults failed %d\n", __func__, ret); 1088 1089 if (soc_is_rk3308bs() || soc_is_px30s()) { 1090 ret = clk_get_by_name(dev, "tsadc", &clk); 1091 if (ret) { 1092 printf("%s get tsadc clk fail\n", __func__); 1093 return -EINVAL; 1094 } 1095 ret = clk_set_rate(&clk, 4000000); 1096 if (ret < 0) { 1097 printf("%s: failed to set tsadc clk rate for %s\n", 1098 __func__, dev_read_name(dev)); 1099 return -EINVAL; 1100 } 1101 } 1102 if (soc_is_rk3308bs()) 1103 tsadc = (struct rockchip_tsadc_chip *)&rk3308bs_tsadc_data; 1104 else if (soc_is_px30s()) 1105 tsadc = (struct rockchip_tsadc_chip *)&px30s_tsadc_data; 1106 else 1107 tsadc = (struct rockchip_tsadc_chip *)dev_get_driver_data(dev); 1108 1109 priv->data = tsadc; 1110 1111 priv->tshut_mode = dev_read_u32_default(dev, 1112 "rockchip,hw-tshut-mode", 1113 -1); 1114 if (priv->tshut_mode < 0) 1115 priv->tshut_mode = priv->data->tshut_mode; 1116 1117 priv->tshut_polarity = dev_read_u32_default(dev, 1118 "rockchip,hw-tshut-polarity", 1119 -1); 1120 if (priv->tshut_polarity < 0) 1121 priv->tshut_polarity = tsadc->tshut_polarity; 1122 1123 if (priv->tshut_mode == TSHUT_MODE_GPIO) 1124 pinctrl_select_state(dev, "otpout"); 1125 else 1126 pinctrl_select_state(dev, "gpio"); 1127 1128 tsadc->tsadc_init(dev); 1129 tsadc->irq_ack(dev); 1130 1131 shut_temp = dev_read_u32_default(dev, "rockchip,hw-tshut-temp", -1); 1132 if (shut_temp < 0) 1133 shut_temp = 120000; 1134 1135 for (i = 0; i < tsadc->chn_num; i++) { 1136 tsadc->set_alarm_temp(dev, i, tsadc->tshut_temp); 1137 tsadc->set_tshut_temp(dev, i, shut_temp); 1138 if (priv->tshut_mode == TSHUT_MODE_GPIO) 1139 tsadc->set_tshut_mode(dev, i, TSHUT_MODE_GPIO); 1140 else 1141 tsadc->set_tshut_mode(dev, i, TSHUT_MODE_CRU); 1142 } 1143 1144 tsadc->tsadc_control(dev, true); 1145 if (soc_is_rk3308bs() || soc_is_px30s()) 1146 mdelay(3); 1147 else 1148 udelay(1000); 1149 1150 debug("tsadc probed successfully\n"); 1151 1152 return 0; 1153 } 1154 1155 static int rockchip_thermal_ofdata_to_platdata(struct udevice *dev) 1156 { 1157 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 1158 1159 priv->base = dev_read_addr_ptr(dev); 1160 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1161 1162 return 0; 1163 } 1164 1165 static const struct rockchip_tsadc_chip rk1808_tsadc_data = { 1166 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1167 .chn_num = 1, /* one channel for tsadc */ 1168 1169 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1170 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1171 .tshut_temp = 95000, 1172 1173 .tsadc_init = tsadc_init_v2, 1174 .tsadc_control = tsadc_control_v3, 1175 .tsadc_get_temp = tsadc_get_temp_v2, 1176 .irq_ack = tsadc_irq_ack_v3, 1177 .set_alarm_temp = tsadc_alarm_temp_v2, 1178 .set_tshut_temp = tsadc_tshut_temp_v2, 1179 .set_tshut_mode = tsadc_tshut_mode_v2, 1180 1181 .table = { 1182 .id = rk1808_code_table, 1183 .length = ARRAY_SIZE(rk1808_code_table), 1184 .data_mask = TSADCV2_DATA_MASK, 1185 .mode = ADC_INCREMENT, 1186 }, 1187 }; 1188 1189 static const struct rockchip_tsadc_chip rk3228_tsadc_data = { 1190 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1191 .chn_num = 1, /* one channel for tsadc */ 1192 1193 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1194 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1195 .tshut_temp = 95000, 1196 1197 .tsadc_init = tsadc_init_v2, 1198 .tsadc_control = tsadc_control_v3, 1199 .tsadc_get_temp = tsadc_get_temp_v2, 1200 .irq_ack = tsadc_irq_ack_v3, 1201 .set_alarm_temp = tsadc_alarm_temp_v2, 1202 .set_tshut_temp = tsadc_tshut_temp_v2, 1203 .set_tshut_mode = tsadc_tshut_mode_v2, 1204 1205 .table = { 1206 .id = rk3228_code_table, 1207 .length = ARRAY_SIZE(rk3228_code_table), 1208 .data_mask = TSADCV3_DATA_MASK, 1209 .mode = ADC_INCREMENT, 1210 }, 1211 }; 1212 1213 static const struct rockchip_tsadc_chip rk3288_tsadc_data = { 1214 .chn_id[SENSOR_CPU] = 1, /* cpu sensor is channel 1 */ 1215 .chn_id[SENSOR_GPU] = 2, /* gpu sensor is channel 2 */ 1216 .chn_num = 2, /* two channels for tsadc */ 1217 1218 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1219 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1220 .tshut_temp = 95000, 1221 1222 .tsadc_init = tsadc_init_v2, 1223 .tsadc_control = tsadc_control_v2, 1224 .tsadc_get_temp = tsadc_get_temp_v3, 1225 .irq_ack = tsadc_irq_ack_v2, 1226 .set_alarm_temp = tsadc_alarm_temp_v2, 1227 .set_tshut_temp = tsadc_tshut_temp_v2, 1228 .set_tshut_mode = tsadc_tshut_mode_v2, 1229 1230 .table = { 1231 .id = rk3288_code_table, 1232 .length = ARRAY_SIZE(rk3288_code_table), 1233 .data_mask = TSADCV2_DATA_MASK, 1234 .mode = ADC_DECREMENT, 1235 }, 1236 }; 1237 1238 static const struct rockchip_tsadc_chip rk3308_tsadc_data = { 1239 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1240 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1241 .chn_num = 2, /* 2 channels for tsadc */ 1242 1243 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ 1244 .tshut_temp = 95000, 1245 1246 .tsadc_init = tsadc_init_v4, 1247 .tsadc_control = tsadc_control_v3, 1248 .tsadc_get_temp = tsadc_get_temp_v2, 1249 .irq_ack = tsadc_irq_ack_v3, 1250 .set_alarm_temp = tsadc_alarm_temp_v2, 1251 .set_tshut_temp = tsadc_tshut_temp_v2, 1252 .set_tshut_mode = tsadc_tshut_mode_v2, 1253 1254 .table = { 1255 .id = rk3328_code_table, 1256 .length = ARRAY_SIZE(rk3328_code_table), 1257 .data_mask = TSADCV2_DATA_MASK, 1258 .mode = ADC_INCREMENT, 1259 }, 1260 }; 1261 1262 static const struct rockchip_tsadc_chip px30_tsadc_data = { 1263 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1264 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1265 .chn_num = 2, /* 2 channels for tsadc */ 1266 1267 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ 1268 .tshut_temp = 95000, 1269 1270 .tsadc_init = tsadc_init_v4, 1271 .tsadc_control = tsadc_control_v3, 1272 .tsadc_get_temp = tsadc_get_temp_v2, 1273 .irq_ack = tsadc_irq_ack_v3, 1274 .set_alarm_temp = tsadc_alarm_temp_v2, 1275 .set_tshut_temp = tsadc_tshut_temp_v2, 1276 .set_tshut_mode = tsadc_tshut_mode_v2, 1277 1278 .table = { 1279 .id = rk3328_code_table, 1280 .length = ARRAY_SIZE(rk3328_code_table), 1281 .data_mask = TSADCV2_DATA_MASK, 1282 .mode = ADC_INCREMENT, 1283 }, 1284 }; 1285 1286 static const struct rockchip_tsadc_chip rk3328_tsadc_data = { 1287 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1288 .chn_num = 1, /* one channels for tsadc */ 1289 1290 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ 1291 .tshut_temp = 95000, 1292 1293 .tsadc_init = tsadc_init_v2, 1294 .tsadc_control = tsadc_control_v3, 1295 .tsadc_get_temp = tsadc_get_temp_v2, 1296 .irq_ack = tsadc_irq_ack_v3, 1297 .set_alarm_temp = tsadc_alarm_temp_v2, 1298 .set_tshut_temp = tsadc_tshut_temp_v2, 1299 .set_tshut_mode = tsadc_tshut_mode_v2, 1300 1301 .table = { 1302 .id = rk3328_code_table, 1303 .length = ARRAY_SIZE(rk3328_code_table), 1304 .data_mask = TSADCV2_DATA_MASK, 1305 .mode = ADC_INCREMENT, 1306 }, 1307 }; 1308 1309 static const struct rockchip_tsadc_chip rk3366_tsadc_data = { 1310 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1311 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1312 .chn_num = 2, /* two channels for tsadc */ 1313 1314 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1315 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1316 .tshut_temp = 95000, 1317 1318 .tsadc_init = tsadc_init_v3, 1319 .tsadc_control = tsadc_control_v3, 1320 .tsadc_get_temp = tsadc_get_temp_v2, 1321 .irq_ack = tsadc_irq_ack_v3, 1322 .set_alarm_temp = tsadc_alarm_temp_v2, 1323 .set_tshut_temp = tsadc_tshut_temp_v2, 1324 .set_tshut_mode = tsadc_tshut_mode_v2, 1325 1326 .table = { 1327 .id = rk3228_code_table, 1328 .length = ARRAY_SIZE(rk3228_code_table), 1329 .data_mask = TSADCV3_DATA_MASK, 1330 .mode = ADC_INCREMENT, 1331 }, 1332 }; 1333 1334 static const struct rockchip_tsadc_chip rk3368_tsadc_data = { 1335 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1336 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1337 .chn_num = 2, /* two channels for tsadc */ 1338 1339 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1340 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1341 .tshut_temp = 95000, 1342 1343 .tsadc_init = tsadc_init_v2, 1344 .tsadc_control = tsadc_control_v2, 1345 .tsadc_get_temp = tsadc_get_temp_v2, 1346 .irq_ack = tsadc_irq_ack_v2, 1347 .set_alarm_temp = tsadc_alarm_temp_v2, 1348 .set_tshut_temp = tsadc_tshut_temp_v2, 1349 .set_tshut_mode = tsadc_tshut_mode_v2, 1350 1351 .table = { 1352 .id = rk3368_code_table, 1353 .length = ARRAY_SIZE(rk3368_code_table), 1354 .data_mask = TSADCV3_DATA_MASK, 1355 .mode = ADC_INCREMENT, 1356 }, 1357 }; 1358 1359 static const struct rockchip_tsadc_chip rk3399_tsadc_data = { 1360 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1361 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1362 .chn_num = 2, /* two channels for tsadc */ 1363 1364 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1365 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1366 .tshut_temp = 95000, 1367 1368 .tsadc_init = tsadc_init_v3, 1369 .tsadc_control = tsadc_control_v3, 1370 .tsadc_get_temp = tsadc_get_temp_v2, 1371 .irq_ack = tsadc_irq_ack_v3, 1372 .set_alarm_temp = tsadc_alarm_temp_v2, 1373 .set_tshut_temp = tsadc_tshut_temp_v2, 1374 .set_tshut_mode = tsadc_tshut_mode_v2, 1375 1376 .table = { 1377 .id = rk3399_code_table, 1378 .length = ARRAY_SIZE(rk3399_code_table), 1379 .data_mask = TSADCV3_DATA_MASK, 1380 .mode = ADC_INCREMENT, 1381 }, 1382 }; 1383 1384 static const struct rockchip_tsadc_chip rk3568_tsadc_data = { 1385 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1386 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1387 .chn_num = 2, /* two channels for tsadc */ 1388 1389 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1390 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1391 .tshut_temp = 95000, 1392 1393 .tsadc_init = tsadc_init_v7, 1394 .tsadc_control = tsadc_control_v3, 1395 .tsadc_get_temp = tsadc_get_temp_v2, 1396 .irq_ack = tsadc_irq_ack_v3, 1397 .set_alarm_temp = tsadc_alarm_temp_v2, 1398 .set_tshut_temp = tsadc_tshut_temp_v2, 1399 .set_tshut_mode = tsadc_tshut_mode_v2, 1400 1401 .table = { 1402 .id = rk3568_code_table, 1403 .length = ARRAY_SIZE(rk3568_code_table), 1404 .data_mask = TSADCV2_DATA_MASK, 1405 .mode = ADC_INCREMENT, 1406 }, 1407 }; 1408 1409 static const struct rockchip_tsadc_chip rk3588_tsadc_data = { 1410 /* top, big_core0, big_core1, little_core, center, gpu, npu */ 1411 .chn_id = {0, 1, 2, 3, 4, 5, 6}, 1412 .chn_num = 7, /* seven channels for tsadc */ 1413 1414 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1415 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1416 .tshut_temp = 95000, 1417 1418 .tsadc_init = tsadc_init_v8, 1419 .tsadc_control = tsadc_control_v4, 1420 .tsadc_get_temp = tsadc_get_temp_v4, 1421 .irq_ack = tsadc_irq_ack_v4, 1422 .set_alarm_temp = tsadc_alarm_temp_v3, 1423 .set_tshut_temp = tsadc_tshut_temp_v3, 1424 .set_tshut_mode = tsadc_tshut_mode_v4, 1425 1426 .table = { 1427 .id = rk3588_code_table, 1428 .length = ARRAY_SIZE(rk3588_code_table), 1429 .data_mask = TSADCV4_DATA_MASK, 1430 .mode = ADC_INCREMENT, 1431 }, 1432 }; 1433 1434 static const struct udevice_id rockchip_thermal_match[] = { 1435 { 1436 .compatible = "rockchip,px30-tsadc", 1437 .data = (ulong)&px30_tsadc_data, 1438 }, 1439 { 1440 .compatible = "rockchip,px30s-tsadc", 1441 .data = (ulong)&px30s_tsadc_data, 1442 }, 1443 { 1444 .compatible = "rockchip,rk1808-tsadc", 1445 .data = (ulong)&rk1808_tsadc_data, 1446 }, 1447 { 1448 .compatible = "rockchip,rk3228-tsadc", 1449 .data = (ulong)&rk3228_tsadc_data, 1450 }, 1451 { 1452 .compatible = "rockchip,rk3288-tsadc", 1453 .data = (ulong)&rk3288_tsadc_data, 1454 }, 1455 { 1456 .compatible = "rockchip,rk3308-tsadc", 1457 .data = (ulong)&rk3308_tsadc_data, 1458 }, 1459 { 1460 .compatible = "rockchip,rk3308bs-tsadc", 1461 .data = (ulong)&rk3308bs_tsadc_data, 1462 }, 1463 { 1464 .compatible = "rockchip,rk3328-tsadc", 1465 .data = (ulong)&rk3328_tsadc_data, 1466 }, 1467 { 1468 .compatible = "rockchip,rk3366-tsadc", 1469 .data = (ulong)&rk3366_tsadc_data, 1470 }, 1471 { 1472 .compatible = "rockchip,rk3368-tsadc", 1473 .data = (ulong)&rk3368_tsadc_data, 1474 }, 1475 { 1476 .compatible = "rockchip,rk3399-tsadc", 1477 .data = (ulong)&rk3399_tsadc_data, 1478 }, 1479 { 1480 .compatible = "rockchip,rk3568-tsadc", 1481 .data = (ulong)&rk3568_tsadc_data, 1482 }, 1483 { 1484 .compatible = "rockchip,rk3588-tsadc", 1485 .data = (ulong)&rk3588_tsadc_data, 1486 }, 1487 { /* end */ }, 1488 }; 1489 1490 U_BOOT_DRIVER(rockchip_thermal) = { 1491 .name = "rockchip_thermal", 1492 .id = UCLASS_THERMAL, 1493 .of_match = rockchip_thermal_match, 1494 .priv_auto_alloc_size = sizeof(struct rockchip_thermal_priv), 1495 .ofdata_to_platdata = rockchip_thermal_ofdata_to_platdata, 1496 .ops = &rockchip_thermal_ops, 1497 .probe = rockchip_thermal_probe, 1498 }; 1499