1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6 #include <common.h> 7 #include <bitfield.h> 8 #include <thermal.h> 9 #include <dm.h> 10 #include <dm/pinctrl.h> 11 #include <div64.h> 12 #include <errno.h> 13 #include <syscon.h> 14 #include <asm/arch/clock.h> 15 #include <asm/arch/cpu.h> 16 #include <asm/arch/hardware.h> 17 #include <asm/io.h> 18 #include <dm/lists.h> 19 #include <clk.h> 20 #include <clk-uclass.h> 21 #include <reset.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 /** 26 * If the temperature over a period of time High, 27 * the resulting TSHUT gave CRU module,let it reset the entire chip, 28 * or via GPIO give PMIC. 29 */ 30 enum tshut_mode { 31 TSHUT_MODE_CRU = 0, 32 TSHUT_MODE_GPIO, 33 }; 34 35 /** 36 * The system Temperature Sensors tshut(tshut) polarity 37 * the bit 8 is tshut polarity. 38 * 0: low active, 1: high active 39 */ 40 enum tshut_polarity { 41 TSHUT_LOW_ACTIVE = 0, 42 TSHUT_HIGH_ACTIVE, 43 }; 44 45 /** 46 * The conversion table has the adc value and temperature. 47 * ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table) 48 * ADC_INCREMENT: the adc value is incremental.(e.g. rk3368_code_table) 49 */ 50 enum adc_sort_mode { 51 ADC_DECREMENT = 0, 52 ADC_INCREMENT, 53 }; 54 55 #define SOC_MAX_SENSORS 2 56 57 #define TSADCV2_USER_CON 0x00 58 #define TSADCV2_AUTO_CON 0x04 59 #define TSADCV2_INT_EN 0x08 60 #define TSADCV2_INT_PD 0x0c 61 #define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04) 62 #define TSADCV2_COMP_INT(chn) (0x30 + (chn) * 0x04) 63 #define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04) 64 #define TSADCV2_HIGHT_INT_DEBOUNCE 0x60 65 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64 66 #define TSADCV2_AUTO_PERIOD 0x68 67 #define TSADCV2_AUTO_PERIOD_HT 0x6c 68 69 #define TSADCV2_AUTO_EN BIT(0) 70 #define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn)) 71 #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8) 72 73 #define TSADCV3_AUTO_Q_SEL_EN BIT(1) 74 75 #define TSADCV2_INT_SRC_EN(chn) BIT(chn) 76 #define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn)) 77 #define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn)) 78 79 #define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8) 80 #define TSADCV3_INT_PD_CLEAR_MASK ~BIT(16) 81 82 #define TSADCV2_DATA_MASK 0xfff 83 #define TSADCV3_DATA_MASK 0x3ff 84 85 #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4 86 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4 87 #define TSADCV2_AUTO_PERIOD_TIME 250 88 #define TSADCV2_AUTO_PERIOD_HT_TIME 50 89 #define TSADCV3_AUTO_PERIOD_TIME 1875 90 #define TSADCV3_AUTO_PERIOD_HT_TIME 1875 91 #define TSADCV5_AUTO_PERIOD_TIME 1622 /* 2.5ms */ 92 #define TSADCV5_AUTO_PERIOD_HT_TIME 1622 /* 2.5ms */ 93 94 #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */ 95 #define TSADCV5_USER_INTER_PD_SOC 0xfc0 /* 97us, at least 90us */ 96 97 #define GRF_SARADC_TESTBIT 0x0e644 98 #define GRF_TSADC_TESTBIT_L 0x0e648 99 #define GRF_TSADC_TESTBIT_H 0x0e64c 100 101 #define PX30_GRF_SOC_CON2 0x0408 102 103 #define RK3568_GRF_TSADC_CON 0x0600 104 #define RK3568_GRF_TSADC_ANA_REG0 (0x10001 << 0) 105 #define RK3568_GRF_TSADC_ANA_REG1 (0x10001 << 1) 106 #define RK3568_GRF_TSADC_ANA_REG2 (0x10001 << 2) 107 #define RK3568_GRF_TSADC_TSEN (0x10001 << 8) 108 109 #define GRF_SARADC_TESTBIT_ON (0x10001 << 2) 110 #define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2) 111 #define GRF_TSADC_VCM_EN_L (0x10001 << 7) 112 #define GRF_TSADC_VCM_EN_H (0x10001 << 7) 113 114 #define GRF_CON_TSADC_CH_INV (0x10001 << 1) 115 116 #define MIN_TEMP (-40000) 117 #define LOWEST_TEMP (-273000) 118 #define MAX_TEMP (125000) 119 #define MAX_ENV_TEMP (85000) 120 121 #define BASE (1024) 122 #define BASE_SHIFT (10) 123 #define START_DEBOUNCE_COUNT (100) 124 #define HIGHER_DEBOUNCE_TEMP (30000) 125 #define LOWER_DEBOUNCE_TEMP (15000) 126 127 /** 128 * struct tsadc_table - hold information about code and temp mapping 129 * @code: raw code from tsadc ip 130 * @temp: the mapping temperature 131 */ 132 133 struct tsadc_table { 134 unsigned long code; 135 int temp; 136 }; 137 138 struct chip_tsadc_table { 139 const struct tsadc_table *id; 140 unsigned int length; 141 u32 data_mask; 142 /* Tsadc is linear, using linear parameters */ 143 int knum; 144 int bnum; 145 enum adc_sort_mode mode; 146 }; 147 148 enum sensor_id { 149 SENSOR_CPU = 0, 150 SENSOR_GPU, 151 }; 152 153 struct rockchip_tsadc_chip { 154 /* The sensor id of chip correspond to the ADC channel */ 155 int chn_id[SOC_MAX_SENSORS]; 156 int chn_num; 157 fdt_addr_t base; 158 fdt_addr_t grf; 159 160 /* The hardware-controlled tshut property */ 161 int tshut_temp; 162 enum tshut_mode tshut_mode; 163 enum tshut_polarity tshut_polarity; 164 165 void (*tsadc_control)(struct udevice *dev, bool enable); 166 void (*tsadc_init)(struct udevice *dev); 167 int (*tsadc_get_temp)(struct udevice *dev, int chn, 168 int *temp); 169 void (*irq_ack)(struct udevice *dev); 170 void (*set_alarm_temp)(struct udevice *dev, 171 int chn, int temp); 172 void (*set_tshut_temp)(struct udevice *dev, 173 int chn, int temp); 174 void (*set_tshut_mode)(struct udevice *dev, int chn, enum tshut_mode m); 175 struct chip_tsadc_table table; 176 }; 177 178 struct rockchip_thermal_priv { 179 void *base; 180 void *grf; 181 enum tshut_mode tshut_mode; 182 enum tshut_polarity tshut_polarity; 183 const struct rockchip_tsadc_chip *data; 184 }; 185 186 static const struct tsadc_table rk1808_code_table[] = { 187 {0, -40000}, 188 {3455, -40000}, 189 {3463, -35000}, 190 {3471, -30000}, 191 {3479, -25000}, 192 {3487, -20000}, 193 {3495, -15000}, 194 {3503, -10000}, 195 {3511, -5000}, 196 {3519, 0}, 197 {3527, 5000}, 198 {3535, 10000}, 199 {3543, 15000}, 200 {3551, 20000}, 201 {3559, 25000}, 202 {3567, 30000}, 203 {3576, 35000}, 204 {3584, 40000}, 205 {3592, 45000}, 206 {3600, 50000}, 207 {3609, 55000}, 208 {3617, 60000}, 209 {3625, 65000}, 210 {3633, 70000}, 211 {3642, 75000}, 212 {3650, 80000}, 213 {3659, 85000}, 214 {3667, 90000}, 215 {3675, 95000}, 216 {3684, 100000}, 217 {3692, 105000}, 218 {3701, 110000}, 219 {3709, 115000}, 220 {3718, 120000}, 221 {3726, 125000}, 222 {TSADCV2_DATA_MASK, 125000}, 223 }; 224 225 static const struct tsadc_table rk3228_code_table[] = { 226 {0, -40000}, 227 {588, -40000}, 228 {593, -35000}, 229 {598, -30000}, 230 {603, -25000}, 231 {608, -20000}, 232 {613, -15000}, 233 {618, -10000}, 234 {623, -5000}, 235 {629, 0}, 236 {634, 5000}, 237 {639, 10000}, 238 {644, 15000}, 239 {649, 20000}, 240 {654, 25000}, 241 {660, 30000}, 242 {665, 35000}, 243 {670, 40000}, 244 {675, 45000}, 245 {681, 50000}, 246 {686, 55000}, 247 {691, 60000}, 248 {696, 65000}, 249 {702, 70000}, 250 {707, 75000}, 251 {712, 80000}, 252 {717, 85000}, 253 {723, 90000}, 254 {728, 95000}, 255 {733, 100000}, 256 {738, 105000}, 257 {744, 110000}, 258 {749, 115000}, 259 {754, 120000}, 260 {760, 125000}, 261 {TSADCV2_DATA_MASK, 125000}, 262 }; 263 264 static const struct tsadc_table rk3288_code_table[] = { 265 {TSADCV2_DATA_MASK, -40000}, 266 {3800, -40000}, 267 {3792, -35000}, 268 {3783, -30000}, 269 {3774, -25000}, 270 {3765, -20000}, 271 {3756, -15000}, 272 {3747, -10000}, 273 {3737, -5000}, 274 {3728, 0}, 275 {3718, 5000}, 276 {3708, 10000}, 277 {3698, 15000}, 278 {3688, 20000}, 279 {3678, 25000}, 280 {3667, 30000}, 281 {3656, 35000}, 282 {3645, 40000}, 283 {3634, 45000}, 284 {3623, 50000}, 285 {3611, 55000}, 286 {3600, 60000}, 287 {3588, 65000}, 288 {3575, 70000}, 289 {3563, 75000}, 290 {3550, 80000}, 291 {3537, 85000}, 292 {3524, 90000}, 293 {3510, 95000}, 294 {3496, 100000}, 295 {3482, 105000}, 296 {3467, 110000}, 297 {3452, 115000}, 298 {3437, 120000}, 299 {3421, 125000}, 300 }; 301 302 static const struct tsadc_table rk3328_code_table[] = { 303 {0, -40000}, 304 {296, -40000}, 305 {304, -35000}, 306 {313, -30000}, 307 {331, -20000}, 308 {340, -15000}, 309 {349, -10000}, 310 {359, -5000}, 311 {368, 0}, 312 {378, 5000}, 313 {388, 10000}, 314 {398, 15000}, 315 {408, 20000}, 316 {418, 25000}, 317 {429, 30000}, 318 {440, 35000}, 319 {451, 40000}, 320 {462, 45000}, 321 {473, 50000}, 322 {485, 55000}, 323 {496, 60000}, 324 {508, 65000}, 325 {521, 70000}, 326 {533, 75000}, 327 {546, 80000}, 328 {559, 85000}, 329 {572, 90000}, 330 {586, 95000}, 331 {600, 100000}, 332 {614, 105000}, 333 {629, 110000}, 334 {644, 115000}, 335 {659, 120000}, 336 {675, 125000}, 337 {TSADCV2_DATA_MASK, 125000}, 338 }; 339 340 static const struct tsadc_table rk3368_code_table[] = { 341 {0, -40000}, 342 {106, -40000}, 343 {108, -35000}, 344 {110, -30000}, 345 {112, -25000}, 346 {114, -20000}, 347 {116, -15000}, 348 {118, -10000}, 349 {120, -5000}, 350 {122, 0}, 351 {124, 5000}, 352 {126, 10000}, 353 {128, 15000}, 354 {130, 20000}, 355 {132, 25000}, 356 {134, 30000}, 357 {136, 35000}, 358 {138, 40000}, 359 {140, 45000}, 360 {142, 50000}, 361 {144, 55000}, 362 {146, 60000}, 363 {148, 65000}, 364 {150, 70000}, 365 {152, 75000}, 366 {154, 80000}, 367 {156, 85000}, 368 {158, 90000}, 369 {160, 95000}, 370 {162, 100000}, 371 {163, 105000}, 372 {165, 110000}, 373 {167, 115000}, 374 {169, 120000}, 375 {171, 125000}, 376 {TSADCV3_DATA_MASK, 125000}, 377 }; 378 379 static const struct tsadc_table rk3399_code_table[] = { 380 {0, -40000}, 381 {402, -40000}, 382 {410, -35000}, 383 {419, -30000}, 384 {427, -25000}, 385 {436, -20000}, 386 {444, -15000}, 387 {453, -10000}, 388 {461, -5000}, 389 {470, 0}, 390 {478, 5000}, 391 {487, 10000}, 392 {496, 15000}, 393 {504, 20000}, 394 {513, 25000}, 395 {521, 30000}, 396 {530, 35000}, 397 {538, 40000}, 398 {547, 45000}, 399 {555, 50000}, 400 {564, 55000}, 401 {573, 60000}, 402 {581, 65000}, 403 {590, 70000}, 404 {599, 75000}, 405 {607, 80000}, 406 {616, 85000}, 407 {624, 90000}, 408 {633, 95000}, 409 {642, 100000}, 410 {650, 105000}, 411 {659, 110000}, 412 {668, 115000}, 413 {677, 120000}, 414 {685, 125000}, 415 {TSADCV3_DATA_MASK, 125000}, 416 }; 417 418 static const struct tsadc_table rk3568_code_table[] = { 419 {0, -40000}, 420 {1584, -40000}, 421 {1620, -35000}, 422 {1652, -30000}, 423 {1688, -25000}, 424 {1720, -20000}, 425 {1756, -15000}, 426 {1788, -10000}, 427 {1824, -5000}, 428 {1856, 0}, 429 {1892, 5000}, 430 {1924, 10000}, 431 {1956, 15000}, 432 {1992, 20000}, 433 {2024, 25000}, 434 {2060, 30000}, 435 {2092, 35000}, 436 {2128, 40000}, 437 {2160, 45000}, 438 {2196, 50000}, 439 {2228, 55000}, 440 {2264, 60000}, 441 {2300, 65000}, 442 {2332, 70000}, 443 {2368, 75000}, 444 {2400, 80000}, 445 {2436, 85000}, 446 {2468, 90000}, 447 {2500, 95000}, 448 {2536, 100000}, 449 {2572, 105000}, 450 {2604, 110000}, 451 {2636, 115000}, 452 {2672, 120000}, 453 {2704, 125000}, 454 {TSADCV2_DATA_MASK, 125000}, 455 }; 456 457 /* 458 * Struct used for matching a device 459 */ 460 struct of_device_id { 461 char compatible[32]; 462 const void *data; 463 }; 464 465 static int tsadc_code_to_temp(struct chip_tsadc_table *table, u32 code, 466 int *temp) 467 { 468 unsigned int low = 1; 469 unsigned int high = table->length - 1; 470 unsigned int mid = (low + high) / 2; 471 unsigned int num; 472 unsigned long denom; 473 474 if (table->knum) { 475 *temp = (((int)code - table->bnum) * 10000 / table->knum) * 100; 476 if (*temp < MIN_TEMP || *temp > MAX_TEMP) 477 return -EAGAIN; 478 return 0; 479 } 480 481 switch (table->mode) { 482 case ADC_DECREMENT: 483 code &= table->data_mask; 484 if (code < table->id[high].code) 485 return -EAGAIN; /* Incorrect reading */ 486 487 while (low <= high) { 488 if (code >= table->id[mid].code && 489 code < table->id[mid - 1].code) 490 break; 491 else if (code < table->id[mid].code) 492 low = mid + 1; 493 else 494 high = mid - 1; 495 496 mid = (low + high) / 2; 497 } 498 break; 499 case ADC_INCREMENT: 500 code &= table->data_mask; 501 if (code < table->id[low].code) 502 return -EAGAIN; /* Incorrect reading */ 503 504 while (low <= high) { 505 if (code <= table->id[mid].code && 506 code > table->id[mid - 1].code) 507 break; 508 else if (code > table->id[mid].code) 509 low = mid + 1; 510 else 511 high = mid - 1; 512 513 mid = (low + high) / 2; 514 } 515 break; 516 default: 517 printf("%s: Invalid the conversion table mode=%d\n", 518 __func__, table->mode); 519 return -EINVAL; 520 } 521 522 /* 523 * The 5C granularity provided by the table is too much. Let's 524 * assume that the relationship between sensor readings and 525 * temperature between 2 table entries is linear and interpolate 526 * to produce less granular result. 527 */ 528 num = table->id[mid].temp - table->id[mid - 1].temp; 529 num *= abs(table->id[mid - 1].code - code); 530 denom = abs(table->id[mid - 1].code - table->id[mid].code); 531 *temp = table->id[mid - 1].temp + (num / denom); 532 533 return 0; 534 } 535 536 static u32 tsadc_temp_to_code_v2(struct chip_tsadc_table table, 537 int temp) 538 { 539 int high, low, mid; 540 u32 error = table.data_mask; 541 542 if (table.knum) 543 return (((temp / 1000) * table.knum) / 1000 + table.bnum); 544 545 low = 0; 546 high = table.length - 1; 547 mid = (high + low) / 2; 548 549 /* Return mask code data when the temp is over table range */ 550 if (temp < table.id[low].temp || temp > table.id[high].temp) 551 goto exit; 552 553 while (low <= high) { 554 if (temp == table.id[mid].temp) 555 return table.id[mid].code; 556 else if (temp < table.id[mid].temp) 557 high = mid - 1; 558 else 559 low = mid + 1; 560 mid = (low + high) / 2; 561 } 562 563 exit: 564 pr_err("%s: Invalid conversion table: code=%d, temperature=%d\n", 565 __func__, error, temp); 566 567 return error; 568 } 569 570 static void tsadc_irq_ack_v2(struct udevice *dev) 571 { 572 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 573 u32 val; 574 575 val = readl(priv->base + TSADCV2_INT_PD); 576 writel(val & TSADCV2_INT_PD_CLEAR_MASK, priv->base + TSADCV2_INT_PD); 577 } 578 579 static void tsadc_irq_ack_v3(struct udevice *dev) 580 { 581 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 582 u32 val; 583 584 val = readl(priv->base + TSADCV2_INT_PD); 585 writel(val & TSADCV3_INT_PD_CLEAR_MASK, priv->base + TSADCV2_INT_PD); 586 } 587 588 static void tsadc_control_v3(struct udevice *dev, bool enable) 589 { 590 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 591 u32 val; 592 593 val = readl(priv->base + TSADCV2_AUTO_CON); 594 if (enable) 595 val |= TSADCV2_AUTO_EN | TSADCV3_AUTO_Q_SEL_EN; 596 else 597 val &= ~TSADCV2_AUTO_EN; 598 599 writel(val, priv->base + TSADCV2_AUTO_CON); 600 } 601 602 static void tsadc_control_v2(struct udevice *dev, bool enable) 603 { 604 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 605 u32 val; 606 607 val = readl(priv->base + TSADCV2_AUTO_CON); 608 if (enable) 609 val |= TSADCV2_AUTO_EN; 610 else 611 val &= ~TSADCV2_AUTO_EN; 612 613 writel(val, priv->base + TSADCV2_AUTO_CON); 614 } 615 616 static void tsadc_init_v2(struct udevice *dev) 617 { 618 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 619 620 writel(TSADCV2_AUTO_PERIOD_TIME, 621 priv->base + TSADCV2_AUTO_PERIOD); 622 writel(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, 623 priv->base + TSADCV2_HIGHT_INT_DEBOUNCE); 624 writel(TSADCV2_AUTO_PERIOD_HT_TIME, 625 priv->base + TSADCV2_AUTO_PERIOD_HT); 626 writel(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, 627 priv->base + TSADCV2_HIGHT_TSHUT_DEBOUNCE); 628 629 if (priv->tshut_polarity == TSHUT_HIGH_ACTIVE) 630 writel(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 631 priv->base + TSADCV2_AUTO_CON); 632 else 633 writel(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 634 priv->base + TSADCV2_AUTO_CON); 635 } 636 637 static void tsadc_init_v3(struct udevice *dev) 638 { 639 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 640 641 if (!IS_ERR(priv->grf)) { 642 writel(GRF_TSADC_VCM_EN_L, priv->grf + GRF_TSADC_TESTBIT_L); 643 writel(GRF_TSADC_VCM_EN_H, priv->grf + GRF_TSADC_TESTBIT_H); 644 645 udelay(100);/* The spec note says at least 15 us */ 646 writel(GRF_SARADC_TESTBIT_ON, priv->grf + GRF_SARADC_TESTBIT); 647 writel(GRF_TSADC_TESTBIT_H_ON, priv->grf + GRF_TSADC_TESTBIT_H); 648 udelay(200);/* The spec note says at least 90 us */ 649 } 650 tsadc_init_v2(dev); 651 } 652 653 static void __maybe_unused tsadc_init_v5(struct udevice *dev) 654 { 655 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 656 657 /* Set interleave value to workround ic time sync issue */ 658 writel(TSADCV2_USER_INTER_PD_SOC, priv->base + 659 TSADCV2_USER_CON); 660 tsadc_init_v2(dev); 661 } 662 663 static void tsadc_init_v4(struct udevice *dev) 664 { 665 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 666 667 tsadc_init_v2(dev); 668 if (!IS_ERR(priv->grf)) 669 writel(GRF_CON_TSADC_CH_INV, priv->grf + PX30_GRF_SOC_CON2); 670 } 671 672 static void tsadc_init_v7(struct udevice *dev) 673 { 674 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 675 676 writel(TSADCV5_USER_INTER_PD_SOC, 677 priv->base + TSADCV2_USER_CON); 678 writel(TSADCV5_AUTO_PERIOD_TIME, 679 priv->base + TSADCV2_AUTO_PERIOD); 680 writel(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, 681 priv->base + TSADCV2_HIGHT_INT_DEBOUNCE); 682 writel(TSADCV5_AUTO_PERIOD_HT_TIME, 683 priv->base + TSADCV2_AUTO_PERIOD_HT); 684 writel(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, 685 priv->base + TSADCV2_HIGHT_TSHUT_DEBOUNCE); 686 687 if (priv->tshut_polarity == TSHUT_HIGH_ACTIVE) 688 writel(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 689 priv->base + TSADCV2_AUTO_CON); 690 else 691 writel(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 692 priv->base + TSADCV2_AUTO_CON); 693 694 if (!IS_ERR(priv->grf)) { 695 writel(RK3568_GRF_TSADC_TSEN, 696 priv->grf + RK3568_GRF_TSADC_CON); 697 udelay(15); 698 writel(RK3568_GRF_TSADC_ANA_REG0, 699 priv->grf + RK3568_GRF_TSADC_CON); 700 writel(RK3568_GRF_TSADC_ANA_REG1, 701 priv->grf + RK3568_GRF_TSADC_CON); 702 writel(RK3568_GRF_TSADC_ANA_REG2, 703 priv->grf + RK3568_GRF_TSADC_CON); 704 udelay(200); 705 } 706 } 707 708 static int tsadc_get_temp_v2(struct udevice *dev, 709 int chn, int *temp) 710 { 711 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 712 struct chip_tsadc_table table = priv->data->table; 713 u32 val; 714 715 val = readl(priv->base + TSADCV2_DATA(chn)); 716 717 return tsadc_code_to_temp(&table, val, temp); 718 } 719 720 static int predict_temp(int temp) 721 { 722 /* 723 * The deviation of prediction. the temperature will not change rapidly, 724 * so this cov_q is small 725 */ 726 int cov_q = 18; 727 /* 728 * The deviation of tsadc's reading, deviation of tsadc is very big when 729 * abnormal temperature is get 730 */ 731 int cov_r = 542; 732 733 int gain; 734 int temp_mid; 735 int temp_now; 736 int prob_mid; 737 int prob_now; 738 static int temp_last = LOWEST_TEMP; 739 static int prob_last = 160; 740 static int bounding_cnt; 741 742 /* 743 * init temp_last with a more suitable value, which mostly equals to 744 * temp reading from tsadc, but not higher than MAX_ENV_TEMP. If the 745 * temp is higher than MAX_ENV_TEMP, it is assumed to be abnormal 746 * value and temp_last is adjusted to MAX_ENV_TEMP. 747 */ 748 if (temp_last == LOWEST_TEMP) 749 temp_last = min(temp, MAX_ENV_TEMP); 750 751 /* 752 * Before START_DEBOUNCE_COUNT's samples of temperature, we consider 753 * tsadc is stable, i.e. after that, the temperature may be not stable 754 * and may have abnormal reading, so we set a bounding temperature. If 755 * the reading from tsadc is too big, we set the delta temperature of 756 * DEBOUNCE_TEMP/3 comparing to the last temperature. 757 */ 758 759 if (bounding_cnt++ > START_DEBOUNCE_COUNT) { 760 bounding_cnt = START_DEBOUNCE_COUNT; 761 if (temp - temp_last > HIGHER_DEBOUNCE_TEMP) 762 temp = temp_last + HIGHER_DEBOUNCE_TEMP / 3; 763 if (temp_last - temp > LOWER_DEBOUNCE_TEMP) 764 temp = temp_last - LOWER_DEBOUNCE_TEMP / 3; 765 } 766 767 temp_mid = temp_last; 768 769 /* calculate the probability of this time's prediction */ 770 prob_mid = prob_last + cov_q; 771 772 /* calculate the Kalman Gain */ 773 gain = (prob_mid * BASE) / (prob_mid + cov_r); 774 775 /* calculate the prediction of temperature */ 776 temp_now = (temp_mid * BASE + gain * (temp - temp_mid)) >> BASE_SHIFT; 777 778 /* 779 * Base on this time's Kalman Gain, ajust our probability of prediction 780 * for next time calculation 781 */ 782 prob_now = ((BASE - gain) * prob_mid) >> BASE_SHIFT; 783 784 prob_last = prob_now; 785 temp_last = temp_now; 786 787 return temp_last; 788 } 789 790 static int tsadc_get_temp_v3(struct udevice *dev, 791 int chn, int *temp) 792 { 793 int ret; 794 795 ret = tsadc_get_temp_v2(dev, chn, temp); 796 if (!ret) 797 *temp = predict_temp(*temp); 798 799 return ret; 800 } 801 802 static void tsadc_alarm_temp_v2(struct udevice *dev, 803 int chn, int temp) 804 { 805 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 806 struct chip_tsadc_table table = priv->data->table; 807 u32 alarm_value, int_en; 808 809 alarm_value = tsadc_temp_to_code_v2(table, temp); 810 if (alarm_value == table.data_mask) 811 return; 812 813 writel(alarm_value, priv->base + TSADCV2_COMP_INT(chn)); 814 815 int_en = readl(priv->base + TSADCV2_INT_EN); 816 int_en |= TSADCV2_INT_SRC_EN(chn); 817 writel(int_en, priv->base + TSADCV2_INT_EN); 818 } 819 820 static void tsadc_tshut_temp_v2(struct udevice *dev, 821 int chn, int temp) 822 { 823 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 824 struct chip_tsadc_table table = priv->data->table; 825 u32 tshut_value, val; 826 827 tshut_value = tsadc_temp_to_code_v2(table, temp); 828 if (tshut_value == table.data_mask) 829 return; 830 831 writel(tshut_value, priv->base + TSADCV2_COMP_SHUT(chn)); 832 833 /* TSHUT will be valid */ 834 val = readl(priv->base + TSADCV2_AUTO_CON); 835 writel(val | TSADCV2_AUTO_SRC_EN(chn), priv->base + TSADCV2_AUTO_CON); 836 } 837 838 static void tsadc_tshut_mode_v2(struct udevice *dev, int chn, 839 enum tshut_mode mode) 840 { 841 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 842 u32 val; 843 844 val = readl(priv->base + TSADCV2_INT_EN); 845 if (mode == TSHUT_MODE_GPIO) { 846 val &= ~TSADCV2_SHUT_2CRU_SRC_EN(chn); 847 val |= TSADCV2_SHUT_2GPIO_SRC_EN(chn); 848 } else { 849 val &= ~TSADCV2_SHUT_2GPIO_SRC_EN(chn); 850 val |= TSADCV2_SHUT_2CRU_SRC_EN(chn); 851 } 852 853 writel(val, priv->base + TSADCV2_INT_EN); 854 } 855 856 int rockchip_thermal_get_temp(struct udevice *dev, int *temp) 857 { 858 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 859 860 priv->data->tsadc_get_temp(dev, 0, temp); 861 862 return 0; 863 } 864 865 static const struct dm_thermal_ops rockchip_thermal_ops = { 866 .get_temp = rockchip_thermal_get_temp, 867 }; 868 869 static const struct rockchip_tsadc_chip rk3308bs_tsadc_data = { 870 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 871 .chn_num = 1, /* 1 channels for tsadc */ 872 873 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ 874 .tshut_temp = 95000, 875 876 .tsadc_init = tsadc_init_v2, 877 .tsadc_control = tsadc_control_v2, 878 .tsadc_get_temp = tsadc_get_temp_v2, 879 .irq_ack = tsadc_irq_ack_v3, 880 .set_alarm_temp = tsadc_alarm_temp_v2, 881 .set_tshut_temp = tsadc_tshut_temp_v2, 882 .set_tshut_mode = tsadc_tshut_mode_v2, 883 884 .table = { 885 .knum = 2699, 886 .bnum = 2796, 887 .data_mask = TSADCV2_DATA_MASK, 888 .mode = ADC_INCREMENT, 889 }, 890 }; 891 892 static int rockchip_thermal_probe(struct udevice *dev) 893 { 894 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 895 struct rockchip_tsadc_chip *tsadc; 896 struct clk clk; 897 int ret, i, shut_temp; 898 899 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 900 ret = clk_set_defaults(dev); 901 if (ret) 902 printf("%s clk_set_defaults failed %d\n", __func__, ret); 903 904 if (soc_is_rk3308bs()) { 905 ret = clk_get_by_name(dev, "tsadc", &clk); 906 if (ret) { 907 printf("%s get tsadc clk fail\n", __func__); 908 return -EINVAL; 909 } 910 ret = clk_set_rate(&clk, 4000000); 911 if (ret < 0) { 912 printf("%s: failed to set tsadc clk rate for %s\n", 913 __func__, dev_read_name(dev)); 914 return -EINVAL; 915 } 916 917 tsadc = (struct rockchip_tsadc_chip *)&rk3308bs_tsadc_data; 918 } else { 919 tsadc = (struct rockchip_tsadc_chip *)dev_get_driver_data(dev); 920 } 921 priv->data = tsadc; 922 923 priv->tshut_mode = dev_read_u32_default(dev, 924 "rockchip,hw-tshut-mode", 925 -1); 926 if (priv->tshut_mode < 0) 927 priv->tshut_mode = priv->data->tshut_mode; 928 929 priv->tshut_polarity = dev_read_u32_default(dev, 930 "rockchip,hw-tshut-polarity", 931 -1); 932 if (priv->tshut_polarity < 0) 933 priv->tshut_polarity = tsadc->tshut_polarity; 934 935 if (priv->tshut_mode == TSHUT_MODE_GPIO) 936 pinctrl_select_state(dev, "otpout"); 937 else 938 pinctrl_select_state(dev, "gpio"); 939 940 tsadc->tsadc_init(dev); 941 tsadc->irq_ack(dev); 942 943 shut_temp = dev_read_u32_default(dev, "rockchip,hw-tshut-temp", -1); 944 if (shut_temp < 0) 945 shut_temp = 120000; 946 947 for (i = 0; i < tsadc->chn_num; i++) { 948 tsadc->set_alarm_temp(dev, i, tsadc->tshut_temp); 949 tsadc->set_tshut_temp(dev, i, shut_temp); 950 if (priv->tshut_mode == TSHUT_MODE_GPIO) 951 tsadc->set_tshut_mode(dev, i, TSHUT_MODE_GPIO); 952 else 953 tsadc->set_tshut_mode(dev, i, TSHUT_MODE_CRU); 954 } 955 956 tsadc->tsadc_control(dev, true); 957 if (soc_is_rk3308bs()) 958 mdelay(3); 959 else 960 udelay(1000); 961 962 debug("tsadc probed successfully\n"); 963 964 return 0; 965 } 966 967 static int rockchip_thermal_ofdata_to_platdata(struct udevice *dev) 968 { 969 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 970 971 priv->base = dev_read_addr_ptr(dev); 972 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 973 974 return 0; 975 } 976 977 static const struct rockchip_tsadc_chip rk1808_tsadc_data = { 978 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 979 .chn_num = 1, /* one channel for tsadc */ 980 981 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 982 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 983 .tshut_temp = 95000, 984 985 .tsadc_init = tsadc_init_v2, 986 .tsadc_control = tsadc_control_v3, 987 .tsadc_get_temp = tsadc_get_temp_v2, 988 .irq_ack = tsadc_irq_ack_v3, 989 .set_alarm_temp = tsadc_alarm_temp_v2, 990 .set_tshut_temp = tsadc_tshut_temp_v2, 991 .set_tshut_mode = tsadc_tshut_mode_v2, 992 993 .table = { 994 .id = rk1808_code_table, 995 .length = ARRAY_SIZE(rk1808_code_table), 996 .data_mask = TSADCV2_DATA_MASK, 997 .mode = ADC_INCREMENT, 998 }, 999 }; 1000 1001 static const struct rockchip_tsadc_chip rk3228_tsadc_data = { 1002 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1003 .chn_num = 1, /* one channel for tsadc */ 1004 1005 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1006 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1007 .tshut_temp = 95000, 1008 1009 .tsadc_init = tsadc_init_v2, 1010 .tsadc_control = tsadc_control_v3, 1011 .tsadc_get_temp = tsadc_get_temp_v2, 1012 .irq_ack = tsadc_irq_ack_v3, 1013 .set_alarm_temp = tsadc_alarm_temp_v2, 1014 .set_tshut_temp = tsadc_tshut_temp_v2, 1015 .set_tshut_mode = tsadc_tshut_mode_v2, 1016 1017 .table = { 1018 .id = rk3228_code_table, 1019 .length = ARRAY_SIZE(rk3228_code_table), 1020 .data_mask = TSADCV3_DATA_MASK, 1021 .mode = ADC_INCREMENT, 1022 }, 1023 }; 1024 1025 static const struct rockchip_tsadc_chip rk3288_tsadc_data = { 1026 .chn_id[SENSOR_CPU] = 1, /* cpu sensor is channel 1 */ 1027 .chn_id[SENSOR_GPU] = 2, /* gpu sensor is channel 2 */ 1028 .chn_num = 2, /* two channels for tsadc */ 1029 1030 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1031 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1032 .tshut_temp = 95000, 1033 1034 .tsadc_init = tsadc_init_v2, 1035 .tsadc_control = tsadc_control_v2, 1036 .tsadc_get_temp = tsadc_get_temp_v3, 1037 .irq_ack = tsadc_irq_ack_v2, 1038 .set_alarm_temp = tsadc_alarm_temp_v2, 1039 .set_tshut_temp = tsadc_tshut_temp_v2, 1040 .set_tshut_mode = tsadc_tshut_mode_v2, 1041 1042 .table = { 1043 .id = rk3288_code_table, 1044 .length = ARRAY_SIZE(rk3288_code_table), 1045 .data_mask = TSADCV2_DATA_MASK, 1046 .mode = ADC_DECREMENT, 1047 }, 1048 }; 1049 1050 static const struct rockchip_tsadc_chip rk3308_tsadc_data = { 1051 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1052 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1053 .chn_num = 2, /* 2 channels for tsadc */ 1054 1055 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ 1056 .tshut_temp = 95000, 1057 1058 .tsadc_init = tsadc_init_v4, 1059 .tsadc_control = tsadc_control_v3, 1060 .tsadc_get_temp = tsadc_get_temp_v2, 1061 .irq_ack = tsadc_irq_ack_v3, 1062 .set_alarm_temp = tsadc_alarm_temp_v2, 1063 .set_tshut_temp = tsadc_tshut_temp_v2, 1064 .set_tshut_mode = tsadc_tshut_mode_v2, 1065 1066 .table = { 1067 .id = rk3328_code_table, 1068 .length = ARRAY_SIZE(rk3328_code_table), 1069 .data_mask = TSADCV2_DATA_MASK, 1070 .mode = ADC_INCREMENT, 1071 }, 1072 }; 1073 1074 static const struct rockchip_tsadc_chip px30_tsadc_data = { 1075 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1076 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1077 .chn_num = 2, /* 2 channels for tsadc */ 1078 1079 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ 1080 .tshut_temp = 95000, 1081 1082 .tsadc_init = tsadc_init_v4, 1083 .tsadc_control = tsadc_control_v3, 1084 .tsadc_get_temp = tsadc_get_temp_v2, 1085 .irq_ack = tsadc_irq_ack_v3, 1086 .set_alarm_temp = tsadc_alarm_temp_v2, 1087 .set_tshut_temp = tsadc_tshut_temp_v2, 1088 .set_tshut_mode = tsadc_tshut_mode_v2, 1089 1090 .table = { 1091 .id = rk3328_code_table, 1092 .length = ARRAY_SIZE(rk3328_code_table), 1093 .data_mask = TSADCV2_DATA_MASK, 1094 .mode = ADC_INCREMENT, 1095 }, 1096 }; 1097 1098 static const struct rockchip_tsadc_chip rk3328_tsadc_data = { 1099 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1100 .chn_num = 1, /* one channels for tsadc */ 1101 1102 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ 1103 .tshut_temp = 95000, 1104 1105 .tsadc_init = tsadc_init_v2, 1106 .tsadc_control = tsadc_control_v3, 1107 .tsadc_get_temp = tsadc_get_temp_v2, 1108 .irq_ack = tsadc_irq_ack_v3, 1109 .set_alarm_temp = tsadc_alarm_temp_v2, 1110 .set_tshut_temp = tsadc_tshut_temp_v2, 1111 .set_tshut_mode = tsadc_tshut_mode_v2, 1112 1113 .table = { 1114 .id = rk3328_code_table, 1115 .length = ARRAY_SIZE(rk3328_code_table), 1116 .data_mask = TSADCV2_DATA_MASK, 1117 .mode = ADC_INCREMENT, 1118 }, 1119 }; 1120 1121 static const struct rockchip_tsadc_chip rk3366_tsadc_data = { 1122 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1123 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1124 .chn_num = 2, /* two channels for tsadc */ 1125 1126 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1127 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1128 .tshut_temp = 95000, 1129 1130 .tsadc_init = tsadc_init_v3, 1131 .tsadc_control = tsadc_control_v3, 1132 .tsadc_get_temp = tsadc_get_temp_v2, 1133 .irq_ack = tsadc_irq_ack_v3, 1134 .set_alarm_temp = tsadc_alarm_temp_v2, 1135 .set_tshut_temp = tsadc_tshut_temp_v2, 1136 .set_tshut_mode = tsadc_tshut_mode_v2, 1137 1138 .table = { 1139 .id = rk3228_code_table, 1140 .length = ARRAY_SIZE(rk3228_code_table), 1141 .data_mask = TSADCV3_DATA_MASK, 1142 .mode = ADC_INCREMENT, 1143 }, 1144 }; 1145 1146 static const struct rockchip_tsadc_chip rk3368_tsadc_data = { 1147 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1148 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1149 .chn_num = 2, /* two channels for tsadc */ 1150 1151 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1152 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1153 .tshut_temp = 95000, 1154 1155 .tsadc_init = tsadc_init_v2, 1156 .tsadc_control = tsadc_control_v2, 1157 .tsadc_get_temp = tsadc_get_temp_v2, 1158 .irq_ack = tsadc_irq_ack_v2, 1159 .set_alarm_temp = tsadc_alarm_temp_v2, 1160 .set_tshut_temp = tsadc_tshut_temp_v2, 1161 .set_tshut_mode = tsadc_tshut_mode_v2, 1162 1163 .table = { 1164 .id = rk3368_code_table, 1165 .length = ARRAY_SIZE(rk3368_code_table), 1166 .data_mask = TSADCV3_DATA_MASK, 1167 .mode = ADC_INCREMENT, 1168 }, 1169 }; 1170 1171 static const struct rockchip_tsadc_chip rk3399_tsadc_data = { 1172 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1173 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1174 .chn_num = 2, /* two channels for tsadc */ 1175 1176 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1177 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1178 .tshut_temp = 95000, 1179 1180 .tsadc_init = tsadc_init_v3, 1181 .tsadc_control = tsadc_control_v3, 1182 .tsadc_get_temp = tsadc_get_temp_v2, 1183 .irq_ack = tsadc_irq_ack_v3, 1184 .set_alarm_temp = tsadc_alarm_temp_v2, 1185 .set_tshut_temp = tsadc_tshut_temp_v2, 1186 .set_tshut_mode = tsadc_tshut_mode_v2, 1187 1188 .table = { 1189 .id = rk3399_code_table, 1190 .length = ARRAY_SIZE(rk3399_code_table), 1191 .data_mask = TSADCV3_DATA_MASK, 1192 .mode = ADC_INCREMENT, 1193 }, 1194 }; 1195 1196 static const struct rockchip_tsadc_chip rk3568_tsadc_data = { 1197 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1198 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1199 .chn_num = 2, /* two channels for tsadc */ 1200 1201 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1202 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1203 .tshut_temp = 95000, 1204 1205 .tsadc_init = tsadc_init_v7, 1206 .tsadc_control = tsadc_control_v3, 1207 .tsadc_get_temp = tsadc_get_temp_v2, 1208 .irq_ack = tsadc_irq_ack_v3, 1209 .set_alarm_temp = tsadc_alarm_temp_v2, 1210 .set_tshut_temp = tsadc_tshut_temp_v2, 1211 .set_tshut_mode = tsadc_tshut_mode_v2, 1212 1213 .table = { 1214 .id = rk3568_code_table, 1215 .length = ARRAY_SIZE(rk3568_code_table), 1216 .data_mask = TSADCV2_DATA_MASK, 1217 .mode = ADC_INCREMENT, 1218 }, 1219 }; 1220 1221 static const struct udevice_id rockchip_thermal_match[] = { 1222 { 1223 .compatible = "rockchip,px30-tsadc", 1224 .data = (ulong)&px30_tsadc_data, 1225 }, 1226 { 1227 .compatible = "rockchip,rk1808-tsadc", 1228 .data = (ulong)&rk1808_tsadc_data, 1229 }, 1230 { 1231 .compatible = "rockchip,rk3228-tsadc", 1232 .data = (ulong)&rk3228_tsadc_data, 1233 }, 1234 { 1235 .compatible = "rockchip,rk3288-tsadc", 1236 .data = (ulong)&rk3288_tsadc_data, 1237 }, 1238 { 1239 .compatible = "rockchip,rk3308-tsadc", 1240 .data = (ulong)&rk3308_tsadc_data, 1241 }, 1242 { 1243 .compatible = "rockchip,rk3308bs-tsadc", 1244 .data = (ulong)&rk3308bs_tsadc_data, 1245 }, 1246 { 1247 .compatible = "rockchip,rk3328-tsadc", 1248 .data = (ulong)&rk3328_tsadc_data, 1249 }, 1250 { 1251 .compatible = "rockchip,rk3366-tsadc", 1252 .data = (ulong)&rk3366_tsadc_data, 1253 }, 1254 { 1255 .compatible = "rockchip,rk3368-tsadc", 1256 .data = (ulong)&rk3368_tsadc_data, 1257 }, 1258 { 1259 .compatible = "rockchip,rk3399-tsadc", 1260 .data = (ulong)&rk3399_tsadc_data, 1261 }, 1262 { 1263 .compatible = "rockchip,rk3568-tsadc", 1264 .data = (ulong)&rk3568_tsadc_data, 1265 }, 1266 { /* end */ }, 1267 }; 1268 1269 U_BOOT_DRIVER(rockchip_thermal) = { 1270 .name = "rockchip_thermal", 1271 .id = UCLASS_THERMAL, 1272 .of_match = rockchip_thermal_match, 1273 .priv_auto_alloc_size = sizeof(struct rockchip_thermal_priv), 1274 .ofdata_to_platdata = rockchip_thermal_ofdata_to_platdata, 1275 .ops = &rockchip_thermal_ops, 1276 .probe = rockchip_thermal_probe, 1277 }; 1278