1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6 #include <common.h> 7 #include <bitfield.h> 8 #include <thermal.h> 9 #include <dm.h> 10 #include <dm/pinctrl.h> 11 #include <div64.h> 12 #include <errno.h> 13 #include <syscon.h> 14 #include <asm/arch/clock.h> 15 #include <asm/arch/cpu.h> 16 #include <asm/arch/hardware.h> 17 #include <asm/io.h> 18 #include <dm/lists.h> 19 #include <clk.h> 20 #include <clk-uclass.h> 21 #include <reset.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 /** 26 * If the temperature over a period of time High, 27 * the resulting TSHUT gave CRU module,let it reset the entire chip, 28 * or via GPIO give PMIC. 29 */ 30 enum tshut_mode { 31 TSHUT_MODE_CRU = 0, 32 TSHUT_MODE_GPIO, 33 }; 34 35 /** 36 * The system Temperature Sensors tshut(tshut) polarity 37 * the bit 8 is tshut polarity. 38 * 0: low active, 1: high active 39 */ 40 enum tshut_polarity { 41 TSHUT_LOW_ACTIVE = 0, 42 TSHUT_HIGH_ACTIVE, 43 }; 44 45 /** 46 * The conversion table has the adc value and temperature. 47 * ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table) 48 * ADC_INCREMENT: the adc value is incremental.(e.g. rk3368_code_table) 49 */ 50 enum adc_sort_mode { 51 ADC_DECREMENT = 0, 52 ADC_INCREMENT, 53 }; 54 55 #define SOC_MAX_SENSORS 7 56 57 #define TSADCV2_USER_CON 0x00 58 #define TSADCV2_AUTO_CON 0x04 59 #define TSADCV2_INT_EN 0x08 60 #define TSADCV2_INT_PD 0x0c 61 #define TSADCV3_AUTO_SRC_CON 0x0c 62 #define TSADCV3_HT_INT_EN 0x14 63 #define TSADCV3_HSHUT_GPIO_INT_EN 0x18 64 #define TSADCV3_HSHUT_CRU_INT_EN 0x1c 65 #define TSADCV3_INT_PD 0x24 66 #define TSADCV3_HSHUT_PD 0x28 67 #define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04) 68 #define TSADCV2_COMP_INT(chn) (0x30 + (chn) * 0x04) 69 #define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04) 70 #define TSADCV3_DATA(chn) (0x2c + (chn) * 0x04) 71 #define TSADCV3_COMP_INT(chn) (0x6c + (chn) * 0x04) 72 #define TSADCV3_COMP_SHUT(chn) (0x10c + (chn) * 0x04) 73 #define TSADCV2_HIGHT_INT_DEBOUNCE 0x60 74 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64 75 #define TSADCV3_HIGHT_INT_DEBOUNCE 0x14c 76 #define TSADCV3_HIGHT_TSHUT_DEBOUNCE 0x150 77 #define TSADCV2_AUTO_PERIOD 0x68 78 #define TSADCV2_AUTO_PERIOD_HT 0x6c 79 #define TSADCV3_AUTO_PERIOD 0x154 80 #define TSADCV3_AUTO_PERIOD_HT 0x158 81 #define TSADCV3_Q_MAX 0x210 82 83 #define TSADCV2_AUTO_EN BIT(0) 84 #define TSADCV2_AUTO_EN_MASK BIT(16) 85 #define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn)) 86 #define TSADCV3_AUTO_SRC_EN(chn) BIT(chn) 87 #define TSADCV3_AUTO_SRC_EN_MASK(chn) BIT(16 + (chn)) 88 #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8) 89 #define TSADCV2_AUTO_TSHUT_POLARITY_MASK BIT(24) 90 91 #define TSADCV3_AUTO_Q_SEL_EN BIT(1) 92 #define TSADCV3_AUTO_Q_SEL_EN_MASK BIT(17) 93 94 #define TSADCV2_INT_SRC_EN(chn) BIT(chn) 95 #define TSADCV2_INT_SRC_EN_MASK(chn) BIT(16 + (chn)) 96 #define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn)) 97 #define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn)) 98 99 #define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8) 100 #define TSADCV3_INT_PD_CLEAR_MASK ~BIT(16) 101 #define TSADCV4_INT_PD_CLEAR_MASK 0xffffffff 102 103 #define TSADCV2_DATA_MASK 0xfff 104 #define TSADCV3_DATA_MASK 0x3ff 105 #define TSADCV4_DATA_MASK 0x1ff 106 #define TSADCV5_DATA_MASK 0x7ff 107 108 #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4 109 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4 110 #define TSADCV2_AUTO_PERIOD_TIME 250 111 #define TSADCV2_AUTO_PERIOD_HT_TIME 50 112 #define TSADCV3_AUTO_PERIOD_TIME 1875 113 #define TSADCV3_AUTO_PERIOD_HT_TIME 1875 114 #define TSADCV5_AUTO_PERIOD_TIME 1622 /* 2.5ms */ 115 #define TSADCV5_AUTO_PERIOD_HT_TIME 1622 /* 2.5ms */ 116 #define TSADCV6_AUTO_PERIOD_TIME 5000 /* 2.5ms */ 117 #define TSADCV6_AUTO_PERIOD_HT_TIME 5000 /* 2.5ms */ 118 #define TSADCV7_AUTO_PERIOD_TIME 3000 /* 2.5ms */ 119 #define TSADCV7_AUTO_PERIOD_HT_TIME 3000 /* 2.5ms */ 120 #define TSADCV3_Q_MAX_VAL 0x7ff /* 11bit 2047 */ 121 #define TSADCV12_AUTO_PERIOD_TIME 3000 /* 2.5ms */ 122 #define TSADCV12_AUTO_PERIOD_HT_TIME 3000 /* 2.5ms */ 123 #define TSADCV12_Q_MAX_VAL 0xfff /* 12bit 4095 */ 124 #define TSADCV9_Q_MAX 0x210 125 #define TSADCV9_Q_MAX_VAL (0xffff0400 << 0) 126 127 #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */ 128 #define TSADCV5_USER_INTER_PD_SOC 0xfc0 /* 97us, at least 90us */ 129 130 #define GRF_SARADC_TESTBIT 0x0e644 131 #define GRF_TSADC_TESTBIT_L 0x0e648 132 #define GRF_TSADC_TESTBIT_H 0x0e64c 133 134 #define PX30_GRF_SOC_CON0 0x0400 135 #define PX30_GRF_SOC_CON2 0x0408 136 137 #define RK3562_GRF_TSADC_CON 0x0580 138 139 #define RK3568_GRF_TSADC_CON 0x0600 140 #define RK3528_GRF_TSADC_CON 0x40030 141 #define RK3568_GRF_TSADC_ANA_REG0 (0x10001 << 0) 142 #define RK3568_GRF_TSADC_ANA_REG1 (0x10001 << 1) 143 #define RK3568_GRF_TSADC_ANA_REG2 (0x10001 << 2) 144 #define RK3568_GRF_TSADC_TSEN (0x10001 << 8) 145 146 #define GRF_SARADC_TESTBIT_ON (0x10001 << 2) 147 #define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2) 148 #define GRF_TSADC_VCM_EN_L (0x10001 << 7) 149 #define GRF_TSADC_VCM_EN_H (0x10001 << 7) 150 151 #define GRF_CON_TSADC_CH_INV (0x10001 << 1) 152 #define PX30S_TSADC_TDC_MODE (0x10001 << 4) 153 154 #define MIN_TEMP (-40000) 155 #define LOWEST_TEMP (-273000) 156 #define MAX_TEMP (125000) 157 #define MAX_ENV_TEMP (85000) 158 159 #define BASE (1024) 160 #define BASE_SHIFT (10) 161 #define START_DEBOUNCE_COUNT (100) 162 #define HIGHER_DEBOUNCE_TEMP (30000) 163 #define LOWER_DEBOUNCE_TEMP (15000) 164 165 /** 166 * struct tsadc_table - hold information about code and temp mapping 167 * @code: raw code from tsadc ip 168 * @temp: the mapping temperature 169 */ 170 171 struct tsadc_table { 172 unsigned long code; 173 int temp; 174 }; 175 176 struct chip_tsadc_table { 177 const struct tsadc_table *id; 178 unsigned int length; 179 u32 data_mask; 180 /* Tsadc is linear, using linear parameters */ 181 int knum; 182 int bnum; 183 enum adc_sort_mode mode; 184 }; 185 186 enum sensor_id { 187 SENSOR_CPU = 0, 188 SENSOR_GPU, 189 }; 190 191 struct rockchip_tsadc_chip { 192 /* The sensor id of chip correspond to the ADC channel */ 193 int chn_id[SOC_MAX_SENSORS]; 194 int chn_num; 195 fdt_addr_t base; 196 fdt_addr_t grf; 197 198 /* The hardware-controlled tshut property */ 199 int tshut_temp; 200 enum tshut_mode tshut_mode; 201 enum tshut_polarity tshut_polarity; 202 203 void (*tsadc_control)(struct udevice *dev, bool enable); 204 void (*tsadc_init)(struct udevice *dev); 205 int (*tsadc_get_temp)(struct udevice *dev, int chn, 206 int *temp); 207 void (*irq_ack)(struct udevice *dev); 208 void (*set_alarm_temp)(struct udevice *dev, 209 int chn, int temp); 210 void (*set_tshut_temp)(struct udevice *dev, 211 int chn, int temp); 212 void (*set_tshut_mode)(struct udevice *dev, int chn, enum tshut_mode m); 213 struct chip_tsadc_table table; 214 }; 215 216 struct rockchip_thermal_priv { 217 void *base; 218 void *grf; 219 enum tshut_mode tshut_mode; 220 enum tshut_polarity tshut_polarity; 221 const struct rockchip_tsadc_chip *data; 222 }; 223 224 static const struct tsadc_table rk1808_code_table[] = { 225 {0, -40000}, 226 {3455, -40000}, 227 {3463, -35000}, 228 {3471, -30000}, 229 {3479, -25000}, 230 {3487, -20000}, 231 {3495, -15000}, 232 {3503, -10000}, 233 {3511, -5000}, 234 {3519, 0}, 235 {3527, 5000}, 236 {3535, 10000}, 237 {3543, 15000}, 238 {3551, 20000}, 239 {3559, 25000}, 240 {3567, 30000}, 241 {3576, 35000}, 242 {3584, 40000}, 243 {3592, 45000}, 244 {3600, 50000}, 245 {3609, 55000}, 246 {3617, 60000}, 247 {3625, 65000}, 248 {3633, 70000}, 249 {3642, 75000}, 250 {3650, 80000}, 251 {3659, 85000}, 252 {3667, 90000}, 253 {3675, 95000}, 254 {3684, 100000}, 255 {3692, 105000}, 256 {3701, 110000}, 257 {3709, 115000}, 258 {3718, 120000}, 259 {3726, 125000}, 260 {TSADCV2_DATA_MASK, 125000}, 261 }; 262 263 static const struct tsadc_table rk3228_code_table[] = { 264 {0, -40000}, 265 {588, -40000}, 266 {593, -35000}, 267 {598, -30000}, 268 {603, -25000}, 269 {608, -20000}, 270 {613, -15000}, 271 {618, -10000}, 272 {623, -5000}, 273 {629, 0}, 274 {634, 5000}, 275 {639, 10000}, 276 {644, 15000}, 277 {649, 20000}, 278 {654, 25000}, 279 {660, 30000}, 280 {665, 35000}, 281 {670, 40000}, 282 {675, 45000}, 283 {681, 50000}, 284 {686, 55000}, 285 {691, 60000}, 286 {696, 65000}, 287 {702, 70000}, 288 {707, 75000}, 289 {712, 80000}, 290 {717, 85000}, 291 {723, 90000}, 292 {728, 95000}, 293 {733, 100000}, 294 {738, 105000}, 295 {744, 110000}, 296 {749, 115000}, 297 {754, 120000}, 298 {760, 125000}, 299 {TSADCV2_DATA_MASK, 125000}, 300 }; 301 302 static const struct tsadc_table rk3288_code_table[] = { 303 {TSADCV2_DATA_MASK, -40000}, 304 {3800, -40000}, 305 {3792, -35000}, 306 {3783, -30000}, 307 {3774, -25000}, 308 {3765, -20000}, 309 {3756, -15000}, 310 {3747, -10000}, 311 {3737, -5000}, 312 {3728, 0}, 313 {3718, 5000}, 314 {3708, 10000}, 315 {3698, 15000}, 316 {3688, 20000}, 317 {3678, 25000}, 318 {3667, 30000}, 319 {3656, 35000}, 320 {3645, 40000}, 321 {3634, 45000}, 322 {3623, 50000}, 323 {3611, 55000}, 324 {3600, 60000}, 325 {3588, 65000}, 326 {3575, 70000}, 327 {3563, 75000}, 328 {3550, 80000}, 329 {3537, 85000}, 330 {3524, 90000}, 331 {3510, 95000}, 332 {3496, 100000}, 333 {3482, 105000}, 334 {3467, 110000}, 335 {3452, 115000}, 336 {3437, 120000}, 337 {3421, 125000}, 338 }; 339 340 static const struct tsadc_table rk3328_code_table[] = { 341 {0, -40000}, 342 {296, -40000}, 343 {304, -35000}, 344 {313, -30000}, 345 {331, -20000}, 346 {340, -15000}, 347 {349, -10000}, 348 {359, -5000}, 349 {368, 0}, 350 {378, 5000}, 351 {388, 10000}, 352 {398, 15000}, 353 {408, 20000}, 354 {418, 25000}, 355 {429, 30000}, 356 {440, 35000}, 357 {451, 40000}, 358 {462, 45000}, 359 {473, 50000}, 360 {485, 55000}, 361 {496, 60000}, 362 {508, 65000}, 363 {521, 70000}, 364 {533, 75000}, 365 {546, 80000}, 366 {559, 85000}, 367 {572, 90000}, 368 {586, 95000}, 369 {600, 100000}, 370 {614, 105000}, 371 {629, 110000}, 372 {644, 115000}, 373 {659, 120000}, 374 {675, 125000}, 375 {TSADCV2_DATA_MASK, 125000}, 376 }; 377 378 static const struct tsadc_table rk3368_code_table[] = { 379 {0, -40000}, 380 {106, -40000}, 381 {108, -35000}, 382 {110, -30000}, 383 {112, -25000}, 384 {114, -20000}, 385 {116, -15000}, 386 {118, -10000}, 387 {120, -5000}, 388 {122, 0}, 389 {124, 5000}, 390 {126, 10000}, 391 {128, 15000}, 392 {130, 20000}, 393 {132, 25000}, 394 {134, 30000}, 395 {136, 35000}, 396 {138, 40000}, 397 {140, 45000}, 398 {142, 50000}, 399 {144, 55000}, 400 {146, 60000}, 401 {148, 65000}, 402 {150, 70000}, 403 {152, 75000}, 404 {154, 80000}, 405 {156, 85000}, 406 {158, 90000}, 407 {160, 95000}, 408 {162, 100000}, 409 {163, 105000}, 410 {165, 110000}, 411 {167, 115000}, 412 {169, 120000}, 413 {171, 125000}, 414 {TSADCV3_DATA_MASK, 125000}, 415 }; 416 417 static const struct tsadc_table rk3399_code_table[] = { 418 {0, -40000}, 419 {402, -40000}, 420 {410, -35000}, 421 {419, -30000}, 422 {427, -25000}, 423 {436, -20000}, 424 {444, -15000}, 425 {453, -10000}, 426 {461, -5000}, 427 {470, 0}, 428 {478, 5000}, 429 {487, 10000}, 430 {496, 15000}, 431 {504, 20000}, 432 {513, 25000}, 433 {521, 30000}, 434 {530, 35000}, 435 {538, 40000}, 436 {547, 45000}, 437 {555, 50000}, 438 {564, 55000}, 439 {573, 60000}, 440 {581, 65000}, 441 {590, 70000}, 442 {599, 75000}, 443 {607, 80000}, 444 {616, 85000}, 445 {624, 90000}, 446 {633, 95000}, 447 {642, 100000}, 448 {650, 105000}, 449 {659, 110000}, 450 {668, 115000}, 451 {677, 120000}, 452 {685, 125000}, 453 {TSADCV3_DATA_MASK, 125000}, 454 }; 455 456 static const struct tsadc_table rk3528_code_table[] = { 457 {0, -40000}, 458 {1419, -40000}, 459 {1427, -35000}, 460 {1435, -30000}, 461 {1443, -25000}, 462 {1452, -20000}, 463 {1460, -15000}, 464 {1468, -10000}, 465 {1477, -5000}, 466 {1486, 0}, 467 {1494, 5000}, 468 {1502, 10000}, 469 {1510, 15000}, 470 {1519, 20000}, 471 {1527, 25000}, 472 {1535, 30000}, 473 {1544, 35000}, 474 {1552, 40000}, 475 {1561, 45000}, 476 {1569, 50000}, 477 {1578, 55000}, 478 {1586, 60000}, 479 {1594, 65000}, 480 {1603, 70000}, 481 {1612, 75000}, 482 {1620, 80000}, 483 {1628, 85000}, 484 {1637, 90000}, 485 {1646, 95000}, 486 {1654, 100000}, 487 {1662, 105000}, 488 {1671, 110000}, 489 {1679, 115000}, 490 {1688, 120000}, 491 {1696, 125000}, 492 {TSADCV5_DATA_MASK, 125000}, 493 }; 494 495 static const struct tsadc_table rk3562_code_table[] = { 496 {0, -40000}, 497 {1419, -40000}, 498 {1428, -35000}, 499 {1436, -30000}, 500 {1445, -25000}, 501 {1453, -20000}, 502 {1462, -15000}, 503 {1470, -10000}, 504 {1479, -5000}, 505 {1487, 0}, 506 {1496, 5000}, 507 {1504, 10000}, 508 {1512, 15000}, 509 {1521, 20000}, 510 {1529, 25000}, 511 {1538, 30000}, 512 {1546, 35000}, 513 {1555, 40000}, 514 {1563, 45000}, 515 {1572, 50000}, 516 {1580, 55000}, 517 {1589, 60000}, 518 {1598, 65000}, 519 {1606, 70000}, 520 {1615, 75000}, 521 {1623, 80000}, 522 {1632, 85000}, 523 {1640, 90000}, 524 {1648, 95000}, 525 {1657, 100000}, 526 {1666, 105000}, 527 {1674, 110000}, 528 {1682, 115000}, 529 {1691, 120000}, 530 {1699, 125000}, 531 {TSADCV2_DATA_MASK, 125000}, 532 }; 533 534 static const struct tsadc_table rk3568_code_table[] = { 535 {0, -40000}, 536 {1584, -40000}, 537 {1620, -35000}, 538 {1652, -30000}, 539 {1688, -25000}, 540 {1720, -20000}, 541 {1756, -15000}, 542 {1788, -10000}, 543 {1824, -5000}, 544 {1856, 0}, 545 {1892, 5000}, 546 {1924, 10000}, 547 {1956, 15000}, 548 {1992, 20000}, 549 {2024, 25000}, 550 {2060, 30000}, 551 {2092, 35000}, 552 {2128, 40000}, 553 {2160, 45000}, 554 {2196, 50000}, 555 {2228, 55000}, 556 {2264, 60000}, 557 {2300, 65000}, 558 {2332, 70000}, 559 {2368, 75000}, 560 {2400, 80000}, 561 {2436, 85000}, 562 {2468, 90000}, 563 {2500, 95000}, 564 {2536, 100000}, 565 {2572, 105000}, 566 {2604, 110000}, 567 {2636, 115000}, 568 {2672, 120000}, 569 {2704, 125000}, 570 {TSADCV2_DATA_MASK, 125000}, 571 }; 572 573 static const struct tsadc_table rk3588_code_table[] = { 574 {0, -40000}, 575 {215, -40000}, 576 {285, 25000}, 577 {350, 85000}, 578 {395, 125000}, 579 {TSADCV4_DATA_MASK, 125000}, 580 }; 581 582 /* 583 * Struct used for matching a device 584 */ 585 struct of_device_id { 586 char compatible[32]; 587 const void *data; 588 }; 589 590 static int tsadc_code_to_temp(struct chip_tsadc_table *table, u32 code, 591 int *temp) 592 { 593 unsigned int low = 1; 594 unsigned int high = table->length - 1; 595 unsigned int mid = (low + high) / 2; 596 unsigned int num; 597 unsigned long denom; 598 599 if (table->knum) { 600 *temp = (((int)code - table->bnum) * 10000 / table->knum) * 100; 601 if (*temp < MIN_TEMP || *temp > MAX_TEMP) 602 return -EAGAIN; 603 return 0; 604 } 605 606 switch (table->mode) { 607 case ADC_DECREMENT: 608 code &= table->data_mask; 609 if (code < table->id[high].code) 610 return -EAGAIN; /* Incorrect reading */ 611 612 while (low <= high) { 613 if (code >= table->id[mid].code && 614 code < table->id[mid - 1].code) 615 break; 616 else if (code < table->id[mid].code) 617 low = mid + 1; 618 else 619 high = mid - 1; 620 621 mid = (low + high) / 2; 622 } 623 break; 624 case ADC_INCREMENT: 625 code &= table->data_mask; 626 if (code < table->id[low].code) 627 return -EAGAIN; /* Incorrect reading */ 628 629 while (low <= high) { 630 if (code <= table->id[mid].code && 631 code > table->id[mid - 1].code) 632 break; 633 else if (code > table->id[mid].code) 634 low = mid + 1; 635 else 636 high = mid - 1; 637 638 mid = (low + high) / 2; 639 } 640 break; 641 default: 642 printf("%s: Invalid the conversion table mode=%d\n", 643 __func__, table->mode); 644 return -EINVAL; 645 } 646 647 /* 648 * The 5C granularity provided by the table is too much. Let's 649 * assume that the relationship between sensor readings and 650 * temperature between 2 table entries is linear and interpolate 651 * to produce less granular result. 652 */ 653 num = table->id[mid].temp - table->id[mid - 1].temp; 654 num *= abs(table->id[mid - 1].code - code); 655 denom = abs(table->id[mid - 1].code - table->id[mid].code); 656 *temp = table->id[mid - 1].temp + (num / denom); 657 658 return 0; 659 } 660 661 static u32 tsadc_temp_to_code_v2(struct chip_tsadc_table table, 662 int temp) 663 { 664 int high, low, mid; 665 unsigned long num; 666 unsigned int denom; 667 u32 error = table.data_mask; 668 669 if (table.knum) 670 return (((temp / 1000) * table.knum) / 1000 + table.bnum); 671 672 low = 0; 673 high = table.length - 1; 674 mid = (high + low) / 2; 675 676 /* Return mask code data when the temp is over table range */ 677 if (temp < table.id[low].temp || temp > table.id[high].temp) 678 goto exit; 679 680 while (low <= high) { 681 if (temp == table.id[mid].temp) 682 return table.id[mid].code; 683 else if (temp < table.id[mid].temp) 684 high = mid - 1; 685 else 686 low = mid + 1; 687 mid = (low + high) / 2; 688 } 689 690 num = abs(table.id[mid + 1].code - table.id[mid].code); 691 num *= temp - table.id[mid].temp; 692 denom = table.id[mid + 1].temp - table.id[mid].temp; 693 694 switch (table.mode) { 695 case ADC_DECREMENT: 696 return table.id[mid].code - (num / denom); 697 case ADC_INCREMENT: 698 return table.id[mid].code + (num / denom); 699 default: 700 pr_err("%s: unknown table mode: %d\n", __func__, table.mode); 701 return error; 702 } 703 704 exit: 705 pr_err("%s: Invalid conversion table: code=%d, temperature=%d\n", 706 __func__, error, temp); 707 708 return error; 709 } 710 711 static void tsadc_irq_ack_v2(struct udevice *dev) 712 { 713 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 714 u32 val; 715 716 val = readl(priv->base + TSADCV2_INT_PD); 717 writel(val & TSADCV2_INT_PD_CLEAR_MASK, priv->base + TSADCV2_INT_PD); 718 } 719 720 static void tsadc_irq_ack_v3(struct udevice *dev) 721 { 722 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 723 u32 val; 724 725 val = readl(priv->base + TSADCV2_INT_PD); 726 writel(val & TSADCV3_INT_PD_CLEAR_MASK, priv->base + TSADCV2_INT_PD); 727 } 728 729 static void tsadc_irq_ack_v4(struct udevice *dev) 730 { 731 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 732 u32 val; 733 734 val = readl(priv->base + TSADCV3_INT_PD); 735 writel(val & TSADCV4_INT_PD_CLEAR_MASK, priv->base + TSADCV3_INT_PD); 736 val = readl(priv->base + TSADCV3_HSHUT_PD); 737 writel(val & TSADCV3_INT_PD_CLEAR_MASK, priv->base + TSADCV3_HSHUT_PD); 738 } 739 740 static void tsadc_control_v2(struct udevice *dev, bool enable) 741 { 742 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 743 u32 val; 744 745 val = readl(priv->base + TSADCV2_AUTO_CON); 746 if (enable) 747 val |= TSADCV2_AUTO_EN; 748 else 749 val &= ~TSADCV2_AUTO_EN; 750 751 writel(val, priv->base + TSADCV2_AUTO_CON); 752 } 753 754 static void tsadc_control_v3(struct udevice *dev, bool enable) 755 { 756 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 757 u32 val; 758 759 val = readl(priv->base + TSADCV2_AUTO_CON); 760 if (enable) 761 val |= TSADCV2_AUTO_EN | TSADCV3_AUTO_Q_SEL_EN; 762 else 763 val &= ~TSADCV2_AUTO_EN; 764 765 writel(val, priv->base + TSADCV2_AUTO_CON); 766 } 767 768 static void tsadc_control_v4(struct udevice *dev, bool enable) 769 { 770 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 771 u32 val; 772 773 if (enable) 774 val = TSADCV2_AUTO_EN | TSADCV2_AUTO_EN_MASK; 775 else 776 val = TSADCV2_AUTO_EN_MASK; 777 778 writel(val, priv->base + TSADCV2_AUTO_CON); 779 } 780 781 static void tsadc_init_v2(struct udevice *dev) 782 { 783 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 784 785 writel(TSADCV2_AUTO_PERIOD_TIME, 786 priv->base + TSADCV2_AUTO_PERIOD); 787 writel(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, 788 priv->base + TSADCV2_HIGHT_INT_DEBOUNCE); 789 writel(TSADCV2_AUTO_PERIOD_HT_TIME, 790 priv->base + TSADCV2_AUTO_PERIOD_HT); 791 writel(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, 792 priv->base + TSADCV2_HIGHT_TSHUT_DEBOUNCE); 793 794 if (priv->tshut_polarity == TSHUT_HIGH_ACTIVE) 795 writel(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 796 priv->base + TSADCV2_AUTO_CON); 797 else 798 writel(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 799 priv->base + TSADCV2_AUTO_CON); 800 } 801 802 static void tsadc_init_v3(struct udevice *dev) 803 { 804 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 805 806 if (!IS_ERR(priv->grf)) { 807 writel(GRF_TSADC_VCM_EN_L, priv->grf + GRF_TSADC_TESTBIT_L); 808 writel(GRF_TSADC_VCM_EN_H, priv->grf + GRF_TSADC_TESTBIT_H); 809 810 udelay(100);/* The spec note says at least 15 us */ 811 writel(GRF_SARADC_TESTBIT_ON, priv->grf + GRF_SARADC_TESTBIT); 812 writel(GRF_TSADC_TESTBIT_H_ON, priv->grf + GRF_TSADC_TESTBIT_H); 813 udelay(200);/* The spec note says at least 90 us */ 814 } 815 tsadc_init_v2(dev); 816 } 817 818 static void __maybe_unused tsadc_init_v5(struct udevice *dev) 819 { 820 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 821 822 /* Set interleave value to workround ic time sync issue */ 823 writel(TSADCV2_USER_INTER_PD_SOC, priv->base + 824 TSADCV2_USER_CON); 825 tsadc_init_v2(dev); 826 } 827 828 static void tsadc_init_v4(struct udevice *dev) 829 { 830 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 831 832 tsadc_init_v2(dev); 833 if (!IS_ERR(priv->grf)) 834 writel(GRF_CON_TSADC_CH_INV, priv->grf + PX30_GRF_SOC_CON2); 835 } 836 837 static void tsadc_init_v7(struct udevice *dev) 838 { 839 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 840 841 writel(TSADCV5_USER_INTER_PD_SOC, 842 priv->base + TSADCV2_USER_CON); 843 writel(TSADCV5_AUTO_PERIOD_TIME, 844 priv->base + TSADCV2_AUTO_PERIOD); 845 writel(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, 846 priv->base + TSADCV2_HIGHT_INT_DEBOUNCE); 847 writel(TSADCV5_AUTO_PERIOD_HT_TIME, 848 priv->base + TSADCV2_AUTO_PERIOD_HT); 849 writel(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, 850 priv->base + TSADCV2_HIGHT_TSHUT_DEBOUNCE); 851 852 if (priv->tshut_polarity == TSHUT_HIGH_ACTIVE) 853 writel(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 854 priv->base + TSADCV2_AUTO_CON); 855 else 856 writel(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 857 priv->base + TSADCV2_AUTO_CON); 858 859 if (!IS_ERR(priv->grf)) { 860 writel(RK3568_GRF_TSADC_TSEN, 861 priv->grf + RK3568_GRF_TSADC_CON); 862 udelay(15); 863 writel(RK3568_GRF_TSADC_ANA_REG0, 864 priv->grf + RK3568_GRF_TSADC_CON); 865 writel(RK3568_GRF_TSADC_ANA_REG1, 866 priv->grf + RK3568_GRF_TSADC_CON); 867 writel(RK3568_GRF_TSADC_ANA_REG2, 868 priv->grf + RK3568_GRF_TSADC_CON); 869 udelay(200); 870 } 871 } 872 873 static void tsadc_init_v8(struct udevice *dev) 874 { 875 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 876 877 writel(TSADCV6_AUTO_PERIOD_TIME, priv->base + TSADCV3_AUTO_PERIOD); 878 writel(TSADCV6_AUTO_PERIOD_HT_TIME, 879 priv->base + TSADCV3_AUTO_PERIOD_HT); 880 writel(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, 881 priv->base + TSADCV3_HIGHT_INT_DEBOUNCE); 882 writel(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, 883 priv->base + TSADCV3_HIGHT_TSHUT_DEBOUNCE); 884 885 if (priv->tshut_polarity == TSHUT_HIGH_ACTIVE) 886 writel(TSADCV2_AUTO_TSHUT_POLARITY_HIGH | 887 TSADCV2_AUTO_TSHUT_POLARITY_MASK, 888 priv->base + TSADCV2_AUTO_CON); 889 else 890 writel(TSADCV2_AUTO_TSHUT_POLARITY_MASK, 891 priv->base + TSADCV2_AUTO_CON); 892 }; 893 894 static void tsadc_init_v9(struct udevice *dev) 895 { 896 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 897 898 tsadc_init_v2(dev); 899 if (!IS_ERR(priv->grf)) 900 writel(PX30S_TSADC_TDC_MODE, priv->grf + PX30_GRF_SOC_CON0); 901 } 902 903 static void tsadc_init_v11(struct udevice *dev) 904 { 905 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 906 907 writel(TSADCV7_AUTO_PERIOD_TIME, priv->base + TSADCV3_AUTO_PERIOD); 908 writel(TSADCV7_AUTO_PERIOD_HT_TIME, 909 priv->base + TSADCV3_AUTO_PERIOD_HT); 910 writel(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, 911 priv->base + TSADCV3_HIGHT_INT_DEBOUNCE); 912 writel(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, 913 priv->base + TSADCV3_HIGHT_TSHUT_DEBOUNCE); 914 writel(TSADCV3_Q_MAX_VAL, priv->base + TSADCV3_Q_MAX); 915 writel(TSADCV3_AUTO_Q_SEL_EN | TSADCV3_AUTO_Q_SEL_EN_MASK, 916 priv->base + TSADCV2_AUTO_CON); 917 918 if (priv->tshut_polarity == TSHUT_HIGH_ACTIVE) 919 writel(TSADCV2_AUTO_TSHUT_POLARITY_HIGH | 920 TSADCV2_AUTO_TSHUT_POLARITY_MASK, 921 priv->base + TSADCV2_AUTO_CON); 922 else 923 writel(TSADCV2_AUTO_TSHUT_POLARITY_MASK, 924 priv->base + TSADCV2_AUTO_CON); 925 926 if (!IS_ERR(priv->grf)) { 927 writel(RK3568_GRF_TSADC_TSEN, 928 priv->grf + RK3528_GRF_TSADC_CON); 929 udelay(15); 930 writel(RK3568_GRF_TSADC_ANA_REG0, 931 priv->grf + RK3528_GRF_TSADC_CON); 932 writel(RK3568_GRF_TSADC_ANA_REG1, 933 priv->grf + RK3528_GRF_TSADC_CON); 934 writel(RK3568_GRF_TSADC_ANA_REG2, 935 priv->grf + RK3528_GRF_TSADC_CON); 936 udelay(200); 937 } 938 } 939 940 static void tsadc_init_v12(struct udevice *dev) 941 { 942 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 943 944 writel(TSADCV12_AUTO_PERIOD_TIME, 945 priv->base + TSADCV3_AUTO_PERIOD); 946 writel(TSADCV12_AUTO_PERIOD_HT_TIME, 947 priv->base + TSADCV3_AUTO_PERIOD_HT); 948 writel(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, 949 priv->base + TSADCV3_HIGHT_INT_DEBOUNCE); 950 writel(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, 951 priv->base + TSADCV3_HIGHT_TSHUT_DEBOUNCE); 952 writel(TSADCV12_Q_MAX_VAL, 953 priv->base + TSADCV9_Q_MAX); 954 writel(TSADCV3_AUTO_Q_SEL_EN | TSADCV3_AUTO_Q_SEL_EN_MASK, 955 priv->base + TSADCV2_AUTO_CON); 956 if (priv->tshut_polarity == TSHUT_HIGH_ACTIVE) 957 writel(TSADCV2_AUTO_TSHUT_POLARITY_HIGH | 958 TSADCV2_AUTO_TSHUT_POLARITY_MASK, 959 priv->base + TSADCV2_AUTO_CON); 960 else 961 writel(TSADCV2_AUTO_TSHUT_POLARITY_MASK, 962 priv->base + TSADCV2_AUTO_CON); 963 964 if (!IS_ERR(priv->grf)) { 965 writel(RK3568_GRF_TSADC_TSEN, 966 priv->grf + RK3562_GRF_TSADC_CON); 967 udelay(15); 968 writel(RK3568_GRF_TSADC_ANA_REG0, 969 priv->grf + RK3562_GRF_TSADC_CON); 970 writel(RK3568_GRF_TSADC_ANA_REG1, 971 priv->grf + RK3562_GRF_TSADC_CON); 972 writel(RK3568_GRF_TSADC_ANA_REG2, 973 priv->grf + RK3562_GRF_TSADC_CON); 974 udelay(200); 975 } 976 } 977 978 static int tsadc_get_temp_v2(struct udevice *dev, 979 int chn, int *temp) 980 { 981 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 982 struct chip_tsadc_table table = priv->data->table; 983 u32 val; 984 985 val = readl(priv->base + TSADCV2_DATA(chn)); 986 987 return tsadc_code_to_temp(&table, val, temp); 988 } 989 990 static int predict_temp(int temp) 991 { 992 /* 993 * The deviation of prediction. the temperature will not change rapidly, 994 * so this cov_q is small 995 */ 996 int cov_q = 18; 997 /* 998 * The deviation of tsadc's reading, deviation of tsadc is very big when 999 * abnormal temperature is get 1000 */ 1001 int cov_r = 542; 1002 1003 int gain; 1004 int temp_mid; 1005 int temp_now; 1006 int prob_mid; 1007 int prob_now; 1008 static int temp_last = LOWEST_TEMP; 1009 static int prob_last = 160; 1010 static int bounding_cnt; 1011 1012 /* 1013 * init temp_last with a more suitable value, which mostly equals to 1014 * temp reading from tsadc, but not higher than MAX_ENV_TEMP. If the 1015 * temp is higher than MAX_ENV_TEMP, it is assumed to be abnormal 1016 * value and temp_last is adjusted to MAX_ENV_TEMP. 1017 */ 1018 if (temp_last == LOWEST_TEMP) 1019 temp_last = min(temp, MAX_ENV_TEMP); 1020 1021 /* 1022 * Before START_DEBOUNCE_COUNT's samples of temperature, we consider 1023 * tsadc is stable, i.e. after that, the temperature may be not stable 1024 * and may have abnormal reading, so we set a bounding temperature. If 1025 * the reading from tsadc is too big, we set the delta temperature of 1026 * DEBOUNCE_TEMP/3 comparing to the last temperature. 1027 */ 1028 1029 if (bounding_cnt++ > START_DEBOUNCE_COUNT) { 1030 bounding_cnt = START_DEBOUNCE_COUNT; 1031 if (temp - temp_last > HIGHER_DEBOUNCE_TEMP) 1032 temp = temp_last + HIGHER_DEBOUNCE_TEMP / 3; 1033 if (temp_last - temp > LOWER_DEBOUNCE_TEMP) 1034 temp = temp_last - LOWER_DEBOUNCE_TEMP / 3; 1035 } 1036 1037 temp_mid = temp_last; 1038 1039 /* calculate the probability of this time's prediction */ 1040 prob_mid = prob_last + cov_q; 1041 1042 /* calculate the Kalman Gain */ 1043 gain = (prob_mid * BASE) / (prob_mid + cov_r); 1044 1045 /* calculate the prediction of temperature */ 1046 temp_now = (temp_mid * BASE + gain * (temp - temp_mid)) >> BASE_SHIFT; 1047 1048 /* 1049 * Base on this time's Kalman Gain, ajust our probability of prediction 1050 * for next time calculation 1051 */ 1052 prob_now = ((BASE - gain) * prob_mid) >> BASE_SHIFT; 1053 1054 prob_last = prob_now; 1055 temp_last = temp_now; 1056 1057 return temp_last; 1058 } 1059 1060 static int tsadc_get_temp_v3(struct udevice *dev, 1061 int chn, int *temp) 1062 { 1063 int ret; 1064 1065 ret = tsadc_get_temp_v2(dev, chn, temp); 1066 if (!ret) 1067 *temp = predict_temp(*temp); 1068 1069 return ret; 1070 } 1071 1072 static int tsadc_get_temp_v4(struct udevice *dev, int chn, int *temp) 1073 { 1074 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 1075 struct chip_tsadc_table table = priv->data->table; 1076 u32 val; 1077 1078 val = readl(priv->base + TSADCV3_DATA(chn)); 1079 1080 return tsadc_code_to_temp(&table, val, temp); 1081 } 1082 1083 static void tsadc_alarm_temp_v2(struct udevice *dev, 1084 int chn, int temp) 1085 { 1086 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 1087 struct chip_tsadc_table table = priv->data->table; 1088 u32 alarm_value, int_en; 1089 1090 alarm_value = tsadc_temp_to_code_v2(table, temp); 1091 if (alarm_value == table.data_mask) 1092 return; 1093 1094 writel(alarm_value, priv->base + TSADCV2_COMP_INT(chn)); 1095 1096 int_en = readl(priv->base + TSADCV2_INT_EN); 1097 int_en |= TSADCV2_INT_SRC_EN(chn); 1098 writel(int_en, priv->base + TSADCV2_INT_EN); 1099 } 1100 1101 static void tsadc_alarm_temp_v3(struct udevice *dev, int chn, int temp) 1102 { 1103 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 1104 struct chip_tsadc_table table = priv->data->table; 1105 u32 alarm_value; 1106 1107 alarm_value = tsadc_temp_to_code_v2(table, temp); 1108 if (alarm_value == table.data_mask) 1109 return; 1110 1111 writel(alarm_value, priv->base + TSADCV3_COMP_INT(chn)); 1112 writel(TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn), 1113 priv->base + TSADCV3_HT_INT_EN); 1114 } 1115 1116 static void tsadc_tshut_temp_v2(struct udevice *dev, 1117 int chn, int temp) 1118 { 1119 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 1120 struct chip_tsadc_table table = priv->data->table; 1121 u32 tshut_value, val; 1122 1123 tshut_value = tsadc_temp_to_code_v2(table, temp); 1124 if (tshut_value == table.data_mask) 1125 return; 1126 1127 writel(tshut_value, priv->base + TSADCV2_COMP_SHUT(chn)); 1128 1129 /* TSHUT will be valid */ 1130 val = readl(priv->base + TSADCV2_AUTO_CON); 1131 writel(val | TSADCV2_AUTO_SRC_EN(chn), priv->base + TSADCV2_AUTO_CON); 1132 } 1133 1134 static void tsadc_tshut_temp_v3(struct udevice *dev, int chn, int temp) 1135 { 1136 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 1137 struct chip_tsadc_table table = priv->data->table; 1138 u32 tshut_value; 1139 1140 tshut_value = tsadc_temp_to_code_v2(table, temp); 1141 if (tshut_value == table.data_mask) 1142 return; 1143 1144 writel(tshut_value, priv->base + TSADCV3_COMP_SHUT(chn)); 1145 writel(TSADCV3_AUTO_SRC_EN(chn) | TSADCV3_AUTO_SRC_EN_MASK(chn), 1146 priv->base + TSADCV3_AUTO_SRC_CON); 1147 } 1148 1149 static void tsadc_tshut_mode_v2(struct udevice *dev, int chn, 1150 enum tshut_mode mode) 1151 { 1152 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 1153 u32 val; 1154 1155 val = readl(priv->base + TSADCV2_INT_EN); 1156 if (mode == TSHUT_MODE_GPIO) { 1157 val &= ~TSADCV2_SHUT_2CRU_SRC_EN(chn); 1158 val |= TSADCV2_SHUT_2GPIO_SRC_EN(chn); 1159 } else { 1160 val &= ~TSADCV2_SHUT_2GPIO_SRC_EN(chn); 1161 val |= TSADCV2_SHUT_2CRU_SRC_EN(chn); 1162 } 1163 1164 writel(val, priv->base + TSADCV2_INT_EN); 1165 } 1166 1167 static void tsadc_tshut_mode_v4(struct udevice *dev, int chn, 1168 enum tshut_mode mode) 1169 { 1170 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 1171 u32 val_gpio, val_cru; 1172 1173 if (mode == TSHUT_MODE_GPIO) { 1174 val_gpio = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn); 1175 val_cru = TSADCV2_INT_SRC_EN_MASK(chn); 1176 } else { 1177 val_cru = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn); 1178 val_gpio = TSADCV2_INT_SRC_EN_MASK(chn); 1179 } 1180 writel(val_gpio, priv->base + TSADCV3_HSHUT_GPIO_INT_EN); 1181 writel(val_cru, priv->base + TSADCV3_HSHUT_CRU_INT_EN); 1182 } 1183 1184 int rockchip_thermal_get_temp(struct udevice *dev, int *temp) 1185 { 1186 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 1187 1188 priv->data->tsadc_get_temp(dev, 0, temp); 1189 1190 return 0; 1191 } 1192 1193 static const struct dm_thermal_ops rockchip_thermal_ops = { 1194 .get_temp = rockchip_thermal_get_temp, 1195 }; 1196 1197 static const struct rockchip_tsadc_chip px30s_tsadc_data = { 1198 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1199 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1200 .chn_num = 2, /* 2 channels for tsadc */ 1201 1202 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ 1203 .tshut_temp = 95000, 1204 1205 .tsadc_init = tsadc_init_v9, 1206 .tsadc_control = tsadc_control_v2, 1207 .tsadc_get_temp = tsadc_get_temp_v2, 1208 .irq_ack = tsadc_irq_ack_v3, 1209 .set_alarm_temp = tsadc_alarm_temp_v2, 1210 .set_tshut_temp = tsadc_tshut_temp_v2, 1211 .set_tshut_mode = tsadc_tshut_mode_v2, 1212 1213 .table = { 1214 .knum = 2699, 1215 .bnum = 2796, 1216 .data_mask = TSADCV2_DATA_MASK, 1217 .mode = ADC_INCREMENT, 1218 }, 1219 }; 1220 1221 static const struct rockchip_tsadc_chip rk3308bs_tsadc_data = { 1222 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1223 .chn_num = 1, /* 1 channels for tsadc */ 1224 1225 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ 1226 .tshut_temp = 95000, 1227 1228 .tsadc_init = tsadc_init_v2, 1229 .tsadc_control = tsadc_control_v2, 1230 .tsadc_get_temp = tsadc_get_temp_v2, 1231 .irq_ack = tsadc_irq_ack_v3, 1232 .set_alarm_temp = tsadc_alarm_temp_v2, 1233 .set_tshut_temp = tsadc_tshut_temp_v2, 1234 .set_tshut_mode = tsadc_tshut_mode_v2, 1235 1236 .table = { 1237 .knum = 2699, 1238 .bnum = 2796, 1239 .data_mask = TSADCV2_DATA_MASK, 1240 .mode = ADC_INCREMENT, 1241 }, 1242 }; 1243 1244 static int rockchip_thermal_probe(struct udevice *dev) 1245 { 1246 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 1247 struct rockchip_tsadc_chip *tsadc; 1248 struct clk clk; 1249 int ret, i, shut_temp; 1250 1251 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 1252 ret = clk_set_defaults(dev); 1253 if (ret) 1254 printf("%s clk_set_defaults failed %d\n", __func__, ret); 1255 1256 if (soc_is_rk3308bs() || soc_is_px30s()) { 1257 ret = clk_get_by_name(dev, "tsadc", &clk); 1258 if (ret) { 1259 printf("%s get tsadc clk fail\n", __func__); 1260 return -EINVAL; 1261 } 1262 ret = clk_set_rate(&clk, 4000000); 1263 if (ret < 0) { 1264 printf("%s: failed to set tsadc clk rate for %s\n", 1265 __func__, dev_read_name(dev)); 1266 return -EINVAL; 1267 } 1268 } 1269 if (soc_is_rk3308bs()) 1270 tsadc = (struct rockchip_tsadc_chip *)&rk3308bs_tsadc_data; 1271 else if (soc_is_px30s()) 1272 tsadc = (struct rockchip_tsadc_chip *)&px30s_tsadc_data; 1273 else 1274 tsadc = (struct rockchip_tsadc_chip *)dev_get_driver_data(dev); 1275 1276 priv->data = tsadc; 1277 1278 priv->tshut_mode = dev_read_u32_default(dev, 1279 "rockchip,hw-tshut-mode", 1280 -1); 1281 if (priv->tshut_mode < 0) 1282 priv->tshut_mode = priv->data->tshut_mode; 1283 1284 priv->tshut_polarity = dev_read_u32_default(dev, 1285 "rockchip,hw-tshut-polarity", 1286 -1); 1287 if (priv->tshut_polarity < 0) 1288 priv->tshut_polarity = tsadc->tshut_polarity; 1289 1290 if (priv->tshut_mode == TSHUT_MODE_GPIO) 1291 pinctrl_select_state(dev, "otpout"); 1292 else if (soc_is_rk3308()) 1293 pinctrl_select_state(dev, "gpio"); 1294 1295 tsadc->tsadc_init(dev); 1296 tsadc->irq_ack(dev); 1297 1298 shut_temp = dev_read_u32_default(dev, "rockchip,hw-tshut-temp", -1); 1299 if (shut_temp < 0) 1300 shut_temp = 120000; 1301 1302 for (i = 0; i < tsadc->chn_num; i++) { 1303 tsadc->set_alarm_temp(dev, i, tsadc->tshut_temp); 1304 tsadc->set_tshut_temp(dev, i, shut_temp); 1305 if (priv->tshut_mode == TSHUT_MODE_GPIO) 1306 tsadc->set_tshut_mode(dev, i, TSHUT_MODE_GPIO); 1307 else 1308 tsadc->set_tshut_mode(dev, i, TSHUT_MODE_CRU); 1309 } 1310 1311 tsadc->tsadc_control(dev, true); 1312 if (soc_is_rk3308bs() || soc_is_px30s()) 1313 mdelay(3); 1314 else 1315 udelay(1000); 1316 1317 debug("tsadc probed successfully\n"); 1318 1319 return 0; 1320 } 1321 1322 static int rockchip_thermal_ofdata_to_platdata(struct udevice *dev) 1323 { 1324 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 1325 1326 priv->base = dev_read_addr_ptr(dev); 1327 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1328 1329 return 0; 1330 } 1331 1332 static const struct rockchip_tsadc_chip rk1808_tsadc_data = { 1333 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1334 .chn_num = 1, /* one channel for tsadc */ 1335 1336 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1337 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1338 .tshut_temp = 95000, 1339 1340 .tsadc_init = tsadc_init_v2, 1341 .tsadc_control = tsadc_control_v3, 1342 .tsadc_get_temp = tsadc_get_temp_v2, 1343 .irq_ack = tsadc_irq_ack_v3, 1344 .set_alarm_temp = tsadc_alarm_temp_v2, 1345 .set_tshut_temp = tsadc_tshut_temp_v2, 1346 .set_tshut_mode = tsadc_tshut_mode_v2, 1347 1348 .table = { 1349 .id = rk1808_code_table, 1350 .length = ARRAY_SIZE(rk1808_code_table), 1351 .data_mask = TSADCV2_DATA_MASK, 1352 .mode = ADC_INCREMENT, 1353 }, 1354 }; 1355 1356 static const struct rockchip_tsadc_chip rk3228_tsadc_data = { 1357 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1358 .chn_num = 1, /* one channel for tsadc */ 1359 1360 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1361 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1362 .tshut_temp = 95000, 1363 1364 .tsadc_init = tsadc_init_v2, 1365 .tsadc_control = tsadc_control_v3, 1366 .tsadc_get_temp = tsadc_get_temp_v2, 1367 .irq_ack = tsadc_irq_ack_v3, 1368 .set_alarm_temp = tsadc_alarm_temp_v2, 1369 .set_tshut_temp = tsadc_tshut_temp_v2, 1370 .set_tshut_mode = tsadc_tshut_mode_v2, 1371 1372 .table = { 1373 .id = rk3228_code_table, 1374 .length = ARRAY_SIZE(rk3228_code_table), 1375 .data_mask = TSADCV3_DATA_MASK, 1376 .mode = ADC_INCREMENT, 1377 }, 1378 }; 1379 1380 static const struct rockchip_tsadc_chip rk3288_tsadc_data = { 1381 .chn_id[SENSOR_CPU] = 1, /* cpu sensor is channel 1 */ 1382 .chn_id[SENSOR_GPU] = 2, /* gpu sensor is channel 2 */ 1383 .chn_num = 2, /* two channels for tsadc */ 1384 1385 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1386 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1387 .tshut_temp = 95000, 1388 1389 .tsadc_init = tsadc_init_v2, 1390 .tsadc_control = tsadc_control_v2, 1391 .tsadc_get_temp = tsadc_get_temp_v3, 1392 .irq_ack = tsadc_irq_ack_v2, 1393 .set_alarm_temp = tsadc_alarm_temp_v2, 1394 .set_tshut_temp = tsadc_tshut_temp_v2, 1395 .set_tshut_mode = tsadc_tshut_mode_v2, 1396 1397 .table = { 1398 .id = rk3288_code_table, 1399 .length = ARRAY_SIZE(rk3288_code_table), 1400 .data_mask = TSADCV2_DATA_MASK, 1401 .mode = ADC_DECREMENT, 1402 }, 1403 }; 1404 1405 static const struct rockchip_tsadc_chip rk3308_tsadc_data = { 1406 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1407 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1408 .chn_num = 2, /* 2 channels for tsadc */ 1409 1410 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ 1411 .tshut_temp = 95000, 1412 1413 .tsadc_init = tsadc_init_v4, 1414 .tsadc_control = tsadc_control_v3, 1415 .tsadc_get_temp = tsadc_get_temp_v2, 1416 .irq_ack = tsadc_irq_ack_v3, 1417 .set_alarm_temp = tsadc_alarm_temp_v2, 1418 .set_tshut_temp = tsadc_tshut_temp_v2, 1419 .set_tshut_mode = tsadc_tshut_mode_v2, 1420 1421 .table = { 1422 .id = rk3328_code_table, 1423 .length = ARRAY_SIZE(rk3328_code_table), 1424 .data_mask = TSADCV2_DATA_MASK, 1425 .mode = ADC_INCREMENT, 1426 }, 1427 }; 1428 1429 static const struct rockchip_tsadc_chip px30_tsadc_data = { 1430 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1431 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1432 .chn_num = 2, /* 2 channels for tsadc */ 1433 1434 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ 1435 .tshut_temp = 95000, 1436 1437 .tsadc_init = tsadc_init_v4, 1438 .tsadc_control = tsadc_control_v3, 1439 .tsadc_get_temp = tsadc_get_temp_v2, 1440 .irq_ack = tsadc_irq_ack_v3, 1441 .set_alarm_temp = tsadc_alarm_temp_v2, 1442 .set_tshut_temp = tsadc_tshut_temp_v2, 1443 .set_tshut_mode = tsadc_tshut_mode_v2, 1444 1445 .table = { 1446 .id = rk3328_code_table, 1447 .length = ARRAY_SIZE(rk3328_code_table), 1448 .data_mask = TSADCV2_DATA_MASK, 1449 .mode = ADC_INCREMENT, 1450 }, 1451 }; 1452 1453 static const struct rockchip_tsadc_chip rk3328_tsadc_data = { 1454 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1455 .chn_num = 1, /* one channels for tsadc */ 1456 1457 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ 1458 .tshut_temp = 95000, 1459 1460 .tsadc_init = tsadc_init_v2, 1461 .tsadc_control = tsadc_control_v3, 1462 .tsadc_get_temp = tsadc_get_temp_v2, 1463 .irq_ack = tsadc_irq_ack_v3, 1464 .set_alarm_temp = tsadc_alarm_temp_v2, 1465 .set_tshut_temp = tsadc_tshut_temp_v2, 1466 .set_tshut_mode = tsadc_tshut_mode_v2, 1467 1468 .table = { 1469 .id = rk3328_code_table, 1470 .length = ARRAY_SIZE(rk3328_code_table), 1471 .data_mask = TSADCV2_DATA_MASK, 1472 .mode = ADC_INCREMENT, 1473 }, 1474 }; 1475 1476 static const struct rockchip_tsadc_chip rk3366_tsadc_data = { 1477 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1478 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1479 .chn_num = 2, /* two channels for tsadc */ 1480 1481 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1482 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1483 .tshut_temp = 95000, 1484 1485 .tsadc_init = tsadc_init_v3, 1486 .tsadc_control = tsadc_control_v3, 1487 .tsadc_get_temp = tsadc_get_temp_v2, 1488 .irq_ack = tsadc_irq_ack_v3, 1489 .set_alarm_temp = tsadc_alarm_temp_v2, 1490 .set_tshut_temp = tsadc_tshut_temp_v2, 1491 .set_tshut_mode = tsadc_tshut_mode_v2, 1492 1493 .table = { 1494 .id = rk3228_code_table, 1495 .length = ARRAY_SIZE(rk3228_code_table), 1496 .data_mask = TSADCV3_DATA_MASK, 1497 .mode = ADC_INCREMENT, 1498 }, 1499 }; 1500 1501 static const struct rockchip_tsadc_chip rk3368_tsadc_data = { 1502 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1503 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1504 .chn_num = 2, /* two channels for tsadc */ 1505 1506 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1507 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1508 .tshut_temp = 95000, 1509 1510 .tsadc_init = tsadc_init_v2, 1511 .tsadc_control = tsadc_control_v2, 1512 .tsadc_get_temp = tsadc_get_temp_v2, 1513 .irq_ack = tsadc_irq_ack_v2, 1514 .set_alarm_temp = tsadc_alarm_temp_v2, 1515 .set_tshut_temp = tsadc_tshut_temp_v2, 1516 .set_tshut_mode = tsadc_tshut_mode_v2, 1517 1518 .table = { 1519 .id = rk3368_code_table, 1520 .length = ARRAY_SIZE(rk3368_code_table), 1521 .data_mask = TSADCV3_DATA_MASK, 1522 .mode = ADC_INCREMENT, 1523 }, 1524 }; 1525 1526 static const struct rockchip_tsadc_chip rk3399_tsadc_data = { 1527 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1528 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1529 .chn_num = 2, /* two channels for tsadc */ 1530 1531 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1532 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1533 .tshut_temp = 95000, 1534 1535 .tsadc_init = tsadc_init_v3, 1536 .tsadc_control = tsadc_control_v3, 1537 .tsadc_get_temp = tsadc_get_temp_v2, 1538 .irq_ack = tsadc_irq_ack_v3, 1539 .set_alarm_temp = tsadc_alarm_temp_v2, 1540 .set_tshut_temp = tsadc_tshut_temp_v2, 1541 .set_tshut_mode = tsadc_tshut_mode_v2, 1542 1543 .table = { 1544 .id = rk3399_code_table, 1545 .length = ARRAY_SIZE(rk3399_code_table), 1546 .data_mask = TSADCV3_DATA_MASK, 1547 .mode = ADC_INCREMENT, 1548 }, 1549 }; 1550 1551 static const struct rockchip_tsadc_chip rk3528_tsadc_data = { 1552 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1553 .chn_num = 1, /* one channels for tsadc */ 1554 1555 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via GPIO give PMIC */ 1556 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1557 .tshut_temp = 95000, 1558 1559 .tsadc_init = tsadc_init_v11, 1560 .tsadc_control = tsadc_control_v4, 1561 .tsadc_get_temp = tsadc_get_temp_v4, 1562 .irq_ack = tsadc_irq_ack_v4, 1563 .set_alarm_temp = tsadc_alarm_temp_v3, 1564 .set_tshut_temp = tsadc_tshut_temp_v3, 1565 .set_tshut_mode = tsadc_tshut_mode_v4, 1566 1567 .table = { 1568 .id = rk3528_code_table, 1569 .length = ARRAY_SIZE(rk3528_code_table), 1570 .data_mask = TSADCV2_DATA_MASK, 1571 .mode = ADC_INCREMENT, 1572 }, 1573 }; 1574 1575 static const struct rockchip_tsadc_chip rk3562_tsadc_data = { 1576 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1577 .chn_num = 1, /* one channels for tsadc */ 1578 1579 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1580 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1581 .tshut_temp = 95000, 1582 1583 .tsadc_init = tsadc_init_v12, 1584 .tsadc_control = tsadc_control_v4, 1585 .tsadc_get_temp = tsadc_get_temp_v4, 1586 .irq_ack = tsadc_irq_ack_v4, 1587 .set_alarm_temp = tsadc_alarm_temp_v3, 1588 .set_tshut_temp = tsadc_tshut_temp_v3, 1589 .set_tshut_mode = tsadc_tshut_mode_v4, 1590 1591 .table = { 1592 .id = rk3562_code_table, 1593 .length = ARRAY_SIZE(rk3562_code_table), 1594 .data_mask = TSADCV2_DATA_MASK, 1595 .mode = ADC_INCREMENT, 1596 }, 1597 }; 1598 1599 static const struct rockchip_tsadc_chip rk3568_tsadc_data = { 1600 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1601 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1602 .chn_num = 2, /* two channels for tsadc */ 1603 1604 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1605 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1606 .tshut_temp = 95000, 1607 1608 .tsadc_init = tsadc_init_v7, 1609 .tsadc_control = tsadc_control_v3, 1610 .tsadc_get_temp = tsadc_get_temp_v2, 1611 .irq_ack = tsadc_irq_ack_v3, 1612 .set_alarm_temp = tsadc_alarm_temp_v2, 1613 .set_tshut_temp = tsadc_tshut_temp_v2, 1614 .set_tshut_mode = tsadc_tshut_mode_v2, 1615 1616 .table = { 1617 .id = rk3568_code_table, 1618 .length = ARRAY_SIZE(rk3568_code_table), 1619 .data_mask = TSADCV2_DATA_MASK, 1620 .mode = ADC_INCREMENT, 1621 }, 1622 }; 1623 1624 static const struct rockchip_tsadc_chip rk3588_tsadc_data = { 1625 /* top, big_core0, big_core1, little_core, center, gpu, npu */ 1626 .chn_id = {0, 1, 2, 3, 4, 5, 6}, 1627 .chn_num = 7, /* seven channels for tsadc */ 1628 1629 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1630 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1631 .tshut_temp = 95000, 1632 1633 .tsadc_init = tsadc_init_v8, 1634 .tsadc_control = tsadc_control_v4, 1635 .tsadc_get_temp = tsadc_get_temp_v4, 1636 .irq_ack = tsadc_irq_ack_v4, 1637 .set_alarm_temp = tsadc_alarm_temp_v3, 1638 .set_tshut_temp = tsadc_tshut_temp_v3, 1639 .set_tshut_mode = tsadc_tshut_mode_v4, 1640 1641 .table = { 1642 .id = rk3588_code_table, 1643 .length = ARRAY_SIZE(rk3588_code_table), 1644 .data_mask = TSADCV4_DATA_MASK, 1645 .mode = ADC_INCREMENT, 1646 }, 1647 }; 1648 1649 static const struct udevice_id rockchip_thermal_match[] = { 1650 { 1651 .compatible = "rockchip,px30-tsadc", 1652 .data = (ulong)&px30_tsadc_data, 1653 }, 1654 { 1655 .compatible = "rockchip,px30s-tsadc", 1656 .data = (ulong)&px30s_tsadc_data, 1657 }, 1658 { 1659 .compatible = "rockchip,rk1808-tsadc", 1660 .data = (ulong)&rk1808_tsadc_data, 1661 }, 1662 { 1663 .compatible = "rockchip,rk3228-tsadc", 1664 .data = (ulong)&rk3228_tsadc_data, 1665 }, 1666 { 1667 .compatible = "rockchip,rk3288-tsadc", 1668 .data = (ulong)&rk3288_tsadc_data, 1669 }, 1670 { 1671 .compatible = "rockchip,rk3308-tsadc", 1672 .data = (ulong)&rk3308_tsadc_data, 1673 }, 1674 { 1675 .compatible = "rockchip,rk3308bs-tsadc", 1676 .data = (ulong)&rk3308bs_tsadc_data, 1677 }, 1678 { 1679 .compatible = "rockchip,rk3328-tsadc", 1680 .data = (ulong)&rk3328_tsadc_data, 1681 }, 1682 { 1683 .compatible = "rockchip,rk3366-tsadc", 1684 .data = (ulong)&rk3366_tsadc_data, 1685 }, 1686 { 1687 .compatible = "rockchip,rk3368-tsadc", 1688 .data = (ulong)&rk3368_tsadc_data, 1689 }, 1690 { 1691 .compatible = "rockchip,rk3399-tsadc", 1692 .data = (ulong)&rk3399_tsadc_data, 1693 }, 1694 { 1695 .compatible = "rockchip,rk3528-tsadc", 1696 .data = (ulong)&rk3528_tsadc_data, 1697 }, 1698 { 1699 .compatible = "rockchip,rk3562-tsadc", 1700 .data = (ulong)&rk3562_tsadc_data, 1701 }, 1702 { 1703 .compatible = "rockchip,rk3568-tsadc", 1704 .data = (ulong)&rk3568_tsadc_data, 1705 }, 1706 { 1707 .compatible = "rockchip,rk3588-tsadc", 1708 .data = (ulong)&rk3588_tsadc_data, 1709 }, 1710 { /* end */ }, 1711 }; 1712 1713 U_BOOT_DRIVER(rockchip_thermal) = { 1714 .name = "rockchip_thermal", 1715 .id = UCLASS_THERMAL, 1716 .of_match = rockchip_thermal_match, 1717 .priv_auto_alloc_size = sizeof(struct rockchip_thermal_priv), 1718 .ofdata_to_platdata = rockchip_thermal_ofdata_to_platdata, 1719 .ops = &rockchip_thermal_ops, 1720 .probe = rockchip_thermal_probe, 1721 }; 1722