1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6 #include <common.h> 7 #include <bitfield.h> 8 #include <thermal.h> 9 #include <dm.h> 10 #include <dm/pinctrl.h> 11 #include <div64.h> 12 #include <errno.h> 13 #include <syscon.h> 14 #include <asm/arch/clock.h> 15 #include <asm/arch/hardware.h> 16 #include <asm/io.h> 17 #include <dm/lists.h> 18 #include <clk.h> 19 #include <clk-uclass.h> 20 #include <reset.h> 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 /** 25 * If the temperature over a period of time High, 26 * the resulting TSHUT gave CRU module,let it reset the entire chip, 27 * or via GPIO give PMIC. 28 */ 29 enum tshut_mode { 30 TSHUT_MODE_CRU = 0, 31 TSHUT_MODE_GPIO, 32 }; 33 34 /** 35 * The system Temperature Sensors tshut(tshut) polarity 36 * the bit 8 is tshut polarity. 37 * 0: low active, 1: high active 38 */ 39 enum tshut_polarity { 40 TSHUT_LOW_ACTIVE = 0, 41 TSHUT_HIGH_ACTIVE, 42 }; 43 44 /** 45 * The conversion table has the adc value and temperature. 46 * ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table) 47 * ADC_INCREMENT: the adc value is incremental.(e.g. rk3368_code_table) 48 */ 49 enum adc_sort_mode { 50 ADC_DECREMENT = 0, 51 ADC_INCREMENT, 52 }; 53 54 #define SOC_MAX_SENSORS 2 55 56 #define TSADCV2_USER_CON 0x00 57 #define TSADCV2_AUTO_CON 0x04 58 #define TSADCV2_INT_EN 0x08 59 #define TSADCV2_INT_PD 0x0c 60 #define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04) 61 #define TSADCV2_COMP_INT(chn) (0x30 + (chn) * 0x04) 62 #define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04) 63 #define TSADCV2_HIGHT_INT_DEBOUNCE 0x60 64 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64 65 #define TSADCV2_AUTO_PERIOD 0x68 66 #define TSADCV2_AUTO_PERIOD_HT 0x6c 67 68 #define TSADCV2_AUTO_EN BIT(0) 69 #define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn)) 70 #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8) 71 72 #define TSADCV3_AUTO_Q_SEL_EN BIT(1) 73 74 #define TSADCV2_INT_SRC_EN(chn) BIT(chn) 75 #define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn)) 76 #define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn)) 77 78 #define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8) 79 #define TSADCV3_INT_PD_CLEAR_MASK ~BIT(16) 80 81 #define TSADCV2_DATA_MASK 0xfff 82 #define TSADCV3_DATA_MASK 0x3ff 83 84 #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4 85 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4 86 #define TSADCV2_AUTO_PERIOD_TIME 250 87 #define TSADCV2_AUTO_PERIOD_HT_TIME 50 88 #define TSADCV3_AUTO_PERIOD_TIME 1875 89 #define TSADCV3_AUTO_PERIOD_HT_TIME 1875 90 91 #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */ 92 93 #define GRF_SARADC_TESTBIT 0x0e644 94 #define GRF_TSADC_TESTBIT_L 0x0e648 95 #define GRF_TSADC_TESTBIT_H 0x0e64c 96 97 #define PX30_GRF_SOC_CON2 0x0408 98 99 #define GRF_SARADC_TESTBIT_ON (0x10001 << 2) 100 #define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2) 101 #define GRF_TSADC_VCM_EN_L (0x10001 << 7) 102 #define GRF_TSADC_VCM_EN_H (0x10001 << 7) 103 104 #define GRF_CON_TSADC_CH_INV (0x10001 << 1) 105 106 #define MIN_TEMP (-40000) 107 #define LOWEST_TEMP (-273000) 108 #define MAX_TEMP (125000) 109 #define MAX_ENV_TEMP (85000) 110 111 #define BASE (1024) 112 #define BASE_SHIFT (10) 113 #define START_DEBOUNCE_COUNT (100) 114 #define HIGHER_DEBOUNCE_TEMP (30000) 115 #define LOWER_DEBOUNCE_TEMP (15000) 116 117 /** 118 * struct tsadc_table - hold information about code and temp mapping 119 * @code: raw code from tsadc ip 120 * @temp: the mapping temperature 121 */ 122 123 struct tsadc_table { 124 unsigned long code; 125 int temp; 126 }; 127 128 struct chip_tsadc_table { 129 const struct tsadc_table *id; 130 unsigned int length; 131 u32 data_mask; 132 enum adc_sort_mode mode; 133 }; 134 135 enum sensor_id { 136 SENSOR_CPU = 0, 137 SENSOR_GPU, 138 }; 139 140 struct rockchip_tsadc_chip { 141 /* The sensor id of chip correspond to the ADC channel */ 142 int chn_id[SOC_MAX_SENSORS]; 143 int chn_num; 144 fdt_addr_t base; 145 fdt_addr_t grf; 146 147 /* The hardware-controlled tshut property */ 148 int tshut_temp; 149 enum tshut_mode tshut_mode; 150 enum tshut_polarity tshut_polarity; 151 152 void (*tsadc_control)(struct udevice *dev, bool enable); 153 void (*tsadc_init)(struct udevice *dev); 154 int (*tsadc_get_temp)(struct udevice *dev, int chn, 155 int *temp); 156 void (*irq_ack)(struct udevice *dev); 157 void (*set_alarm_temp)(struct udevice *dev, 158 int chn, int temp); 159 void (*set_tshut_temp)(struct udevice *dev, 160 int chn, int temp); 161 void (*set_tshut_mode)(struct udevice *dev, int chn, enum tshut_mode m); 162 struct chip_tsadc_table table; 163 }; 164 165 struct rockchip_thermal_priv { 166 void *base; 167 void *grf; 168 enum tshut_mode tshut_mode; 169 const struct rockchip_tsadc_chip *data; 170 }; 171 172 static const struct tsadc_table rk1808_code_table[] = { 173 {TSADCV2_DATA_MASK, -40000}, 174 {641, -40000}, 175 {633, -35000}, 176 {625, -30000}, 177 {617, -25000}, 178 {609, -20000}, 179 {601, -15000}, 180 {593, -10000}, 181 {585, -5000}, 182 {577, 0}, 183 {569, 5000}, 184 {561, 10000}, 185 {553, 15000}, 186 {545, 20000}, 187 {537, 25000}, 188 {529, 30000}, 189 {520, 35000}, 190 {512, 40000}, 191 {504, 45000}, 192 {496, 50000}, 193 {487, 55000}, 194 {479, 60000}, 195 {471, 65000}, 196 {463, 70000}, 197 {454, 75000}, 198 {446, 80000}, 199 {437, 85000}, 200 {429, 90000}, 201 {421, 95000}, 202 {412, 100000}, 203 {404, 105000}, 204 {395, 110000}, 205 {387, 115000}, 206 {378, 120000}, 207 {370, 125000}, 208 {0, 125000}, 209 }; 210 211 static const struct tsadc_table rk3228_code_table[] = { 212 {0, -40000}, 213 {588, -40000}, 214 {593, -35000}, 215 {598, -30000}, 216 {603, -25000}, 217 {608, -20000}, 218 {613, -15000}, 219 {618, -10000}, 220 {623, -5000}, 221 {629, 0}, 222 {634, 5000}, 223 {639, 10000}, 224 {644, 15000}, 225 {649, 20000}, 226 {654, 25000}, 227 {660, 30000}, 228 {665, 35000}, 229 {670, 40000}, 230 {675, 45000}, 231 {681, 50000}, 232 {686, 55000}, 233 {691, 60000}, 234 {696, 65000}, 235 {702, 70000}, 236 {707, 75000}, 237 {712, 80000}, 238 {717, 85000}, 239 {723, 90000}, 240 {728, 95000}, 241 {733, 100000}, 242 {738, 105000}, 243 {744, 110000}, 244 {749, 115000}, 245 {754, 120000}, 246 {760, 125000}, 247 {TSADCV2_DATA_MASK, 125000}, 248 }; 249 250 static const struct tsadc_table rk3288_code_table[] = { 251 {TSADCV2_DATA_MASK, -40000}, 252 {3800, -40000}, 253 {3792, -35000}, 254 {3783, -30000}, 255 {3774, -25000}, 256 {3765, -20000}, 257 {3756, -15000}, 258 {3747, -10000}, 259 {3737, -5000}, 260 {3728, 0}, 261 {3718, 5000}, 262 {3708, 10000}, 263 {3698, 15000}, 264 {3688, 20000}, 265 {3678, 25000}, 266 {3667, 30000}, 267 {3656, 35000}, 268 {3645, 40000}, 269 {3634, 45000}, 270 {3623, 50000}, 271 {3611, 55000}, 272 {3600, 60000}, 273 {3588, 65000}, 274 {3575, 70000}, 275 {3563, 75000}, 276 {3550, 80000}, 277 {3537, 85000}, 278 {3524, 90000}, 279 {3510, 95000}, 280 {3496, 100000}, 281 {3482, 105000}, 282 {3467, 110000}, 283 {3452, 115000}, 284 {3437, 120000}, 285 {3421, 125000}, 286 }; 287 288 static const struct tsadc_table rk3328_code_table[] = { 289 {0, -40000}, 290 {296, -40000}, 291 {304, -35000}, 292 {313, -30000}, 293 {331, -20000}, 294 {340, -15000}, 295 {349, -10000}, 296 {359, -5000}, 297 {368, 0}, 298 {378, 5000}, 299 {388, 10000}, 300 {398, 15000}, 301 {408, 20000}, 302 {418, 25000}, 303 {429, 30000}, 304 {440, 35000}, 305 {451, 40000}, 306 {462, 45000}, 307 {473, 50000}, 308 {485, 55000}, 309 {496, 60000}, 310 {508, 65000}, 311 {521, 70000}, 312 {533, 75000}, 313 {546, 80000}, 314 {559, 85000}, 315 {572, 90000}, 316 {586, 95000}, 317 {600, 100000}, 318 {614, 105000}, 319 {629, 110000}, 320 {644, 115000}, 321 {659, 120000}, 322 {675, 125000}, 323 {TSADCV2_DATA_MASK, 125000}, 324 }; 325 326 static const struct tsadc_table rk3368_code_table[] = { 327 {0, -40000}, 328 {106, -40000}, 329 {108, -35000}, 330 {110, -30000}, 331 {112, -25000}, 332 {114, -20000}, 333 {116, -15000}, 334 {118, -10000}, 335 {120, -5000}, 336 {122, 0}, 337 {124, 5000}, 338 {126, 10000}, 339 {128, 15000}, 340 {130, 20000}, 341 {132, 25000}, 342 {134, 30000}, 343 {136, 35000}, 344 {138, 40000}, 345 {140, 45000}, 346 {142, 50000}, 347 {144, 55000}, 348 {146, 60000}, 349 {148, 65000}, 350 {150, 70000}, 351 {152, 75000}, 352 {154, 80000}, 353 {156, 85000}, 354 {158, 90000}, 355 {160, 95000}, 356 {162, 100000}, 357 {163, 105000}, 358 {165, 110000}, 359 {167, 115000}, 360 {169, 120000}, 361 {171, 125000}, 362 {TSADCV3_DATA_MASK, 125000}, 363 }; 364 365 static const struct tsadc_table rk3399_code_table[] = { 366 {0, -40000}, 367 {402, -40000}, 368 {410, -35000}, 369 {419, -30000}, 370 {427, -25000}, 371 {436, -20000}, 372 {444, -15000}, 373 {453, -10000}, 374 {461, -5000}, 375 {470, 0}, 376 {478, 5000}, 377 {487, 10000}, 378 {496, 15000}, 379 {504, 20000}, 380 {513, 25000}, 381 {521, 30000}, 382 {530, 35000}, 383 {538, 40000}, 384 {547, 45000}, 385 {555, 50000}, 386 {564, 55000}, 387 {573, 60000}, 388 {581, 65000}, 389 {590, 70000}, 390 {599, 75000}, 391 {607, 80000}, 392 {616, 85000}, 393 {624, 90000}, 394 {633, 95000}, 395 {642, 100000}, 396 {650, 105000}, 397 {659, 110000}, 398 {668, 115000}, 399 {677, 120000}, 400 {685, 125000}, 401 {TSADCV3_DATA_MASK, 125000}, 402 }; 403 404 /* 405 * Struct used for matching a device 406 */ 407 struct of_device_id { 408 char compatible[32]; 409 const void *data; 410 }; 411 412 static int tsadc_code_to_temp(struct chip_tsadc_table *table, u32 code, 413 int *temp) 414 { 415 unsigned int low = 1; 416 unsigned int high = table->length - 1; 417 unsigned int mid = (low + high) / 2; 418 unsigned int num; 419 unsigned long denom; 420 421 switch (table->mode) { 422 case ADC_DECREMENT: 423 code &= table->data_mask; 424 if (code < table->id[high].code) 425 return -EAGAIN; /* Incorrect reading */ 426 427 while (low <= high) { 428 if (code >= table->id[mid].code && 429 code < table->id[mid - 1].code) 430 break; 431 else if (code < table->id[mid].code) 432 low = mid + 1; 433 else 434 high = mid - 1; 435 436 mid = (low + high) / 2; 437 } 438 break; 439 case ADC_INCREMENT: 440 code &= table->data_mask; 441 if (code < table->id[low].code) 442 return -EAGAIN; /* Incorrect reading */ 443 444 while (low <= high) { 445 if (code <= table->id[mid].code && 446 code > table->id[mid - 1].code) 447 break; 448 else if (code > table->id[mid].code) 449 low = mid + 1; 450 else 451 high = mid - 1; 452 453 mid = (low + high) / 2; 454 } 455 break; 456 default: 457 printf("%s: Invalid the conversion table mode=%d\n", 458 __func__, table->mode); 459 return -EINVAL; 460 } 461 462 /* 463 * The 5C granularity provided by the table is too much. Let's 464 * assume that the relationship between sensor readings and 465 * temperature between 2 table entries is linear and interpolate 466 * to produce less granular result. 467 */ 468 num = table->id[mid].temp - table->id[mid - 1].temp; 469 num *= abs(table->id[mid - 1].code - code); 470 denom = abs(table->id[mid - 1].code - table->id[mid].code); 471 *temp = table->id[mid - 1].temp + (num / denom); 472 473 return 0; 474 } 475 476 static u32 tsadc_temp_to_code_v2(struct chip_tsadc_table table, 477 int temp) 478 { 479 int high, low, mid; 480 u32 error = table.data_mask; 481 482 low = 0; 483 high = table.length - 1; 484 mid = (high + low) / 2; 485 486 /* Return mask code data when the temp is over table range */ 487 if (temp < table.id[low].temp || temp > table.id[high].temp) 488 goto exit; 489 490 while (low <= high) { 491 if (temp == table.id[mid].temp) 492 return table.id[mid].code; 493 else if (temp < table.id[mid].temp) 494 high = mid - 1; 495 else 496 low = mid + 1; 497 mid = (low + high) / 2; 498 } 499 500 exit: 501 pr_err("%s: Invalid conversion table: code=%d, temperature=%d\n", 502 __func__, error, temp); 503 504 return error; 505 } 506 507 static void tsadc_irq_ack_v2(struct udevice *dev) 508 { 509 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 510 u32 val; 511 512 val = readl(priv->base + TSADCV2_INT_PD); 513 writel(val & TSADCV2_INT_PD_CLEAR_MASK, priv->base + TSADCV2_INT_PD); 514 } 515 516 static void tsadc_irq_ack_v3(struct udevice *dev) 517 { 518 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 519 u32 val; 520 521 val = readl(priv->base + TSADCV2_INT_PD); 522 writel(val & TSADCV3_INT_PD_CLEAR_MASK, priv->base + TSADCV2_INT_PD); 523 } 524 525 static void tsadc_control_v3(struct udevice *dev, bool enable) 526 { 527 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 528 u32 val; 529 530 val = readl(priv->base + TSADCV2_AUTO_CON); 531 if (enable) 532 val |= TSADCV2_AUTO_EN | TSADCV3_AUTO_Q_SEL_EN; 533 else 534 val &= ~TSADCV2_AUTO_EN; 535 536 writel(val, priv->base + TSADCV2_AUTO_CON); 537 } 538 539 static void tsadc_control_v2(struct udevice *dev, bool enable) 540 { 541 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 542 u32 val; 543 544 val = readl(priv->base + TSADCV2_AUTO_CON); 545 if (enable) 546 val |= TSADCV2_AUTO_EN; 547 else 548 val &= ~TSADCV2_AUTO_EN; 549 550 writel(val, priv->base + TSADCV2_AUTO_CON); 551 } 552 553 static void tsadc_init_v2(struct udevice *dev) 554 { 555 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 556 557 writel(TSADCV2_AUTO_PERIOD_TIME, 558 priv->base + TSADCV2_AUTO_PERIOD); 559 writel(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, 560 priv->base + TSADCV2_HIGHT_INT_DEBOUNCE); 561 writel(TSADCV2_AUTO_PERIOD_HT_TIME, 562 priv->base + TSADCV2_AUTO_PERIOD_HT); 563 writel(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, 564 priv->base + TSADCV2_HIGHT_TSHUT_DEBOUNCE); 565 566 if (priv->data->tshut_polarity == TSHUT_HIGH_ACTIVE) 567 writel(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 568 priv->base + TSADCV2_AUTO_CON); 569 else 570 writel(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 571 priv->base + TSADCV2_AUTO_CON); 572 } 573 574 static void tsadc_init_v3(struct udevice *dev) 575 { 576 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 577 578 if (!IS_ERR(priv->grf)) { 579 writel(GRF_TSADC_VCM_EN_L, priv->grf + GRF_TSADC_TESTBIT_L); 580 writel(GRF_TSADC_VCM_EN_H, priv->grf + GRF_TSADC_TESTBIT_H); 581 582 udelay(100);/* The spec note says at least 15 us */ 583 writel(GRF_SARADC_TESTBIT_ON, priv->grf + GRF_SARADC_TESTBIT); 584 writel(GRF_TSADC_TESTBIT_H_ON, priv->grf + GRF_TSADC_TESTBIT_H); 585 udelay(200);/* The spec note says at least 90 us */ 586 } 587 tsadc_init_v2(dev); 588 } 589 590 static void __maybe_unused tsadc_init_v5(struct udevice *dev) 591 { 592 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 593 594 /* Set interleave value to workround ic time sync issue */ 595 writel(TSADCV2_USER_INTER_PD_SOC, priv->base + 596 TSADCV2_USER_CON); 597 tsadc_init_v2(dev); 598 } 599 600 static void tsadc_init_v4(struct udevice *dev) 601 { 602 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 603 604 tsadc_init_v2(dev); 605 if (!IS_ERR(priv->grf)) 606 writel(GRF_CON_TSADC_CH_INV, priv->grf + PX30_GRF_SOC_CON2); 607 } 608 609 static int tsadc_get_temp_v2(struct udevice *dev, 610 int chn, int *temp) 611 { 612 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 613 struct chip_tsadc_table table = priv->data->table; 614 u32 val; 615 616 val = readl(priv->base + TSADCV2_DATA(chn)); 617 618 return tsadc_code_to_temp(&table, val, temp); 619 } 620 621 static int predict_temp(int temp) 622 { 623 /* 624 * The deviation of prediction. the temperature will not change rapidly, 625 * so this cov_q is small 626 */ 627 int cov_q = 18; 628 /* 629 * The deviation of tsadc's reading, deviation of tsadc is very big when 630 * abnormal temperature is get 631 */ 632 int cov_r = 542; 633 634 int gain; 635 int temp_mid; 636 int temp_now; 637 int prob_mid; 638 int prob_now; 639 static int temp_last = LOWEST_TEMP; 640 static int prob_last = 160; 641 static int bounding_cnt; 642 643 /* 644 * init temp_last with a more suitable value, which mostly equals to 645 * temp reading from tsadc, but not higher than MAX_ENV_TEMP. If the 646 * temp is higher than MAX_ENV_TEMP, it is assumed to be abnormal 647 * value and temp_last is adjusted to MAX_ENV_TEMP. 648 */ 649 if (temp_last == LOWEST_TEMP) 650 temp_last = min(temp, MAX_ENV_TEMP); 651 652 /* 653 * Before START_DEBOUNCE_COUNT's samples of temperature, we consider 654 * tsadc is stable, i.e. after that, the temperature may be not stable 655 * and may have abnormal reading, so we set a bounding temperature. If 656 * the reading from tsadc is too big, we set the delta temperature of 657 * DEBOUNCE_TEMP/3 comparing to the last temperature. 658 */ 659 660 if (bounding_cnt++ > START_DEBOUNCE_COUNT) { 661 bounding_cnt = START_DEBOUNCE_COUNT; 662 if (temp - temp_last > HIGHER_DEBOUNCE_TEMP) 663 temp = temp_last + HIGHER_DEBOUNCE_TEMP / 3; 664 if (temp_last - temp > LOWER_DEBOUNCE_TEMP) 665 temp = temp_last - LOWER_DEBOUNCE_TEMP / 3; 666 } 667 668 temp_mid = temp_last; 669 670 /* calculate the probability of this time's prediction */ 671 prob_mid = prob_last + cov_q; 672 673 /* calculate the Kalman Gain */ 674 gain = (prob_mid * BASE) / (prob_mid + cov_r); 675 676 /* calculate the prediction of temperature */ 677 temp_now = (temp_mid * BASE + gain * (temp - temp_mid)) >> BASE_SHIFT; 678 679 /* 680 * Base on this time's Kalman Gain, ajust our probability of prediction 681 * for next time calculation 682 */ 683 prob_now = ((BASE - gain) * prob_mid) >> BASE_SHIFT; 684 685 prob_last = prob_now; 686 temp_last = temp_now; 687 688 return temp_last; 689 } 690 691 static int tsadc_get_temp_v3(struct udevice *dev, 692 int chn, int *temp) 693 { 694 int ret; 695 696 ret = tsadc_get_temp_v2(dev, chn, temp); 697 if (!ret) 698 *temp = predict_temp(*temp); 699 700 return ret; 701 } 702 703 static void tsadc_alarm_temp_v2(struct udevice *dev, 704 int chn, int temp) 705 { 706 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 707 struct chip_tsadc_table table = priv->data->table; 708 u32 alarm_value, int_en; 709 710 alarm_value = tsadc_temp_to_code_v2(table, temp); 711 if (alarm_value == table.data_mask) 712 return; 713 714 writel(alarm_value, priv->base + TSADCV2_COMP_INT(chn)); 715 716 int_en = readl(priv->base + TSADCV2_INT_EN); 717 int_en |= TSADCV2_INT_SRC_EN(chn); 718 writel(int_en, priv->base + TSADCV2_INT_EN); 719 } 720 721 static void tsadc_tshut_temp_v2(struct udevice *dev, 722 int chn, int temp) 723 { 724 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 725 struct chip_tsadc_table table = priv->data->table; 726 u32 tshut_value, val; 727 728 tshut_value = tsadc_temp_to_code_v2(table, temp); 729 if (tshut_value == table.data_mask) 730 return; 731 732 writel(tshut_value, priv->base + TSADCV2_COMP_SHUT(chn)); 733 734 /* TSHUT will be valid */ 735 val = readl(priv->base + TSADCV2_AUTO_CON); 736 writel(val | TSADCV2_AUTO_SRC_EN(chn), priv->base + TSADCV2_AUTO_CON); 737 } 738 739 static void tsadc_tshut_mode_v2(struct udevice *dev, int chn, 740 enum tshut_mode mode) 741 { 742 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 743 u32 val; 744 745 val = readl(priv->base + TSADCV2_INT_EN); 746 if (mode == TSHUT_MODE_GPIO) { 747 val &= ~TSADCV2_SHUT_2CRU_SRC_EN(chn); 748 val |= TSADCV2_SHUT_2GPIO_SRC_EN(chn); 749 } else { 750 val &= ~TSADCV2_SHUT_2GPIO_SRC_EN(chn); 751 val |= TSADCV2_SHUT_2CRU_SRC_EN(chn); 752 } 753 754 writel(val, priv->base + TSADCV2_INT_EN); 755 } 756 757 int rockchip_thermal_get_temp(struct udevice *dev, int *temp) 758 { 759 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 760 761 priv->data->tsadc_get_temp(dev, 0, temp); 762 763 return 0; 764 } 765 766 static const struct dm_thermal_ops rockchip_thermal_ops = { 767 .get_temp = rockchip_thermal_get_temp, 768 }; 769 770 static int rockchip_thermal_probe(struct udevice *dev) 771 { 772 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 773 struct rockchip_tsadc_chip *tsadc; 774 int ret, i, shut_temp; 775 776 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 777 ret = clk_set_defaults(dev); 778 if (ret) 779 printf("%s clk_set_defaults failed %d\n", __func__, ret); 780 781 tsadc = (struct rockchip_tsadc_chip *)dev_get_driver_data(dev); 782 priv->data = tsadc; 783 784 priv->tshut_mode = dev_read_u32_default(dev, 785 "rockchip,hw-tshut-mode", 786 -1); 787 if (priv->tshut_mode < 0) 788 priv->tshut_mode = priv->data->tshut_mode; 789 790 if (priv->tshut_mode == TSHUT_MODE_GPIO) 791 pinctrl_select_state(dev, "otpout"); 792 else 793 pinctrl_select_state(dev, "gpio"); 794 795 tsadc->tsadc_init(dev); 796 tsadc->irq_ack(dev); 797 798 shut_temp = dev_read_u32_default(dev, "rockchip,hw-tshut-temp", -1); 799 if (shut_temp < 0) 800 shut_temp = 120000; 801 802 for (i = 0; i < tsadc->chn_num; i++) { 803 tsadc->set_alarm_temp(dev, i, tsadc->tshut_temp); 804 tsadc->set_tshut_temp(dev, i, shut_temp); 805 if (priv->tshut_mode == TSHUT_MODE_GPIO) 806 tsadc->set_tshut_mode(dev, i, TSHUT_MODE_GPIO); 807 else 808 tsadc->set_tshut_mode(dev, i, TSHUT_MODE_CRU); 809 } 810 811 tsadc->tsadc_control(dev, true); 812 udelay(1000); 813 814 debug("tsadc probed successfully\n"); 815 816 return 0; 817 } 818 819 static int rockchip_thermal_ofdata_to_platdata(struct udevice *dev) 820 { 821 struct rockchip_thermal_priv *priv = dev_get_priv(dev); 822 823 priv->base = dev_read_addr_ptr(dev); 824 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 825 826 return 0; 827 } 828 829 static const struct rockchip_tsadc_chip rk1808_tsadc_data = { 830 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 831 .chn_num = 1, /* one channel for tsadc */ 832 833 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 834 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 835 .tshut_temp = 95000, 836 837 .tsadc_init = tsadc_init_v2, 838 .tsadc_control = tsadc_control_v3, 839 .tsadc_get_temp = tsadc_get_temp_v2, 840 .irq_ack = tsadc_irq_ack_v3, 841 .set_alarm_temp = tsadc_alarm_temp_v2, 842 .set_tshut_temp = tsadc_tshut_temp_v2, 843 .set_tshut_mode = tsadc_tshut_mode_v2, 844 845 .table = { 846 .id = rk1808_code_table, 847 .length = ARRAY_SIZE(rk1808_code_table), 848 .data_mask = TSADCV2_DATA_MASK, 849 .mode = ADC_DECREMENT, 850 }, 851 }; 852 853 static const struct rockchip_tsadc_chip rk3228_tsadc_data = { 854 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 855 .chn_num = 1, /* one channel for tsadc */ 856 857 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 858 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 859 .tshut_temp = 95000, 860 861 .tsadc_init = tsadc_init_v2, 862 .tsadc_control = tsadc_control_v3, 863 .tsadc_get_temp = tsadc_get_temp_v2, 864 .irq_ack = tsadc_irq_ack_v3, 865 .set_alarm_temp = tsadc_alarm_temp_v2, 866 .set_tshut_temp = tsadc_tshut_temp_v2, 867 .set_tshut_mode = tsadc_tshut_mode_v2, 868 869 .table = { 870 .id = rk3228_code_table, 871 .length = ARRAY_SIZE(rk3228_code_table), 872 .data_mask = TSADCV3_DATA_MASK, 873 .mode = ADC_INCREMENT, 874 }, 875 }; 876 877 static const struct rockchip_tsadc_chip rk3288_tsadc_data = { 878 .chn_id[SENSOR_CPU] = 1, /* cpu sensor is channel 1 */ 879 .chn_id[SENSOR_GPU] = 2, /* gpu sensor is channel 2 */ 880 .chn_num = 2, /* two channels for tsadc */ 881 882 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 883 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 884 .tshut_temp = 95000, 885 886 .tsadc_init = tsadc_init_v2, 887 .tsadc_control = tsadc_control_v2, 888 .tsadc_get_temp = tsadc_get_temp_v3, 889 .irq_ack = tsadc_irq_ack_v2, 890 .set_alarm_temp = tsadc_alarm_temp_v2, 891 .set_tshut_temp = tsadc_tshut_temp_v2, 892 .set_tshut_mode = tsadc_tshut_mode_v2, 893 894 .table = { 895 .id = rk3288_code_table, 896 .length = ARRAY_SIZE(rk3288_code_table), 897 .data_mask = TSADCV2_DATA_MASK, 898 .mode = ADC_DECREMENT, 899 }, 900 }; 901 902 static const struct rockchip_tsadc_chip rk3308_tsadc_data = { 903 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 904 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 905 .chn_num = 2, /* 2 channels for tsadc */ 906 907 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ 908 .tshut_temp = 95000, 909 910 .tsadc_init = tsadc_init_v4, 911 .tsadc_control = tsadc_control_v3, 912 .tsadc_get_temp = tsadc_get_temp_v2, 913 .irq_ack = tsadc_irq_ack_v3, 914 .set_alarm_temp = tsadc_alarm_temp_v2, 915 .set_tshut_temp = tsadc_tshut_temp_v2, 916 .set_tshut_mode = tsadc_tshut_mode_v2, 917 918 .table = { 919 .id = rk3328_code_table, 920 .length = ARRAY_SIZE(rk3328_code_table), 921 .data_mask = TSADCV2_DATA_MASK, 922 .mode = ADC_INCREMENT, 923 }, 924 }; 925 926 static const struct rockchip_tsadc_chip px30_tsadc_data = { 927 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 928 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 929 .chn_num = 2, /* 2 channels for tsadc */ 930 931 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ 932 .tshut_temp = 95000, 933 934 .tsadc_init = tsadc_init_v4, 935 .tsadc_control = tsadc_control_v3, 936 .tsadc_get_temp = tsadc_get_temp_v2, 937 .irq_ack = tsadc_irq_ack_v3, 938 .set_alarm_temp = tsadc_alarm_temp_v2, 939 .set_tshut_temp = tsadc_tshut_temp_v2, 940 .set_tshut_mode = tsadc_tshut_mode_v2, 941 942 .table = { 943 .id = rk3328_code_table, 944 .length = ARRAY_SIZE(rk3328_code_table), 945 .data_mask = TSADCV2_DATA_MASK, 946 .mode = ADC_INCREMENT, 947 }, 948 }; 949 950 static const struct rockchip_tsadc_chip rk3328_tsadc_data = { 951 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 952 .chn_num = 1, /* one channels for tsadc */ 953 954 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ 955 .tshut_temp = 95000, 956 957 .tsadc_init = tsadc_init_v2, 958 .tsadc_control = tsadc_control_v3, 959 .tsadc_get_temp = tsadc_get_temp_v2, 960 .irq_ack = tsadc_irq_ack_v3, 961 .set_alarm_temp = tsadc_alarm_temp_v2, 962 .set_tshut_temp = tsadc_tshut_temp_v2, 963 .set_tshut_mode = tsadc_tshut_mode_v2, 964 965 .table = { 966 .id = rk3328_code_table, 967 .length = ARRAY_SIZE(rk3328_code_table), 968 .data_mask = TSADCV2_DATA_MASK, 969 .mode = ADC_INCREMENT, 970 }, 971 }; 972 973 static const struct rockchip_tsadc_chip rk3366_tsadc_data = { 974 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 975 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 976 .chn_num = 2, /* two channels for tsadc */ 977 978 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 979 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 980 .tshut_temp = 95000, 981 982 .tsadc_init = tsadc_init_v3, 983 .tsadc_control = tsadc_control_v3, 984 .tsadc_get_temp = tsadc_get_temp_v2, 985 .irq_ack = tsadc_irq_ack_v3, 986 .set_alarm_temp = tsadc_alarm_temp_v2, 987 .set_tshut_temp = tsadc_tshut_temp_v2, 988 .set_tshut_mode = tsadc_tshut_mode_v2, 989 990 .table = { 991 .id = rk3228_code_table, 992 .length = ARRAY_SIZE(rk3228_code_table), 993 .data_mask = TSADCV3_DATA_MASK, 994 .mode = ADC_INCREMENT, 995 }, 996 }; 997 998 static const struct rockchip_tsadc_chip rk3368_tsadc_data = { 999 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1000 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1001 .chn_num = 2, /* two channels for tsadc */ 1002 1003 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1004 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1005 .tshut_temp = 95000, 1006 1007 .tsadc_init = tsadc_init_v2, 1008 .tsadc_control = tsadc_control_v2, 1009 .tsadc_get_temp = tsadc_get_temp_v2, 1010 .irq_ack = tsadc_irq_ack_v2, 1011 .set_alarm_temp = tsadc_alarm_temp_v2, 1012 .set_tshut_temp = tsadc_tshut_temp_v2, 1013 .set_tshut_mode = tsadc_tshut_mode_v2, 1014 1015 .table = { 1016 .id = rk3368_code_table, 1017 .length = ARRAY_SIZE(rk3368_code_table), 1018 .data_mask = TSADCV3_DATA_MASK, 1019 .mode = ADC_INCREMENT, 1020 }, 1021 }; 1022 1023 static const struct rockchip_tsadc_chip rk3399_tsadc_data = { 1024 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1025 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1026 .chn_num = 2, /* two channels for tsadc */ 1027 1028 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1029 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1030 .tshut_temp = 95000, 1031 1032 .tsadc_init = tsadc_init_v3, 1033 .tsadc_control = tsadc_control_v3, 1034 .tsadc_get_temp = tsadc_get_temp_v2, 1035 .irq_ack = tsadc_irq_ack_v3, 1036 .set_alarm_temp = tsadc_alarm_temp_v2, 1037 .set_tshut_temp = tsadc_tshut_temp_v2, 1038 .set_tshut_mode = tsadc_tshut_mode_v2, 1039 1040 .table = { 1041 .id = rk3399_code_table, 1042 .length = ARRAY_SIZE(rk3399_code_table), 1043 .data_mask = TSADCV3_DATA_MASK, 1044 .mode = ADC_INCREMENT, 1045 }, 1046 }; 1047 1048 static const struct udevice_id rockchip_thermal_match[] = { 1049 { 1050 .compatible = "rockchip,px30-tsadc", 1051 .data = (ulong)&px30_tsadc_data, 1052 }, 1053 { 1054 .compatible = "rockchip,rk1808-tsadc", 1055 .data = (ulong)&rk1808_tsadc_data, 1056 }, 1057 { 1058 .compatible = "rockchip,rk3228-tsadc", 1059 .data = (ulong)&rk3228_tsadc_data, 1060 }, 1061 { 1062 .compatible = "rockchip,rk3288-tsadc", 1063 .data = (ulong)&rk3288_tsadc_data, 1064 }, 1065 { 1066 .compatible = "rockchip,rk3308-tsadc", 1067 .data = (ulong)&rk3308_tsadc_data, 1068 }, 1069 { 1070 .compatible = "rockchip,rk3328-tsadc", 1071 .data = (ulong)&rk3328_tsadc_data, 1072 }, 1073 { 1074 .compatible = "rockchip,rk3366-tsadc", 1075 .data = (ulong)&rk3366_tsadc_data, 1076 }, 1077 { 1078 .compatible = "rockchip,rk3368-tsadc", 1079 .data = (ulong)&rk3368_tsadc_data, 1080 }, 1081 { 1082 .compatible = "rockchip,rk3399-tsadc", 1083 .data = (ulong)&rk3399_tsadc_data, 1084 }, 1085 { /* end */ }, 1086 }; 1087 1088 U_BOOT_DRIVER(rockchip_thermal) = { 1089 .name = "rockchip_thermal", 1090 .id = UCLASS_THERMAL, 1091 .of_match = rockchip_thermal_match, 1092 .priv_auto_alloc_size = sizeof(struct rockchip_thermal_priv), 1093 .ofdata_to_platdata = rockchip_thermal_ofdata_to_platdata, 1094 .ops = &rockchip_thermal_ops, 1095 .probe = rockchip_thermal_probe, 1096 }; 1097