1 /* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <errno.h> 10 #include <sysreset.h> 11 #include <asm/io.h> 12 #include <asm/arch/clock.h> 13 #include <asm/arch/cru_rk3328.h> 14 #include <asm/arch/hardware.h> 15 #include <linux/err.h> 16 17 int rockchip_sysreset_request(struct udevice *dev, enum sysreset_t type) 18 { 19 struct sysreset_reg *offset = dev_get_priv(dev); 20 unsigned long cru_base = (unsigned long)rockchip_get_cru(); 21 22 if (IS_ERR_VALUE(cru_base)) 23 return (int)cru_base; 24 25 switch (type) { 26 case SYSRESET_WARM: 27 #ifdef CONFIG_ARM64 28 /* Rockchip 64bit SOC need fst reset for cpu reset entry */ 29 writel(0xfdb9, cru_base + offset->glb_srst_fst_value); 30 #else 31 writel(0xeca8, cru_base + offset->glb_srst_snd_value); 32 #endif 33 break; 34 case SYSRESET_COLD: 35 writel(0xfdb9, cru_base + offset->glb_srst_fst_value); 36 break; 37 default: 38 return -EPROTONOSUPPORT; 39 } 40 41 return -EINPROGRESS; 42 } 43 44 static struct sysreset_ops rockchip_sysreset = { 45 .request = rockchip_sysreset_request, 46 }; 47 48 U_BOOT_DRIVER(sysreset_rockchip) = { 49 .name = "rockchip_sysreset", 50 .id = UCLASS_SYSRESET, 51 .ops = &rockchip_sysreset, 52 }; 53