1 /* 2 * NVIDIA Tegra SPI-SLINK controller 3 * 4 * Copyright (c) 2010-2013 NVIDIA Corporation 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This software is licensed under the terms of the GNU General Public 10 * License version 2, as published by the Free Software Foundation, and 11 * may be copied, distributed, and modified under those terms. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <malloc.h> 26 #include <asm/io.h> 27 #include <asm/gpio.h> 28 #include <asm/arch/clock.h> 29 #include <asm/arch-tegra/clk_rst.h> 30 #include <asm/arch-tegra20/tegra20_slink.h> 31 #include <spi.h> 32 #include <fdtdec.h> 33 34 DECLARE_GLOBAL_DATA_PTR; 35 36 /* COMMAND */ 37 #define SLINK_CMD_ENB (1 << 31) 38 #define SLINK_CMD_GO (1 << 30) 39 #define SLINK_CMD_M_S (1 << 28) 40 #define SLINK_CMD_CK_SDA (1 << 21) 41 #define SLINK_CMD_CS_POL (1 << 13) 42 #define SLINK_CMD_CS_VAL (1 << 12) 43 #define SLINK_CMD_CS_SOFT (1 << 11) 44 #define SLINK_CMD_BIT_LENGTH (1 << 4) 45 #define SLINK_CMD_BIT_LENGTH_MASK 0x0000001F 46 /* COMMAND2 */ 47 #define SLINK_CMD2_TXEN (1 << 30) 48 #define SLINK_CMD2_RXEN (1 << 31) 49 #define SLINK_CMD2_SS_EN (1 << 18) 50 #define SLINK_CMD2_SS_EN_SHIFT 18 51 #define SLINK_CMD2_SS_EN_MASK 0x000C0000 52 #define SLINK_CMD2_CS_ACTIVE_BETWEEN (1 << 17) 53 /* STATUS */ 54 #define SLINK_STAT_BSY (1 << 31) 55 #define SLINK_STAT_RDY (1 << 30) 56 #define SLINK_STAT_ERR (1 << 29) 57 #define SLINK_STAT_RXF_FLUSH (1 << 27) 58 #define SLINK_STAT_TXF_FLUSH (1 << 26) 59 #define SLINK_STAT_RXF_OVF (1 << 25) 60 #define SLINK_STAT_TXF_UNR (1 << 24) 61 #define SLINK_STAT_RXF_EMPTY (1 << 23) 62 #define SLINK_STAT_RXF_FULL (1 << 22) 63 #define SLINK_STAT_TXF_EMPTY (1 << 21) 64 #define SLINK_STAT_TXF_FULL (1 << 20) 65 #define SLINK_STAT_TXF_OVF (1 << 19) 66 #define SLINK_STAT_RXF_UNR (1 << 18) 67 #define SLINK_STAT_CUR_BLKCNT (1 << 15) 68 /* STATUS2 */ 69 #define SLINK_STAT2_RXF_FULL_CNT (1 << 16) 70 #define SLINK_STAT2_TXF_FULL_CNT (1 << 0) 71 72 #define SPI_TIMEOUT 1000 73 #define TEGRA_SPI_MAX_FREQ 52000000 74 75 struct spi_regs { 76 u32 command; /* SLINK_COMMAND_0 register */ 77 u32 command2; /* SLINK_COMMAND2_0 reg */ 78 u32 status; /* SLINK_STATUS_0 register */ 79 u32 reserved; /* Reserved offset 0C */ 80 u32 mas_data; /* SLINK_MAS_DATA_0 reg */ 81 u32 slav_data; /* SLINK_SLAVE_DATA_0 reg */ 82 u32 dma_ctl; /* SLINK_DMA_CTL_0 register */ 83 u32 status2; /* SLINK_STATUS2_0 reg */ 84 u32 rsvd[56]; /* 0x20 to 0xFF reserved */ 85 u32 tx_fifo; /* SLINK_TX_FIFO_0 reg off 100h */ 86 u32 rsvd2[31]; /* 0x104 to 0x17F reserved */ 87 u32 rx_fifo; /* SLINK_RX_FIFO_0 reg off 180h */ 88 }; 89 90 struct tegra_spi_ctrl { 91 struct spi_regs *regs; 92 unsigned int freq; 93 unsigned int mode; 94 int periph_id; 95 int valid; 96 }; 97 98 struct tegra_spi_slave { 99 struct spi_slave slave; 100 struct tegra_spi_ctrl *ctrl; 101 }; 102 103 static struct tegra_spi_ctrl spi_ctrls[CONFIG_TEGRA_SLINK_CTRLS]; 104 105 static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave) 106 { 107 return container_of(slave, struct tegra_spi_slave, slave); 108 } 109 110 int tegra30_spi_cs_is_valid(unsigned int bus, unsigned int cs) 111 { 112 if (bus >= CONFIG_TEGRA_SLINK_CTRLS || cs > 3 || !spi_ctrls[bus].valid) 113 return 0; 114 else 115 return 1; 116 } 117 118 struct spi_slave *tegra30_spi_setup_slave(unsigned int bus, unsigned int cs, 119 unsigned int max_hz, unsigned int mode) 120 { 121 struct tegra_spi_slave *spi; 122 123 debug("%s: bus: %u, cs: %u, max_hz: %u, mode: %u\n", __func__, 124 bus, cs, max_hz, mode); 125 126 if (!spi_cs_is_valid(bus, cs)) { 127 printf("SPI error: unsupported bus %d / chip select %d\n", 128 bus, cs); 129 return NULL; 130 } 131 132 if (max_hz > TEGRA_SPI_MAX_FREQ) { 133 printf("SPI error: unsupported frequency %d Hz. Max frequency" 134 " is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ); 135 return NULL; 136 } 137 138 spi = malloc(sizeof(struct tegra_spi_slave)); 139 if (!spi) { 140 printf("SPI error: malloc of SPI structure failed\n"); 141 return NULL; 142 } 143 spi->slave.bus = bus; 144 spi->slave.cs = cs; 145 spi->ctrl = &spi_ctrls[bus]; 146 if (!spi->ctrl) { 147 printf("SPI error: could not find controller for bus %d\n", 148 bus); 149 return NULL; 150 } 151 152 if (max_hz < spi->ctrl->freq) { 153 debug("%s: limiting frequency from %u to %u\n", __func__, 154 spi->ctrl->freq, max_hz); 155 spi->ctrl->freq = max_hz; 156 } 157 spi->ctrl->mode = mode; 158 159 return &spi->slave; 160 } 161 162 void tegra30_spi_free_slave(struct spi_slave *slave) 163 { 164 struct tegra_spi_slave *spi = to_tegra_spi(slave); 165 166 free(spi); 167 } 168 169 int tegra30_spi_init(int *node_list, int count) 170 { 171 struct tegra_spi_ctrl *ctrl; 172 int i; 173 int node = 0; 174 int found = 0; 175 176 for (i = 0; i < count; i++) { 177 ctrl = &spi_ctrls[i]; 178 node = node_list[i]; 179 180 ctrl->regs = (struct spi_regs *)fdtdec_get_addr(gd->fdt_blob, 181 node, "reg"); 182 if ((fdt_addr_t)ctrl->regs == FDT_ADDR_T_NONE) { 183 debug("%s: no slink register found\n", __func__); 184 continue; 185 } 186 ctrl->freq = fdtdec_get_int(gd->fdt_blob, node, 187 "spi-max-frequency", 0); 188 if (!ctrl->freq) { 189 debug("%s: no slink max frequency found\n", __func__); 190 continue; 191 } 192 193 ctrl->periph_id = clock_decode_periph_id(gd->fdt_blob, node); 194 if (ctrl->periph_id == PERIPH_ID_NONE) { 195 debug("%s: could not decode periph id\n", __func__); 196 continue; 197 } 198 ctrl->valid = 1; 199 found = 1; 200 201 debug("%s: found controller at %p, freq = %u, periph_id = %d\n", 202 __func__, ctrl->regs, ctrl->freq, ctrl->periph_id); 203 } 204 return !found; 205 } 206 207 int tegra30_spi_claim_bus(struct spi_slave *slave) 208 { 209 struct tegra_spi_slave *spi = to_tegra_spi(slave); 210 struct spi_regs *regs = spi->ctrl->regs; 211 u32 reg; 212 213 /* Change SPI clock to correct frequency, PLLP_OUT0 source */ 214 clock_start_periph_pll(spi->ctrl->periph_id, CLOCK_ID_PERIPH, 215 spi->ctrl->freq); 216 217 /* Clear stale status here */ 218 reg = SLINK_STAT_RDY | SLINK_STAT_RXF_FLUSH | SLINK_STAT_TXF_FLUSH | \ 219 SLINK_STAT_RXF_UNR | SLINK_STAT_TXF_OVF; 220 writel(reg, ®s->status); 221 debug("%s: STATUS = %08x\n", __func__, readl(®s->status)); 222 223 /* Set master mode and sw controlled CS */ 224 reg = readl(®s->command); 225 reg |= SLINK_CMD_M_S | SLINK_CMD_CS_SOFT; 226 writel(reg, ®s->command); 227 debug("%s: COMMAND = %08x\n", __func__, readl(®s->command)); 228 229 return 0; 230 } 231 232 void tegra30_spi_cs_activate(struct spi_slave *slave) 233 { 234 struct tegra_spi_slave *spi = to_tegra_spi(slave); 235 struct spi_regs *regs = spi->ctrl->regs; 236 237 /* CS is negated on Tegra, so drive a 1 to get a 0 */ 238 setbits_le32(®s->command, SLINK_CMD_CS_VAL); 239 } 240 241 void tegra30_spi_cs_deactivate(struct spi_slave *slave) 242 { 243 struct tegra_spi_slave *spi = to_tegra_spi(slave); 244 struct spi_regs *regs = spi->ctrl->regs; 245 246 /* CS is negated on Tegra, so drive a 0 to get a 1 */ 247 clrbits_le32(®s->command, SLINK_CMD_CS_VAL); 248 } 249 250 int tegra30_spi_xfer(struct spi_slave *slave, unsigned int bitlen, 251 const void *data_out, void *data_in, unsigned long flags) 252 { 253 struct tegra_spi_slave *spi = to_tegra_spi(slave); 254 struct spi_regs *regs = spi->ctrl->regs; 255 u32 reg, tmpdout, tmpdin = 0; 256 const u8 *dout = data_out; 257 u8 *din = data_in; 258 int num_bytes; 259 int ret; 260 261 debug("%s: slave %u:%u dout %p din %p bitlen %u\n", 262 __func__, slave->bus, slave->cs, dout, din, bitlen); 263 if (bitlen % 8) 264 return -1; 265 num_bytes = bitlen / 8; 266 267 ret = 0; 268 269 reg = readl(®s->status); 270 writel(reg, ®s->status); /* Clear all SPI events via R/W */ 271 debug("%s entry: STATUS = %08x\n", __func__, reg); 272 273 reg = readl(®s->status2); 274 writel(reg, ®s->status2); /* Clear all STATUS2 events via R/W */ 275 debug("%s entry: STATUS2 = %08x\n", __func__, reg); 276 277 debug("%s entry: COMMAND = %08x\n", __func__, readl(®s->command)); 278 279 clrsetbits_le32(®s->command2, SLINK_CMD2_SS_EN_MASK, 280 SLINK_CMD2_TXEN | SLINK_CMD2_RXEN | 281 (slave->cs << SLINK_CMD2_SS_EN_SHIFT)); 282 debug("%s entry: COMMAND2 = %08x\n", __func__, readl(®s->command2)); 283 284 if (flags & SPI_XFER_BEGIN) 285 spi_cs_activate(slave); 286 287 /* handle data in 32-bit chunks */ 288 while (num_bytes > 0) { 289 int bytes; 290 int is_read = 0; 291 int tm, i; 292 293 tmpdout = 0; 294 bytes = (num_bytes > 4) ? 4 : num_bytes; 295 296 if (dout != NULL) { 297 for (i = 0; i < bytes; ++i) 298 tmpdout = (tmpdout << 8) | dout[i]; 299 dout += bytes; 300 } 301 302 num_bytes -= bytes; 303 304 clrsetbits_le32(®s->command, SLINK_CMD_BIT_LENGTH_MASK, 305 bytes * 8 - 1); 306 writel(tmpdout, ®s->tx_fifo); 307 setbits_le32(®s->command, SLINK_CMD_GO); 308 309 /* 310 * Wait for SPI transmit FIFO to empty, or to time out. 311 * The RX FIFO status will be read and cleared last 312 */ 313 for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) { 314 u32 status; 315 316 status = readl(®s->status); 317 318 /* We can exit when we've had both RX and TX activity */ 319 if (is_read && (status & SLINK_STAT_TXF_EMPTY)) 320 break; 321 322 if ((status & (SLINK_STAT_BSY | SLINK_STAT_RDY)) != 323 SLINK_STAT_RDY) 324 tm++; 325 326 else if (!(status & SLINK_STAT_RXF_EMPTY)) { 327 tmpdin = readl(®s->rx_fifo); 328 is_read = 1; 329 330 /* swap bytes read in */ 331 if (din != NULL) { 332 for (i = bytes - 1; i >= 0; --i) { 333 din[i] = tmpdin & 0xff; 334 tmpdin >>= 8; 335 } 336 din += bytes; 337 } 338 } 339 } 340 341 if (tm >= SPI_TIMEOUT) 342 ret = tm; 343 344 /* clear ACK RDY, etc. bits */ 345 writel(readl(®s->status), ®s->status); 346 } 347 348 if (flags & SPI_XFER_END) 349 spi_cs_deactivate(slave); 350 351 debug("%s: transfer ended. Value=%08x, status = %08x\n", 352 __func__, tmpdin, readl(®s->status)); 353 354 if (ret) { 355 printf("%s: timeout during SPI transfer, tm %d\n", 356 __func__, ret); 357 return -1; 358 } 359 360 return 0; 361 } 362