1 /* 2 * Copyright (c) 2010-2012 NVIDIA Corporation 3 * With help from the mpc8xxx SPI driver 4 * With more help from omap3_spi SPI driver 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <malloc.h> 27 #include <asm/io.h> 28 #include <asm/gpio.h> 29 #include <asm/arch/clock.h> 30 #include <asm/arch/pinmux.h> 31 #include <asm/arch-tegra/clk_rst.h> 32 #include <asm/arch-tegra20/tegra20_sflash.h> 33 #include <spi.h> 34 #include <fdtdec.h> 35 36 DECLARE_GLOBAL_DATA_PTR; 37 38 #define SPI_CMD_GO (1 << 30) 39 #define SPI_CMD_ACTIVE_SCLK_SHIFT 26 40 #define SPI_CMD_ACTIVE_SCLK_MASK (3 << SPI_CMD_ACTIVE_SCLK_SHIFT) 41 #define SPI_CMD_CK_SDA (1 << 21) 42 #define SPI_CMD_ACTIVE_SDA_SHIFT 18 43 #define SPI_CMD_ACTIVE_SDA_MASK (3 << SPI_CMD_ACTIVE_SDA_SHIFT) 44 #define SPI_CMD_CS_POL (1 << 16) 45 #define SPI_CMD_TXEN (1 << 15) 46 #define SPI_CMD_RXEN (1 << 14) 47 #define SPI_CMD_CS_VAL (1 << 13) 48 #define SPI_CMD_CS_SOFT (1 << 12) 49 #define SPI_CMD_CS_DELAY (1 << 9) 50 #define SPI_CMD_CS3_EN (1 << 8) 51 #define SPI_CMD_CS2_EN (1 << 7) 52 #define SPI_CMD_CS1_EN (1 << 6) 53 #define SPI_CMD_CS0_EN (1 << 5) 54 #define SPI_CMD_BIT_LENGTH (1 << 4) 55 #define SPI_CMD_BIT_LENGTH_MASK 0x0000001F 56 57 #define SPI_STAT_BSY (1 << 31) 58 #define SPI_STAT_RDY (1 << 30) 59 #define SPI_STAT_RXF_FLUSH (1 << 29) 60 #define SPI_STAT_TXF_FLUSH (1 << 28) 61 #define SPI_STAT_RXF_UNR (1 << 27) 62 #define SPI_STAT_TXF_OVF (1 << 26) 63 #define SPI_STAT_RXF_EMPTY (1 << 25) 64 #define SPI_STAT_RXF_FULL (1 << 24) 65 #define SPI_STAT_TXF_EMPTY (1 << 23) 66 #define SPI_STAT_TXF_FULL (1 << 22) 67 #define SPI_STAT_SEL_TXRX_N (1 << 16) 68 #define SPI_STAT_CUR_BLKCNT (1 << 15) 69 70 #define SPI_TIMEOUT 1000 71 #define TEGRA_SPI_MAX_FREQ 52000000 72 73 struct spi_regs { 74 u32 command; /* SPI_COMMAND_0 register */ 75 u32 status; /* SPI_STATUS_0 register */ 76 u32 rx_cmp; /* SPI_RX_CMP_0 register */ 77 u32 dma_ctl; /* SPI_DMA_CTL_0 register */ 78 u32 tx_fifo; /* SPI_TX_FIFO_0 register */ 79 u32 rsvd[3]; /* offsets 0x14 to 0x1F reserved */ 80 u32 rx_fifo; /* SPI_RX_FIFO_0 register */ 81 }; 82 83 struct tegra_spi_slave { 84 struct spi_slave slave; 85 struct spi_regs *regs; 86 unsigned int freq; 87 unsigned int mode; 88 int periph_id; 89 }; 90 91 static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave) 92 { 93 return container_of(slave, struct tegra_spi_slave, slave); 94 } 95 96 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 97 { 98 /* Tegra20 SPI-Flash - only 1 device ('bus/cs') */ 99 if (bus != 0 || cs != 0) 100 return 0; 101 else 102 return 1; 103 } 104 105 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 106 unsigned int max_hz, unsigned int mode) 107 { 108 struct tegra_spi_slave *spi; 109 int node; 110 111 if (!spi_cs_is_valid(bus, cs)) { 112 printf("SPI error: unsupported bus %d / chip select %d\n", 113 bus, cs); 114 return NULL; 115 } 116 117 if (max_hz > TEGRA_SPI_MAX_FREQ) { 118 printf("SPI error: unsupported frequency %d Hz. Max frequency" 119 " is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ); 120 return NULL; 121 } 122 123 spi = malloc(sizeof(struct tegra_spi_slave)); 124 if (!spi) { 125 printf("SPI error: malloc of SPI structure failed\n"); 126 return NULL; 127 } 128 spi->slave.bus = bus; 129 spi->slave.cs = cs; 130 131 node = fdtdec_next_compatible(gd->fdt_blob, 0, 132 COMPAT_NVIDIA_TEGRA20_SFLASH); 133 if (node < 0) { 134 debug("%s: cannot locate sflash node\n", __func__); 135 return NULL; 136 } 137 if (!fdtdec_get_is_enabled(gd->fdt_blob, node)) { 138 debug("%s: sflash is disabled\n", __func__); 139 return NULL; 140 } 141 spi->regs = (struct spi_regs *)fdtdec_get_addr(gd->fdt_blob, 142 node, "reg"); 143 if ((fdt_addr_t)spi->regs == FDT_ADDR_T_NONE) { 144 debug("%s: no sflash register found\n", __func__); 145 return NULL; 146 } 147 spi->freq = fdtdec_get_int(gd->fdt_blob, node, "spi-max-frequency", 0); 148 if (!spi->freq) { 149 debug("%s: no sflash max frequency found\n", __func__); 150 return NULL; 151 } 152 spi->periph_id = clock_decode_periph_id(gd->fdt_blob, node); 153 if (spi->periph_id == PERIPH_ID_NONE) { 154 debug("%s: could not decode periph id\n", __func__); 155 return NULL; 156 } 157 if (max_hz < spi->freq) { 158 debug("%s: limiting frequency from %u to %u\n", __func__, 159 spi->freq, max_hz); 160 spi->freq = max_hz; 161 } 162 debug("%s: controller initialized at %p, freq = %u, periph_id = %d\n", 163 __func__, spi->regs, spi->freq, spi->periph_id); 164 spi->mode = mode; 165 166 return &spi->slave; 167 } 168 169 void spi_free_slave(struct spi_slave *slave) 170 { 171 struct tegra_spi_slave *spi = to_tegra_spi(slave); 172 173 free(spi); 174 } 175 176 void spi_init(void) 177 { 178 /* do nothing */ 179 } 180 181 int spi_claim_bus(struct spi_slave *slave) 182 { 183 struct tegra_spi_slave *spi = to_tegra_spi(slave); 184 struct spi_regs *regs = spi->regs; 185 u32 reg; 186 187 /* Change SPI clock to correct frequency, PLLP_OUT0 source */ 188 clock_start_periph_pll(spi->periph_id, CLOCK_ID_PERIPH, spi->freq); 189 190 /* Clear stale status here */ 191 reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \ 192 SPI_STAT_RXF_UNR | SPI_STAT_TXF_OVF; 193 writel(reg, ®s->status); 194 debug("spi_init: STATUS = %08x\n", readl(®s->status)); 195 196 /* 197 * Use sw-controlled CS, so we can clock in data after ReadID, etc. 198 */ 199 reg = (spi->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT; 200 if (spi->mode & 2) 201 reg |= 1 << SPI_CMD_ACTIVE_SCLK_SHIFT; 202 clrsetbits_le32(®s->command, SPI_CMD_ACTIVE_SCLK_MASK | 203 SPI_CMD_ACTIVE_SDA_MASK, SPI_CMD_CS_SOFT | reg); 204 debug("spi_init: COMMAND = %08x\n", readl(®s->command)); 205 206 /* 207 * SPI pins on Tegra20 are muxed - change pinmux later due to UART 208 * issue. 209 */ 210 pinmux_set_func(PINGRP_GMD, PMUX_FUNC_SFLASH); 211 pinmux_tristate_disable(PINGRP_LSPI); 212 pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH); 213 214 return 0; 215 } 216 217 void spi_release_bus(struct spi_slave *slave) 218 { 219 /* 220 * We can't release UART_DISABLE and set pinmux to UART4 here since 221 * some code (e,g, spi_flash_probe) uses printf() while the SPI 222 * bus is held. That is arguably bad, but it has the advantage of 223 * already being in the source tree. 224 */ 225 } 226 227 void spi_cs_activate(struct spi_slave *slave) 228 { 229 struct tegra_spi_slave *spi = to_tegra_spi(slave); 230 231 /* CS is negated on Tegra, so drive a 1 to get a 0 */ 232 setbits_le32(&spi->regs->command, SPI_CMD_CS_VAL); 233 } 234 235 void spi_cs_deactivate(struct spi_slave *slave) 236 { 237 struct tegra_spi_slave *spi = to_tegra_spi(slave); 238 239 /* CS is negated on Tegra, so drive a 0 to get a 1 */ 240 clrbits_le32(&spi->regs->command, SPI_CMD_CS_VAL); 241 } 242 243 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, 244 const void *data_out, void *data_in, unsigned long flags) 245 { 246 struct tegra_spi_slave *spi = to_tegra_spi(slave); 247 struct spi_regs *regs = spi->regs; 248 u32 reg, tmpdout, tmpdin = 0; 249 const u8 *dout = data_out; 250 u8 *din = data_in; 251 int num_bytes; 252 int ret; 253 254 debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n", 255 slave->bus, slave->cs, *(u8 *)dout, *(u8 *)din, bitlen); 256 if (bitlen % 8) 257 return -1; 258 num_bytes = bitlen / 8; 259 260 ret = 0; 261 262 reg = readl(®s->status); 263 writel(reg, ®s->status); /* Clear all SPI events via R/W */ 264 debug("spi_xfer entry: STATUS = %08x\n", reg); 265 266 reg = readl(®s->command); 267 reg |= SPI_CMD_TXEN | SPI_CMD_RXEN; 268 writel(reg, ®s->command); 269 debug("spi_xfer: COMMAND = %08x\n", readl(®s->command)); 270 271 if (flags & SPI_XFER_BEGIN) 272 spi_cs_activate(slave); 273 274 /* handle data in 32-bit chunks */ 275 while (num_bytes > 0) { 276 int bytes; 277 int is_read = 0; 278 int tm, i; 279 280 tmpdout = 0; 281 bytes = (num_bytes > 4) ? 4 : num_bytes; 282 283 if (dout != NULL) { 284 for (i = 0; i < bytes; ++i) 285 tmpdout = (tmpdout << 8) | dout[i]; 286 } 287 288 num_bytes -= bytes; 289 if (dout) 290 dout += bytes; 291 292 clrsetbits_le32(®s->command, SPI_CMD_BIT_LENGTH_MASK, 293 bytes * 8 - 1); 294 writel(tmpdout, ®s->tx_fifo); 295 setbits_le32(®s->command, SPI_CMD_GO); 296 297 /* 298 * Wait for SPI transmit FIFO to empty, or to time out. 299 * The RX FIFO status will be read and cleared last 300 */ 301 for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) { 302 u32 status; 303 304 status = readl(®s->status); 305 306 /* We can exit when we've had both RX and TX activity */ 307 if (is_read && (status & SPI_STAT_TXF_EMPTY)) 308 break; 309 310 if ((status & (SPI_STAT_BSY | SPI_STAT_RDY)) != 311 SPI_STAT_RDY) 312 tm++; 313 314 else if (!(status & SPI_STAT_RXF_EMPTY)) { 315 tmpdin = readl(®s->rx_fifo); 316 is_read = 1; 317 318 /* swap bytes read in */ 319 if (din != NULL) { 320 for (i = bytes - 1; i >= 0; --i) { 321 din[i] = tmpdin & 0xff; 322 tmpdin >>= 8; 323 } 324 din += bytes; 325 } 326 } 327 } 328 329 if (tm >= SPI_TIMEOUT) 330 ret = tm; 331 332 /* clear ACK RDY, etc. bits */ 333 writel(readl(®s->status), ®s->status); 334 } 335 336 if (flags & SPI_XFER_END) 337 spi_cs_deactivate(slave); 338 339 debug("spi_xfer: transfer ended. Value=%08x, status = %08x\n", 340 tmpdin, readl(®s->status)); 341 342 if (ret) { 343 printf("spi_xfer: timeout during SPI transfer, tm %d\n", ret); 344 return -1; 345 } 346 347 return 0; 348 } 349