1 /* 2 * Copyright (c) 2010-2012 NVIDIA Corporation 3 * With help from the mpc8xxx SPI driver 4 * With more help from omap3_spi SPI driver 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <malloc.h> 27 #include <asm/io.h> 28 #include <asm/gpio.h> 29 #include <asm/arch/clock.h> 30 #include <asm/arch/pinmux.h> 31 #include <asm/arch-tegra/clk_rst.h> 32 #include <asm/arch-tegra20/tegra20_sflash.h> 33 #include <spi.h> 34 #include <fdtdec.h> 35 36 DECLARE_GLOBAL_DATA_PTR; 37 38 struct tegra_spi_slave { 39 struct spi_slave slave; 40 struct spi_tegra *regs; 41 unsigned int freq; 42 unsigned int mode; 43 int periph_id; 44 }; 45 46 static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave) 47 { 48 return container_of(slave, struct tegra_spi_slave, slave); 49 } 50 51 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 52 { 53 /* Tegra20 SPI-Flash - only 1 device ('bus/cs') */ 54 if (bus != 0 || cs != 0) 55 return 0; 56 else 57 return 1; 58 } 59 60 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 61 unsigned int max_hz, unsigned int mode) 62 { 63 struct tegra_spi_slave *spi; 64 int node; 65 66 if (!spi_cs_is_valid(bus, cs)) { 67 printf("SPI error: unsupported bus %d / chip select %d\n", 68 bus, cs); 69 return NULL; 70 } 71 72 if (max_hz > TEGRA_SPI_MAX_FREQ) { 73 printf("SPI error: unsupported frequency %d Hz. Max frequency" 74 " is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ); 75 return NULL; 76 } 77 78 spi = malloc(sizeof(struct tegra_spi_slave)); 79 if (!spi) { 80 printf("SPI error: malloc of SPI structure failed\n"); 81 return NULL; 82 } 83 spi->slave.bus = bus; 84 spi->slave.cs = cs; 85 86 node = fdtdec_next_compatible(gd->fdt_blob, 0, 87 COMPAT_NVIDIA_TEGRA20_SFLASH); 88 if (node < 0) { 89 debug("%s: cannot locate sflash node\n", __func__); 90 return NULL; 91 } 92 if (!fdtdec_get_is_enabled(gd->fdt_blob, node)) { 93 debug("%s: sflash is disabled\n", __func__); 94 return NULL; 95 } 96 spi->regs = (struct spi_tegra *)fdtdec_get_addr(gd->fdt_blob, 97 node, "reg"); 98 if ((fdt_addr_t)spi->regs == FDT_ADDR_T_NONE) { 99 debug("%s: no sflash register found\n", __func__); 100 return NULL; 101 } 102 spi->freq = fdtdec_get_int(gd->fdt_blob, node, "spi-max-frequency", 0); 103 if (!spi->freq) { 104 debug("%s: no sflash max frequency found\n", __func__); 105 return NULL; 106 } 107 spi->periph_id = clock_decode_periph_id(gd->fdt_blob, node); 108 if (spi->periph_id == PERIPH_ID_NONE) { 109 debug("%s: could not decode periph id\n", __func__); 110 return NULL; 111 } 112 if (max_hz < spi->freq) { 113 debug("%s: limiting frequency from %u to %u\n", __func__, 114 spi->freq, max_hz); 115 spi->freq = max_hz; 116 } 117 debug("%s: controller initialized at %p, freq = %u, periph_id = %d\n", 118 __func__, spi->regs, spi->freq, spi->periph_id); 119 spi->mode = mode; 120 121 return &spi->slave; 122 } 123 124 void spi_free_slave(struct spi_slave *slave) 125 { 126 struct tegra_spi_slave *spi = to_tegra_spi(slave); 127 128 free(spi); 129 } 130 131 void spi_init(void) 132 { 133 /* do nothing */ 134 } 135 136 int spi_claim_bus(struct spi_slave *slave) 137 { 138 struct tegra_spi_slave *spi = to_tegra_spi(slave); 139 struct spi_tegra *regs = spi->regs; 140 u32 reg; 141 142 /* Change SPI clock to correct frequency, PLLP_OUT0 source */ 143 clock_start_periph_pll(spi->periph_id, CLOCK_ID_PERIPH, spi->freq); 144 145 /* Clear stale status here */ 146 reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \ 147 SPI_STAT_RXF_UNR | SPI_STAT_TXF_OVF; 148 writel(reg, ®s->status); 149 debug("spi_init: STATUS = %08x\n", readl(®s->status)); 150 151 /* 152 * Use sw-controlled CS, so we can clock in data after ReadID, etc. 153 */ 154 reg = (spi->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT; 155 if (spi->mode & 2) 156 reg |= 1 << SPI_CMD_ACTIVE_SCLK_SHIFT; 157 clrsetbits_le32(®s->command, SPI_CMD_ACTIVE_SCLK_MASK | 158 SPI_CMD_ACTIVE_SDA_MASK, SPI_CMD_CS_SOFT | reg); 159 debug("spi_init: COMMAND = %08x\n", readl(®s->command)); 160 161 /* 162 * SPI pins on Tegra20 are muxed - change pinmux later due to UART 163 * issue. 164 */ 165 pinmux_set_func(PINGRP_GMD, PMUX_FUNC_SFLASH); 166 pinmux_tristate_disable(PINGRP_LSPI); 167 pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH); 168 169 return 0; 170 } 171 172 void spi_release_bus(struct spi_slave *slave) 173 { 174 /* 175 * We can't release UART_DISABLE and set pinmux to UART4 here since 176 * some code (e,g, spi_flash_probe) uses printf() while the SPI 177 * bus is held. That is arguably bad, but it has the advantage of 178 * already being in the source tree. 179 */ 180 } 181 182 void spi_cs_activate(struct spi_slave *slave) 183 { 184 struct tegra_spi_slave *spi = to_tegra_spi(slave); 185 186 /* CS is negated on Tegra, so drive a 1 to get a 0 */ 187 setbits_le32(&spi->regs->command, SPI_CMD_CS_VAL); 188 } 189 190 void spi_cs_deactivate(struct spi_slave *slave) 191 { 192 struct tegra_spi_slave *spi = to_tegra_spi(slave); 193 194 /* CS is negated on Tegra, so drive a 0 to get a 1 */ 195 clrbits_le32(&spi->regs->command, SPI_CMD_CS_VAL); 196 } 197 198 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, 199 const void *data_out, void *data_in, unsigned long flags) 200 { 201 struct tegra_spi_slave *spi = to_tegra_spi(slave); 202 struct spi_tegra *regs = spi->regs; 203 u32 reg, tmpdout, tmpdin = 0; 204 const u8 *dout = data_out; 205 u8 *din = data_in; 206 int num_bytes; 207 int ret; 208 209 debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n", 210 slave->bus, slave->cs, *(u8 *)dout, *(u8 *)din, bitlen); 211 if (bitlen % 8) 212 return -1; 213 num_bytes = bitlen / 8; 214 215 ret = 0; 216 217 reg = readl(®s->status); 218 writel(reg, ®s->status); /* Clear all SPI events via R/W */ 219 debug("spi_xfer entry: STATUS = %08x\n", reg); 220 221 reg = readl(®s->command); 222 reg |= SPI_CMD_TXEN | SPI_CMD_RXEN; 223 writel(reg, ®s->command); 224 debug("spi_xfer: COMMAND = %08x\n", readl(®s->command)); 225 226 if (flags & SPI_XFER_BEGIN) 227 spi_cs_activate(slave); 228 229 /* handle data in 32-bit chunks */ 230 while (num_bytes > 0) { 231 int bytes; 232 int is_read = 0; 233 int tm, i; 234 235 tmpdout = 0; 236 bytes = (num_bytes > 4) ? 4 : num_bytes; 237 238 if (dout != NULL) { 239 for (i = 0; i < bytes; ++i) 240 tmpdout = (tmpdout << 8) | dout[i]; 241 } 242 243 num_bytes -= bytes; 244 if (dout) 245 dout += bytes; 246 247 clrsetbits_le32(®s->command, SPI_CMD_BIT_LENGTH_MASK, 248 bytes * 8 - 1); 249 writel(tmpdout, ®s->tx_fifo); 250 setbits_le32(®s->command, SPI_CMD_GO); 251 252 /* 253 * Wait for SPI transmit FIFO to empty, or to time out. 254 * The RX FIFO status will be read and cleared last 255 */ 256 for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) { 257 u32 status; 258 259 status = readl(®s->status); 260 261 /* We can exit when we've had both RX and TX activity */ 262 if (is_read && (status & SPI_STAT_TXF_EMPTY)) 263 break; 264 265 if ((status & (SPI_STAT_BSY | SPI_STAT_RDY)) != 266 SPI_STAT_RDY) 267 tm++; 268 269 else if (!(status & SPI_STAT_RXF_EMPTY)) { 270 tmpdin = readl(®s->rx_fifo); 271 is_read = 1; 272 273 /* swap bytes read in */ 274 if (din != NULL) { 275 for (i = bytes - 1; i >= 0; --i) { 276 din[i] = tmpdin & 0xff; 277 tmpdin >>= 8; 278 } 279 din += bytes; 280 } 281 } 282 } 283 284 if (tm >= SPI_TIMEOUT) 285 ret = tm; 286 287 /* clear ACK RDY, etc. bits */ 288 writel(readl(®s->status), ®s->status); 289 } 290 291 if (flags & SPI_XFER_END) 292 spi_cs_deactivate(slave); 293 294 debug("spi_xfer: transfer ended. Value=%08x, status = %08x\n", 295 tmpdin, readl(®s->status)); 296 297 if (ret) { 298 printf("spi_xfer: timeout during SPI transfer, tm %d\n", ret); 299 return -1; 300 } 301 302 return 0; 303 } 304