11b2fd5bfSSimon Glass /* 21b2fd5bfSSimon Glass * SPI driver for rockchip 31b2fd5bfSSimon Glass * 41b2fd5bfSSimon Glass * (C) Copyright 2015 Google, Inc 51b2fd5bfSSimon Glass * 61b2fd5bfSSimon Glass * (C) Copyright 2008-2013 Rockchip Electronics 71b2fd5bfSSimon Glass * Peter, Software Engineering, <superpeter.cai@gmail.com>. 81b2fd5bfSSimon Glass * 91b2fd5bfSSimon Glass * SPDX-License-Identifier: GPL-2.0+ 101b2fd5bfSSimon Glass */ 111b2fd5bfSSimon Glass 121b2fd5bfSSimon Glass #ifndef __RK_SPI_H 131b2fd5bfSSimon Glass #define __RK_SPI_H 141b2fd5bfSSimon Glass 151b2fd5bfSSimon Glass struct rockchip_spi { 161b2fd5bfSSimon Glass u32 ctrlr0; 171b2fd5bfSSimon Glass u32 ctrlr1; 181b2fd5bfSSimon Glass u32 enr; 191b2fd5bfSSimon Glass u32 ser; 201b2fd5bfSSimon Glass u32 baudr; 211b2fd5bfSSimon Glass u32 txftlr; 221b2fd5bfSSimon Glass u32 rxftlr; 231b2fd5bfSSimon Glass u32 txflr; 241b2fd5bfSSimon Glass u32 rxflr; 251b2fd5bfSSimon Glass u32 sr; 261b2fd5bfSSimon Glass u32 ipr; 271b2fd5bfSSimon Glass u32 imr; 281b2fd5bfSSimon Glass u32 isr; 291b2fd5bfSSimon Glass u32 risr; 301b2fd5bfSSimon Glass u32 icr; 311b2fd5bfSSimon Glass u32 dmacr; 321b2fd5bfSSimon Glass u32 dmatdlr; 331b2fd5bfSSimon Glass u32 dmardlr; /* 0x44 */ 341b2fd5bfSSimon Glass u32 reserved[0xef]; 351b2fd5bfSSimon Glass u32 txdr[0x100]; /* 0x400 */ 361b2fd5bfSSimon Glass u32 rxdr[0x100]; /* 0x800 */ 371b2fd5bfSSimon Glass }; 381b2fd5bfSSimon Glass 391b2fd5bfSSimon Glass /* CTRLR0 */ 401b2fd5bfSSimon Glass enum { 411b2fd5bfSSimon Glass DFS_SHIFT = 0, /* Data Frame Size */ 421b2fd5bfSSimon Glass DFS_MASK = 3, 431b2fd5bfSSimon Glass DFS_4BIT = 0, 441b2fd5bfSSimon Glass DFS_8BIT, 451b2fd5bfSSimon Glass DFS_16BIT, 461b2fd5bfSSimon Glass DFS_RESV, 471b2fd5bfSSimon Glass 481b2fd5bfSSimon Glass CFS_SHIFT = 2, /* Control Frame Size */ 491b2fd5bfSSimon Glass CFS_MASK = 0xf, 501b2fd5bfSSimon Glass 511b2fd5bfSSimon Glass SCPH_SHIFT = 6, /* Serial Clock Phase */ 521b2fd5bfSSimon Glass SCPH_MASK = 1, 531b2fd5bfSSimon Glass SCPH_TOGMID = 0, /* SCLK toggles in middle of first data bit */ 541b2fd5bfSSimon Glass SCPH_TOGSTA, /* SCLK toggles at start of first data bit */ 551b2fd5bfSSimon Glass 561b2fd5bfSSimon Glass SCOL_SHIFT = 7, /* Serial Clock Polarity */ 571b2fd5bfSSimon Glass SCOL_MASK = 1, 581b2fd5bfSSimon Glass SCOL_LOW = 0, /* Inactive state of serial clock is low */ 591b2fd5bfSSimon Glass SCOL_HIGH, /* Inactive state of serial clock is high */ 601b2fd5bfSSimon Glass 611b2fd5bfSSimon Glass CSM_SHIFT = 8, /* Chip Select Mode */ 621b2fd5bfSSimon Glass CSM_MASK = 0x3, 631b2fd5bfSSimon Glass CSM_KEEP = 0, /* ss_n stays low after each frame */ 641b2fd5bfSSimon Glass CSM_HALF, /* ss_n high for half sclk_out cycles */ 651b2fd5bfSSimon Glass CSM_ONE, /* ss_n high for one sclk_out cycle */ 661b2fd5bfSSimon Glass CSM_RESV, 671b2fd5bfSSimon Glass 681b2fd5bfSSimon Glass SSN_DELAY_SHIFT = 10, /* SSN to Sclk_out delay */ 691b2fd5bfSSimon Glass SSN_DELAY_MASK = 1, 701b2fd5bfSSimon Glass SSN_DELAY_HALF = 0, /* 1/2 sclk_out cycle */ 711b2fd5bfSSimon Glass SSN_DELAY_ONE = 1, /* 1 sclk_out cycle */ 721b2fd5bfSSimon Glass 731b2fd5bfSSimon Glass SEM_SHIFT = 11, /* Serial Endian Mode */ 741b2fd5bfSSimon Glass SEM_MASK = 1, 751b2fd5bfSSimon Glass SEM_LITTLE = 0, /* little endian */ 761b2fd5bfSSimon Glass SEM_BIG, /* big endian */ 771b2fd5bfSSimon Glass 781b2fd5bfSSimon Glass FBM_SHIFT = 12, /* First Bit Mode */ 791b2fd5bfSSimon Glass FBM_MASK = 1, 801b2fd5bfSSimon Glass FBM_MSB = 0, /* first bit is MSB */ 811b2fd5bfSSimon Glass FBM_LSB, /* first bit in LSB */ 821b2fd5bfSSimon Glass 831b2fd5bfSSimon Glass HALF_WORD_TX_SHIFT = 13, /* Byte and Halfword Transform */ 841b2fd5bfSSimon Glass HALF_WORD_MASK = 1, 851b2fd5bfSSimon Glass HALF_WORD_ON = 0, /* apb 16bit write/read, spi 8bit write/read */ 861b2fd5bfSSimon Glass HALF_WORD_OFF, /* apb 8bit write/read, spi 8bit write/read */ 871b2fd5bfSSimon Glass 881b2fd5bfSSimon Glass RXDSD_SHIFT = 14, /* Rxd Sample Delay, in cycles */ 891b2fd5bfSSimon Glass RXDSD_MASK = 3, 901b2fd5bfSSimon Glass 911b2fd5bfSSimon Glass FRF_SHIFT = 16, /* Frame Format */ 921b2fd5bfSSimon Glass FRF_MASK = 3, 931b2fd5bfSSimon Glass FRF_SPI = 0, /* Motorola SPI */ 941b2fd5bfSSimon Glass FRF_SSP, /* Texas Instruments SSP*/ 951b2fd5bfSSimon Glass FRF_MICROWIRE, /* National Semiconductors Microwire */ 961b2fd5bfSSimon Glass FRF_RESV, 971b2fd5bfSSimon Glass 981b2fd5bfSSimon Glass TMOD_SHIFT = 18, /* Transfer Mode */ 991b2fd5bfSSimon Glass TMOD_MASK = 3, 1001b2fd5bfSSimon Glass TMOD_TR = 0, /* xmit & recv */ 1011b2fd5bfSSimon Glass TMOD_TO, /* xmit only */ 1021b2fd5bfSSimon Glass TMOD_RO, /* recv only */ 1031b2fd5bfSSimon Glass TMOD_RESV, 1041b2fd5bfSSimon Glass 1051b2fd5bfSSimon Glass OMOD_SHIFT = 20, /* Operation Mode */ 1061b2fd5bfSSimon Glass OMOD_MASK = 1, 1071b2fd5bfSSimon Glass OMOD_MASTER = 0, /* Master Mode */ 1081b2fd5bfSSimon Glass OMOD_SLAVE, /* Slave Mode */ 1091b2fd5bfSSimon Glass }; 1101b2fd5bfSSimon Glass 1111b2fd5bfSSimon Glass /* SR */ 1121b2fd5bfSSimon Glass enum { 1131b2fd5bfSSimon Glass SR_MASK = 0x7f, 1141b2fd5bfSSimon Glass SR_BUSY = 1 << 0, 1151b2fd5bfSSimon Glass SR_TF_FULL = 1 << 1, 1161b2fd5bfSSimon Glass SR_TF_EMPT = 1 << 2, 1171b2fd5bfSSimon Glass SR_RF_EMPT = 1 << 3, 1181b2fd5bfSSimon Glass SR_RF_FULL = 1 << 4, 1191b2fd5bfSSimon Glass }; 1201b2fd5bfSSimon Glass 1211b2fd5bfSSimon Glass #define ROCKCHIP_SPI_TIMEOUT_MS 1000 122*bd376714SPhilipp Tomsich 123*bd376714SPhilipp Tomsich /* 124*bd376714SPhilipp Tomsich * We limit the maximum bitrate to 50MBit/s (50MHz) due to an assumed 125*bd376714SPhilipp Tomsich * hardware limitation... the Linux kernel source has the following 126*bd376714SPhilipp Tomsich * comment: 127*bd376714SPhilipp Tomsich * "sclk_out: spi master internal logic in rk3x can support 50Mhz" 128*bd376714SPhilipp Tomsich */ 129*bd376714SPhilipp Tomsich #define ROCKCHIP_SPI_MAX_RATE 50000000 1301b2fd5bfSSimon Glass 1311b2fd5bfSSimon Glass #endif /* __RK_SPI_H */ 132