1 /* 2 * spi driver for rockchip 3 * 4 * (C) Copyright 2015 Google, Inc 5 * 6 * (C) Copyright 2008-2013 Rockchip Electronics 7 * Peter, Software Engineering, <superpeter.cai@gmail.com>. 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <clk.h> 14 #include <dm.h> 15 #include <dt-structs.h> 16 #include <errno.h> 17 #include <spi.h> 18 #include <linux/errno.h> 19 #include <asm/io.h> 20 #include <asm/arch/clock.h> 21 #include <asm/arch/periph.h> 22 #include <dm/pinctrl.h> 23 #include "rk_spi.h" 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 /* Change to 1 to output registers at the start of each transaction */ 28 #define DEBUG_RK_SPI 0 29 30 struct rockchip_spi_platdata { 31 #if CONFIG_IS_ENABLED(OF_PLATDATA) 32 struct dtd_rockchip_rk3288_spi of_plat; 33 #endif 34 s32 frequency; /* Default clock frequency, -1 for none */ 35 fdt_addr_t base; 36 uint deactivate_delay_us; /* Delay to wait after deactivate */ 37 uint activate_delay_us; /* Delay to wait after activate */ 38 }; 39 40 struct rockchip_spi_priv { 41 struct rockchip_spi *regs; 42 struct clk clk; 43 unsigned int max_freq; 44 unsigned int mode; 45 ulong last_transaction_us; /* Time of last transaction end */ 46 u8 bits_per_word; /* max 16 bits per word */ 47 u8 n_bytes; 48 unsigned int speed_hz; 49 unsigned int last_speed_hz; 50 uint input_rate; 51 uint cr0; 52 u32 rsd; /* Rx sample delay cycles */ 53 }; 54 55 #define SPI_FIFO_DEPTH 32 56 #define SPI_CR0_RSD_MAX 0x3 57 58 static void rkspi_dump_regs(struct rockchip_spi *regs) 59 { 60 debug("ctrl0: \t\t0x%08x\n", readl(®s->ctrlr0)); 61 debug("ctrl1: \t\t0x%08x\n", readl(®s->ctrlr1)); 62 debug("ssienr: \t\t0x%08x\n", readl(®s->enr)); 63 debug("ser: \t\t0x%08x\n", readl(®s->ser)); 64 debug("baudr: \t\t0x%08x\n", readl(®s->baudr)); 65 debug("txftlr: \t\t0x%08x\n", readl(®s->txftlr)); 66 debug("rxftlr: \t\t0x%08x\n", readl(®s->rxftlr)); 67 debug("txflr: \t\t0x%08x\n", readl(®s->txflr)); 68 debug("rxflr: \t\t0x%08x\n", readl(®s->rxflr)); 69 debug("sr: \t\t0x%08x\n", readl(®s->sr)); 70 debug("imr: \t\t0x%08x\n", readl(®s->imr)); 71 debug("isr: \t\t0x%08x\n", readl(®s->isr)); 72 debug("dmacr: \t\t0x%08x\n", readl(®s->dmacr)); 73 debug("dmatdlr: \t0x%08x\n", readl(®s->dmatdlr)); 74 debug("dmardlr: \t0x%08x\n", readl(®s->dmardlr)); 75 } 76 77 static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable) 78 { 79 writel(enable ? 1 : 0, ®s->enr); 80 } 81 82 static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed) 83 { 84 /* 85 * We should try not to exceed the speed requested by the caller: 86 * when selecting a divider, we need to make sure we round up. 87 */ 88 uint clk_div = DIV_ROUND_UP(priv->input_rate, speed); 89 90 /* The baudrate register (BAUDR) is defined as a 32bit register where 91 * the upper 16bit are reserved and having 'Fsclk_out' in the lower 92 * 16bits with 'Fsclk_out' defined as follows: 93 * 94 * Fsclk_out = Fspi_clk/ SCKDV 95 * Where SCKDV is any even value between 2 and 65534. 96 */ 97 if (clk_div > 0xfffe) { 98 clk_div = 0xfffe; 99 debug("%s: can't divide down to %d Hz (actual will be %d Hz)\n", 100 __func__, speed, priv->input_rate / clk_div); 101 } 102 103 /* Round up to the next even 16bit number */ 104 clk_div = (clk_div + 1) & 0xfffe; 105 106 debug("spi speed %u, div %u\n", speed, clk_div); 107 108 clrsetbits_le32(&priv->regs->baudr, 0xffff, clk_div); 109 priv->last_speed_hz = speed; 110 } 111 112 static int rkspi_wait_till_not_busy(struct rockchip_spi *regs) 113 { 114 unsigned long start; 115 116 start = get_timer(0); 117 while (readl(®s->sr) & SR_BUSY) { 118 if (get_timer(start) > ROCKCHIP_SPI_TIMEOUT_MS) { 119 debug("RK SPI: Status keeps busy for 1000us after a read/write!\n"); 120 return -ETIMEDOUT; 121 } 122 } 123 124 return 0; 125 } 126 127 static void spi_cs_activate(struct udevice *dev, uint cs) 128 { 129 struct udevice *bus = dev->parent; 130 struct rockchip_spi_platdata *plat = bus->platdata; 131 struct rockchip_spi_priv *priv = dev_get_priv(bus); 132 struct rockchip_spi *regs = priv->regs; 133 134 /* If it's too soon to do another transaction, wait */ 135 if (plat->deactivate_delay_us && priv->last_transaction_us) { 136 ulong delay_us; /* The delay completed so far */ 137 delay_us = timer_get_us() - priv->last_transaction_us; 138 if (delay_us < plat->deactivate_delay_us) 139 udelay(plat->deactivate_delay_us - delay_us); 140 } 141 142 debug("activate cs%u\n", cs); 143 writel(1 << cs, ®s->ser); 144 if (plat->activate_delay_us) 145 udelay(plat->activate_delay_us); 146 } 147 148 static void spi_cs_deactivate(struct udevice *dev, uint cs) 149 { 150 struct udevice *bus = dev->parent; 151 struct rockchip_spi_platdata *plat = bus->platdata; 152 struct rockchip_spi_priv *priv = dev_get_priv(bus); 153 struct rockchip_spi *regs = priv->regs; 154 155 debug("deactivate cs%u\n", cs); 156 writel(0, ®s->ser); 157 158 /* Remember time of this transaction so we can honour the bus delay */ 159 if (plat->deactivate_delay_us) 160 priv->last_transaction_us = timer_get_us(); 161 } 162 163 #if CONFIG_IS_ENABLED(OF_PLATDATA) 164 static int conv_of_platdata(struct udevice *dev) 165 { 166 struct rockchip_spi_platdata *plat = dev->platdata; 167 struct dtd_rockchip_rk3288_spi *dtplat = &plat->of_plat; 168 struct rockchip_spi_priv *priv = dev_get_priv(dev); 169 int ret; 170 171 plat->base = dtplat->reg[0]; 172 plat->frequency = 20000000; 173 ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk); 174 if (ret < 0) 175 return ret; 176 dev->req_seq = 0; 177 178 return 0; 179 } 180 #endif 181 182 static int rockchip_spi_ofdata_to_platdata(struct udevice *bus) 183 { 184 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 185 struct rockchip_spi_platdata *plat = dev_get_platdata(bus); 186 struct rockchip_spi_priv *priv = dev_get_priv(bus); 187 u32 rsd_nsecs; 188 int ret; 189 190 plat->base = dev_read_addr(bus); 191 192 ret = clk_get_by_index(bus, 0, &priv->clk); 193 if (ret < 0) { 194 debug("%s: Could not get clock for %s: %d\n", __func__, 195 bus->name, ret); 196 return ret; 197 } 198 199 plat->frequency = 200 dev_read_u32_default(bus, "spi-max-frequency", 50000000); 201 plat->deactivate_delay_us = 202 dev_read_u32_default(bus, "spi-deactivate-delay", 0); 203 plat->activate_delay_us = 204 dev_read_u32_default(bus, "spi-activate-delay", 0); 205 206 rsd_nsecs = dev_read_u32_default(bus, "rx-sample-delay-ns", 0); 207 if (rsd_nsecs > 0) { 208 u32 spi_clk, rsd; 209 210 spi_clk = clk_get_rate(&priv->clk); 211 /* rx sample delay is expressed in parent clock cycles (max 3) */ 212 rsd = DIV_ROUND_CLOSEST(rsd_nsecs * (spi_clk >> 8), 1000000000 >> 8); 213 if (!rsd) { 214 pr_err("SPI spi_clk %dHz are too slow to express %u ns delay\n", spi_clk, rsd_nsecs); 215 } else if (rsd > SPI_CR0_RSD_MAX) { 216 rsd = SPI_CR0_RSD_MAX; 217 pr_err("SPI spi_clk %dHz are too fast to express %u ns delay, clamping at %u ns\n", 218 spi_clk, rsd_nsecs, SPI_CR0_RSD_MAX * 1000000000U / spi_clk); 219 } 220 priv->rsd = rsd; 221 } 222 223 debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d rsd=%d\n", 224 __func__, (uint)plat->base, plat->frequency, 225 plat->deactivate_delay_us, priv->rsd); 226 #endif 227 228 return 0; 229 } 230 231 static int rockchip_spi_calc_modclk(ulong max_freq) 232 { 233 /* 234 * While this is not strictly correct for the RK3368, as the 235 * GPLL will be 576MHz, things will still work, as the 236 * clk_set_rate(...) implementation in our clock-driver will 237 * chose the next closest rate not exceeding what we request 238 * based on the output of this function. 239 */ 240 241 unsigned div; 242 const unsigned long gpll_hz = 594000000UL; 243 244 /* 245 * We need to find an input clock that provides at least twice 246 * the maximum frequency and can be generated from the assumed 247 * speed of GPLL (594MHz) using an integer divider. 248 * 249 * To give us more achievable bitrates at higher speeds (these 250 * are generated by dividing by an even 16-bit integer from 251 * this frequency), we try to have an input frequency of at 252 * least 4x our max_freq. 253 */ 254 255 div = DIV_ROUND_UP(gpll_hz, max_freq * 4); 256 return gpll_hz / div; 257 } 258 259 static int rockchip_spi_probe(struct udevice *bus) 260 { 261 struct rockchip_spi_platdata *plat = dev_get_platdata(bus); 262 struct rockchip_spi_priv *priv = dev_get_priv(bus); 263 int ret; 264 265 debug("%s: probe\n", __func__); 266 #if CONFIG_IS_ENABLED(OF_PLATDATA) 267 ret = conv_of_platdata(bus); 268 if (ret) 269 return ret; 270 #endif 271 priv->regs = (struct rockchip_spi *)plat->base; 272 273 priv->last_transaction_us = timer_get_us(); 274 priv->max_freq = plat->frequency; 275 276 /* Clamp the value from the DTS against any hardware limits */ 277 if (priv->max_freq > ROCKCHIP_SPI_MAX_RATE) 278 priv->max_freq = ROCKCHIP_SPI_MAX_RATE; 279 280 /* Find a module-input clock that fits with the max_freq setting */ 281 ret = clk_set_rate(&priv->clk, 282 rockchip_spi_calc_modclk(priv->max_freq)); 283 if (ret < 0) { 284 debug("%s: Failed to set clock: %d\n", __func__, ret); 285 return ret; 286 } 287 priv->input_rate = ret; 288 debug("%s: rate = %u\n", __func__, priv->input_rate); 289 priv->bits_per_word = 8; 290 291 return 0; 292 } 293 294 static int rockchip_spi_claim_bus(struct udevice *dev) 295 { 296 struct udevice *bus = dev->parent; 297 struct rockchip_spi_priv *priv = dev_get_priv(bus); 298 struct rockchip_spi *regs = priv->regs; 299 u8 spi_dfs, spi_tf; 300 uint ctrlr0; 301 302 /* Disable the SPI hardware */ 303 rkspi_enable_chip(regs, 0); 304 305 switch (priv->bits_per_word) { 306 case 8: 307 priv->n_bytes = 1; 308 spi_dfs = DFS_8BIT; 309 spi_tf = HALF_WORD_OFF; 310 break; 311 case 16: 312 priv->n_bytes = 2; 313 spi_dfs = DFS_16BIT; 314 spi_tf = HALF_WORD_ON; 315 break; 316 default: 317 debug("%s: unsupported bits: %dbits\n", __func__, 318 priv->bits_per_word); 319 return -EPROTONOSUPPORT; 320 } 321 322 if (priv->speed_hz != priv->last_speed_hz) 323 rkspi_set_clk(priv, priv->speed_hz); 324 325 /* Operation Mode */ 326 ctrlr0 = OMOD_MASTER << OMOD_SHIFT; 327 328 /* Data Frame Size */ 329 ctrlr0 |= spi_dfs << DFS_SHIFT; 330 331 /* set SPI mode 0..3 */ 332 if (priv->mode & SPI_CPOL) 333 ctrlr0 |= SCOL_HIGH << SCOL_SHIFT; 334 if (priv->mode & SPI_CPHA) 335 ctrlr0 |= SCPH_TOGSTA << SCPH_SHIFT; 336 337 /* Chip Select Mode */ 338 ctrlr0 |= CSM_KEEP << CSM_SHIFT; 339 340 /* SSN to Sclk_out delay */ 341 ctrlr0 |= SSN_DELAY_ONE << SSN_DELAY_SHIFT; 342 343 /* Serial Endian Mode */ 344 ctrlr0 |= SEM_LITTLE << SEM_SHIFT; 345 346 /* First Bit Mode */ 347 ctrlr0 |= FBM_MSB << FBM_SHIFT; 348 349 /* Byte and Halfword Transform */ 350 ctrlr0 |= spi_tf << HALF_WORD_TX_SHIFT; 351 352 /* Rxd Sample Delay */ 353 ctrlr0 |= priv->rsd << RXDSD_SHIFT; 354 355 /* Frame Format */ 356 ctrlr0 |= FRF_SPI << FRF_SHIFT; 357 358 /* Save static configuration */ 359 priv->cr0 = ctrlr0; 360 361 writel(ctrlr0, ®s->ctrlr0); 362 363 return 0; 364 } 365 366 static int rockchip_spi_config(struct rockchip_spi_priv *priv, const void *dout) 367 { 368 struct rockchip_spi *regs = priv->regs; 369 uint ctrlr0 = priv->cr0; 370 u32 tmod; 371 372 if (dout) 373 tmod = TMOD_TR; 374 else 375 tmod = TMOD_RO; 376 377 ctrlr0 |= (tmod & TMOD_MASK) << TMOD_SHIFT; 378 writel(ctrlr0, ®s->ctrlr0); 379 380 return 0; 381 } 382 383 static int rockchip_spi_release_bus(struct udevice *dev) 384 { 385 struct udevice *bus = dev->parent; 386 struct rockchip_spi_priv *priv = dev_get_priv(bus); 387 388 rkspi_enable_chip(priv->regs, false); 389 390 return 0; 391 } 392 393 static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen, 394 const void *dout, void *din, unsigned long flags) 395 { 396 struct udevice *bus = dev->parent; 397 struct rockchip_spi_priv *priv = dev_get_priv(bus); 398 struct rockchip_spi *regs = priv->regs; 399 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 400 int len = bitlen >> 3; 401 const u8 *out = dout; 402 u8 *in = din; 403 int toread, towrite; 404 int ret; 405 406 rockchip_spi_config(priv, dout); 407 408 debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din, 409 len, flags); 410 if (DEBUG_RK_SPI) 411 rkspi_dump_regs(regs); 412 413 /* Assert CS before transfer */ 414 if (flags & SPI_XFER_BEGIN) 415 spi_cs_activate(dev, slave_plat->cs); 416 417 while (len > 0) { 418 int todo = min(len, 0xffff); 419 420 rkspi_enable_chip(regs, false); 421 writel(todo - 1, ®s->ctrlr1); 422 rkspi_enable_chip(regs, true); 423 424 toread = todo; 425 towrite = todo; 426 while (toread || towrite) { 427 u32 status = readl(®s->sr); 428 429 if (towrite && !(status & SR_TF_FULL)) { 430 if (out) 431 writel(out ? *out++ : 0, regs->txdr); 432 towrite--; 433 } 434 if (toread && !(status & SR_RF_EMPT)) { 435 u32 byte = readl(regs->rxdr); 436 437 if (in) 438 *in++ = byte; 439 toread--; 440 } 441 } 442 ret = rkspi_wait_till_not_busy(regs); 443 if (ret) 444 break; 445 len -= todo; 446 } 447 448 /* Deassert CS after transfer */ 449 if (flags & SPI_XFER_END) 450 spi_cs_deactivate(dev, slave_plat->cs); 451 452 rkspi_enable_chip(regs, false); 453 454 return ret; 455 } 456 457 static int rockchip_spi_set_speed(struct udevice *bus, uint speed) 458 { 459 struct rockchip_spi_priv *priv = dev_get_priv(bus); 460 461 /* Clamp to the maximum frequency specified in the DTS */ 462 if (speed > priv->max_freq) 463 speed = priv->max_freq; 464 465 priv->speed_hz = speed; 466 467 return 0; 468 } 469 470 static int rockchip_spi_set_mode(struct udevice *bus, uint mode) 471 { 472 struct rockchip_spi_priv *priv = dev_get_priv(bus); 473 474 priv->mode = mode; 475 476 return 0; 477 } 478 479 static const struct dm_spi_ops rockchip_spi_ops = { 480 .claim_bus = rockchip_spi_claim_bus, 481 .release_bus = rockchip_spi_release_bus, 482 .xfer = rockchip_spi_xfer, 483 .set_speed = rockchip_spi_set_speed, 484 .set_mode = rockchip_spi_set_mode, 485 /* 486 * cs_info is not needed, since we require all chip selects to be 487 * in the device tree explicitly 488 */ 489 }; 490 491 static const struct udevice_id rockchip_spi_ids[] = { 492 { .compatible = "rockchip,rk3288-spi" }, 493 { .compatible = "rockchip,rk3368-spi" }, 494 { .compatible = "rockchip,rk3399-spi" }, 495 { .compatible = "rockchip,rk3066-spi" }, 496 { .compatible = "rockchip,rk3328-spi" }, 497 { } 498 }; 499 500 U_BOOT_DRIVER(rockchip_spi) = { 501 #if CONFIG_IS_ENABLED(OF_PLATDATA) 502 .name = "rockchip_rk3288_spi", 503 #else 504 .name = "rockchip_spi", 505 #endif 506 .id = UCLASS_SPI, 507 .of_match = rockchip_spi_ids, 508 .ops = &rockchip_spi_ops, 509 .ofdata_to_platdata = rockchip_spi_ofdata_to_platdata, 510 .platdata_auto_alloc_size = sizeof(struct rockchip_spi_platdata), 511 .priv_auto_alloc_size = sizeof(struct rockchip_spi_priv), 512 .probe = rockchip_spi_probe, 513 }; 514