1 /* 2 * Copyright (C) 2016 Jagan Teki <jteki@openedev.com> 3 * Christophe Ricard <christophe.ricard@gmail.com> 4 * 5 * Copyright (C) 2010 Dirk Behme <dirk.behme@googlemail.com> 6 * 7 * Driver for McSPI controller on OMAP3. Based on davinci_spi.c 8 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ 9 * 10 * Copyright (C) 2007 Atmel Corporation 11 * 12 * Parts taken from linux/drivers/spi/omap2_mcspi.c 13 * Copyright (C) 2005, 2006 Nokia Corporation 14 * 15 * Modified by Ruslan Araslanov <ruslan.araslanov@vitecmm.com> 16 * 17 * SPDX-License-Identifier: GPL-2.0+ 18 */ 19 20 #include <common.h> 21 #include <dm.h> 22 #include <spi.h> 23 #include <malloc.h> 24 #include <asm/io.h> 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 #if defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX) 29 #define OMAP3_MCSPI1_BASE 0x48030100 30 #define OMAP3_MCSPI2_BASE 0x481A0100 31 #else 32 #define OMAP3_MCSPI1_BASE 0x48098000 33 #define OMAP3_MCSPI2_BASE 0x4809A000 34 #define OMAP3_MCSPI3_BASE 0x480B8000 35 #define OMAP3_MCSPI4_BASE 0x480BA000 36 #endif 37 38 /* per-register bitmasks */ 39 #define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3) 40 #define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2) 41 #define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE BIT(0) 42 #define OMAP3_MCSPI_SYSCONFIG_SOFTRESET BIT(1) 43 44 #define OMAP3_MCSPI_SYSSTATUS_RESETDONE BIT(0) 45 46 #define OMAP3_MCSPI_MODULCTRL_SINGLE BIT(0) 47 #define OMAP3_MCSPI_MODULCTRL_MS BIT(2) 48 #define OMAP3_MCSPI_MODULCTRL_STEST BIT(3) 49 50 #define OMAP3_MCSPI_CHCONF_PHA BIT(0) 51 #define OMAP3_MCSPI_CHCONF_POL BIT(1) 52 #define OMAP3_MCSPI_CHCONF_CLKD_MASK GENMASK(5, 2) 53 #define OMAP3_MCSPI_CHCONF_EPOL BIT(6) 54 #define OMAP3_MCSPI_CHCONF_WL_MASK GENMASK(11, 7) 55 #define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY BIT(12) 56 #define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY BIT(13) 57 #define OMAP3_MCSPI_CHCONF_TRM_MASK GENMASK(13, 12) 58 #define OMAP3_MCSPI_CHCONF_DMAW BIT(14) 59 #define OMAP3_MCSPI_CHCONF_DMAR BIT(15) 60 #define OMAP3_MCSPI_CHCONF_DPE0 BIT(16) 61 #define OMAP3_MCSPI_CHCONF_DPE1 BIT(17) 62 #define OMAP3_MCSPI_CHCONF_IS BIT(18) 63 #define OMAP3_MCSPI_CHCONF_TURBO BIT(19) 64 #define OMAP3_MCSPI_CHCONF_FORCE BIT(20) 65 66 #define OMAP3_MCSPI_CHSTAT_RXS BIT(0) 67 #define OMAP3_MCSPI_CHSTAT_TXS BIT(1) 68 #define OMAP3_MCSPI_CHSTAT_EOT BIT(2) 69 70 #define OMAP3_MCSPI_CHCTRL_EN BIT(0) 71 #define OMAP3_MCSPI_CHCTRL_DIS (0 << 0) 72 73 #define OMAP3_MCSPI_WAKEUPENABLE_WKEN BIT(0) 74 #define MCSPI_PINDIR_D0_IN_D1_OUT 0 75 #define MCSPI_PINDIR_D0_OUT_D1_IN 1 76 77 #define OMAP3_MCSPI_MAX_FREQ 48000000 78 #define SPI_WAIT_TIMEOUT 10 79 80 /* OMAP3 McSPI registers */ 81 struct mcspi_channel { 82 unsigned int chconf; /* 0x2C, 0x40, 0x54, 0x68 */ 83 unsigned int chstat; /* 0x30, 0x44, 0x58, 0x6C */ 84 unsigned int chctrl; /* 0x34, 0x48, 0x5C, 0x70 */ 85 unsigned int tx; /* 0x38, 0x4C, 0x60, 0x74 */ 86 unsigned int rx; /* 0x3C, 0x50, 0x64, 0x78 */ 87 }; 88 89 struct mcspi { 90 unsigned char res1[0x10]; 91 unsigned int sysconfig; /* 0x10 */ 92 unsigned int sysstatus; /* 0x14 */ 93 unsigned int irqstatus; /* 0x18 */ 94 unsigned int irqenable; /* 0x1C */ 95 unsigned int wakeupenable; /* 0x20 */ 96 unsigned int syst; /* 0x24 */ 97 unsigned int modulctrl; /* 0x28 */ 98 struct mcspi_channel channel[4]; 99 /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */ 100 /* channel1: 0x40 - 0x50, bus 0 & 1 */ 101 /* channel2: 0x54 - 0x64, bus 0 & 1 */ 102 /* channel3: 0x68 - 0x78, bus 0 */ 103 }; 104 105 struct omap3_spi_priv { 106 struct mcspi *regs; 107 unsigned int cs; 108 unsigned int freq; 109 unsigned int mode; 110 unsigned int wordlen; 111 unsigned int pin_dir:1; 112 }; 113 114 static void omap3_spi_write_chconf(struct omap3_spi_priv *priv, int val) 115 { 116 writel(val, &priv->regs->channel[priv->cs].chconf); 117 /* Flash post writes to make immediate effect */ 118 readl(&priv->regs->channel[priv->cs].chconf); 119 } 120 121 static void omap3_spi_set_enable(struct omap3_spi_priv *priv, int enable) 122 { 123 writel(enable, &priv->regs->channel[priv->cs].chctrl); 124 /* Flash post writes to make immediate effect */ 125 readl(&priv->regs->channel[priv->cs].chctrl); 126 } 127 128 static int omap3_spi_write(struct omap3_spi_priv *priv, unsigned int len, 129 const void *txp, unsigned long flags) 130 { 131 ulong start; 132 int i, chconf; 133 134 chconf = readl(&priv->regs->channel[priv->cs].chconf); 135 136 /* Enable the channel */ 137 omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_EN); 138 139 chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK); 140 chconf |= (priv->wordlen - 1) << 7; 141 chconf |= OMAP3_MCSPI_CHCONF_TRM_TX_ONLY; 142 chconf |= OMAP3_MCSPI_CHCONF_FORCE; 143 omap3_spi_write_chconf(priv, chconf); 144 145 for (i = 0; i < len; i++) { 146 /* wait till TX register is empty (TXS == 1) */ 147 start = get_timer(0); 148 while (!(readl(&priv->regs->channel[priv->cs].chstat) & 149 OMAP3_MCSPI_CHSTAT_TXS)) { 150 if (get_timer(start) > SPI_WAIT_TIMEOUT) { 151 printf("SPI TXS timed out, status=0x%08x\n", 152 readl(&priv->regs->channel[priv->cs].chstat)); 153 return -1; 154 } 155 } 156 /* Write the data */ 157 unsigned int *tx = &priv->regs->channel[priv->cs].tx; 158 if (priv->wordlen > 16) 159 writel(((u32 *)txp)[i], tx); 160 else if (priv->wordlen > 8) 161 writel(((u16 *)txp)[i], tx); 162 else 163 writel(((u8 *)txp)[i], tx); 164 } 165 166 /* wait to finish of transfer */ 167 while ((readl(&priv->regs->channel[priv->cs].chstat) & 168 (OMAP3_MCSPI_CHSTAT_EOT | OMAP3_MCSPI_CHSTAT_TXS)) != 169 (OMAP3_MCSPI_CHSTAT_EOT | OMAP3_MCSPI_CHSTAT_TXS)) 170 ; 171 172 /* Disable the channel otherwise the next immediate RX will get affected */ 173 omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS); 174 175 if (flags & SPI_XFER_END) { 176 177 chconf &= ~OMAP3_MCSPI_CHCONF_FORCE; 178 omap3_spi_write_chconf(priv, chconf); 179 } 180 return 0; 181 } 182 183 static int omap3_spi_read(struct omap3_spi_priv *priv, unsigned int len, 184 void *rxp, unsigned long flags) 185 { 186 int i, chconf; 187 ulong start; 188 189 chconf = readl(&priv->regs->channel[priv->cs].chconf); 190 191 /* Enable the channel */ 192 omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_EN); 193 194 chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK); 195 chconf |= (priv->wordlen - 1) << 7; 196 chconf |= OMAP3_MCSPI_CHCONF_TRM_RX_ONLY; 197 chconf |= OMAP3_MCSPI_CHCONF_FORCE; 198 omap3_spi_write_chconf(priv, chconf); 199 200 writel(0, &priv->regs->channel[priv->cs].tx); 201 202 for (i = 0; i < len; i++) { 203 start = get_timer(0); 204 /* Wait till RX register contains data (RXS == 1) */ 205 while (!(readl(&priv->regs->channel[priv->cs].chstat) & 206 OMAP3_MCSPI_CHSTAT_RXS)) { 207 if (get_timer(start) > SPI_WAIT_TIMEOUT) { 208 printf("SPI RXS timed out, status=0x%08x\n", 209 readl(&priv->regs->channel[priv->cs].chstat)); 210 return -1; 211 } 212 } 213 214 /* Disable the channel to prevent furher receiving */ 215 if (i == (len - 1)) 216 omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS); 217 218 /* Read the data */ 219 unsigned int *rx = &priv->regs->channel[priv->cs].rx; 220 if (priv->wordlen > 16) 221 ((u32 *)rxp)[i] = readl(rx); 222 else if (priv->wordlen > 8) 223 ((u16 *)rxp)[i] = (u16)readl(rx); 224 else 225 ((u8 *)rxp)[i] = (u8)readl(rx); 226 } 227 228 if (flags & SPI_XFER_END) { 229 chconf &= ~OMAP3_MCSPI_CHCONF_FORCE; 230 omap3_spi_write_chconf(priv, chconf); 231 } 232 233 return 0; 234 } 235 236 /*McSPI Transmit Receive Mode*/ 237 static int omap3_spi_txrx(struct omap3_spi_priv *priv, unsigned int len, 238 const void *txp, void *rxp, unsigned long flags) 239 { 240 ulong start; 241 int chconf, i = 0; 242 243 chconf = readl(&priv->regs->channel[priv->cs].chconf); 244 245 /*Enable SPI channel*/ 246 omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_EN); 247 248 /*set TRANSMIT-RECEIVE Mode*/ 249 chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK); 250 chconf |= (priv->wordlen - 1) << 7; 251 chconf |= OMAP3_MCSPI_CHCONF_FORCE; 252 omap3_spi_write_chconf(priv, chconf); 253 254 /*Shift in and out 1 byte at time*/ 255 for (i=0; i < len; i++){ 256 /* Write: wait for TX empty (TXS == 1)*/ 257 start = get_timer(0); 258 while (!(readl(&priv->regs->channel[priv->cs].chstat) & 259 OMAP3_MCSPI_CHSTAT_TXS)) { 260 if (get_timer(start) > SPI_WAIT_TIMEOUT) { 261 printf("SPI TXS timed out, status=0x%08x\n", 262 readl(&priv->regs->channel[priv->cs].chstat)); 263 return -1; 264 } 265 } 266 /* Write the data */ 267 unsigned int *tx = &priv->regs->channel[priv->cs].tx; 268 if (priv->wordlen > 16) 269 writel(((u32 *)txp)[i], tx); 270 else if (priv->wordlen > 8) 271 writel(((u16 *)txp)[i], tx); 272 else 273 writel(((u8 *)txp)[i], tx); 274 275 /*Read: wait for RX containing data (RXS == 1)*/ 276 start = get_timer(0); 277 while (!(readl(&priv->regs->channel[priv->cs].chstat) & 278 OMAP3_MCSPI_CHSTAT_RXS)) { 279 if (get_timer(start) > SPI_WAIT_TIMEOUT) { 280 printf("SPI RXS timed out, status=0x%08x\n", 281 readl(&priv->regs->channel[priv->cs].chstat)); 282 return -1; 283 } 284 } 285 /* Read the data */ 286 unsigned int *rx = &priv->regs->channel[priv->cs].rx; 287 if (priv->wordlen > 16) 288 ((u32 *)rxp)[i] = readl(rx); 289 else if (priv->wordlen > 8) 290 ((u16 *)rxp)[i] = (u16)readl(rx); 291 else 292 ((u8 *)rxp)[i] = (u8)readl(rx); 293 } 294 /* Disable the channel */ 295 omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS); 296 297 /*if transfer must be terminated disable the channel*/ 298 if (flags & SPI_XFER_END) { 299 chconf &= ~OMAP3_MCSPI_CHCONF_FORCE; 300 omap3_spi_write_chconf(priv, chconf); 301 } 302 303 return 0; 304 } 305 306 static int _spi_xfer(struct omap3_spi_priv *priv, unsigned int bitlen, 307 const void *dout, void *din, unsigned long flags) 308 { 309 unsigned int len; 310 int ret = -1; 311 312 if (priv->wordlen < 4 || priv->wordlen > 32) { 313 printf("omap3_spi: invalid wordlen %d\n", priv->wordlen); 314 return -1; 315 } 316 317 if (bitlen % priv->wordlen) 318 return -1; 319 320 len = bitlen / priv->wordlen; 321 322 if (bitlen == 0) { /* only change CS */ 323 int chconf = readl(&priv->regs->channel[priv->cs].chconf); 324 325 if (flags & SPI_XFER_BEGIN) { 326 omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_EN); 327 chconf |= OMAP3_MCSPI_CHCONF_FORCE; 328 omap3_spi_write_chconf(priv, chconf); 329 } 330 if (flags & SPI_XFER_END) { 331 chconf &= ~OMAP3_MCSPI_CHCONF_FORCE; 332 omap3_spi_write_chconf(priv, chconf); 333 omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS); 334 } 335 ret = 0; 336 } else { 337 if (dout != NULL && din != NULL) 338 ret = omap3_spi_txrx(priv, len, dout, din, flags); 339 else if (dout != NULL) 340 ret = omap3_spi_write(priv, len, dout, flags); 341 else if (din != NULL) 342 ret = omap3_spi_read(priv, len, din, flags); 343 } 344 return ret; 345 } 346 347 static void _omap3_spi_set_speed(struct omap3_spi_priv *priv) 348 { 349 uint32_t confr, div = 0; 350 351 confr = readl(&priv->regs->channel[priv->cs].chconf); 352 353 /* Calculate clock divisor. Valid range: 0x0 - 0xC ( /1 - /4096 ) */ 354 if (priv->freq) { 355 while (div <= 0xC && (OMAP3_MCSPI_MAX_FREQ / (1 << div)) 356 > priv->freq) 357 div++; 358 } else { 359 div = 0xC; 360 } 361 362 /* set clock divisor */ 363 confr &= ~OMAP3_MCSPI_CHCONF_CLKD_MASK; 364 confr |= div << 2; 365 366 omap3_spi_write_chconf(priv, confr); 367 } 368 369 static void _omap3_spi_set_mode(struct omap3_spi_priv *priv) 370 { 371 uint32_t confr; 372 373 confr = readl(&priv->regs->channel[priv->cs].chconf); 374 375 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS 376 * REVISIT: this controller could support SPI_3WIRE mode. 377 */ 378 if (priv->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) { 379 confr &= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1); 380 confr |= OMAP3_MCSPI_CHCONF_DPE0; 381 } else { 382 confr &= ~OMAP3_MCSPI_CHCONF_DPE0; 383 confr |= OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1; 384 } 385 386 /* set SPI mode 0..3 */ 387 confr &= ~(OMAP3_MCSPI_CHCONF_POL | OMAP3_MCSPI_CHCONF_PHA); 388 if (priv->mode & SPI_CPHA) 389 confr |= OMAP3_MCSPI_CHCONF_PHA; 390 if (priv->mode & SPI_CPOL) 391 confr |= OMAP3_MCSPI_CHCONF_POL; 392 393 /* set chipselect polarity; manage with FORCE */ 394 if (!(priv->mode & SPI_CS_HIGH)) 395 confr |= OMAP3_MCSPI_CHCONF_EPOL; /* active-low; normal */ 396 else 397 confr &= ~OMAP3_MCSPI_CHCONF_EPOL; 398 399 /* Transmit & receive mode */ 400 confr &= ~OMAP3_MCSPI_CHCONF_TRM_MASK; 401 402 omap3_spi_write_chconf(priv, confr); 403 } 404 405 static void _omap3_spi_set_wordlen(struct omap3_spi_priv *priv) 406 { 407 unsigned int confr; 408 409 /* McSPI individual channel configuration */ 410 confr = readl(&priv->regs->channel[priv->wordlen].chconf); 411 412 /* wordlength */ 413 confr &= ~OMAP3_MCSPI_CHCONF_WL_MASK; 414 confr |= (priv->wordlen - 1) << 7; 415 416 omap3_spi_write_chconf(priv, confr); 417 } 418 419 static void spi_reset(struct mcspi *regs) 420 { 421 unsigned int tmp; 422 423 writel(OMAP3_MCSPI_SYSCONFIG_SOFTRESET, ®s->sysconfig); 424 do { 425 tmp = readl(®s->sysstatus); 426 } while (!(tmp & OMAP3_MCSPI_SYSSTATUS_RESETDONE)); 427 428 writel(OMAP3_MCSPI_SYSCONFIG_AUTOIDLE | 429 OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP | 430 OMAP3_MCSPI_SYSCONFIG_SMARTIDLE, ®s->sysconfig); 431 432 writel(OMAP3_MCSPI_WAKEUPENABLE_WKEN, ®s->wakeupenable); 433 } 434 435 static void _omap3_spi_claim_bus(struct omap3_spi_priv *priv) 436 { 437 unsigned int conf; 438 439 spi_reset(priv->regs); 440 441 /* 442 * setup when switching from (reset default) slave mode 443 * to single-channel master mode 444 */ 445 conf = readl(&priv->regs->modulctrl); 446 conf &= ~(OMAP3_MCSPI_MODULCTRL_STEST | OMAP3_MCSPI_MODULCTRL_MS); 447 conf |= OMAP3_MCSPI_MODULCTRL_SINGLE; 448 449 writel(conf, &priv->regs->modulctrl); 450 451 _omap3_spi_set_mode(priv); 452 _omap3_spi_set_speed(priv); 453 } 454 455 #ifndef CONFIG_DM_SPI 456 457 struct omap3_spi_slave { 458 struct spi_slave slave; 459 struct omap3_spi_priv spi_priv; 460 }; 461 462 struct omap3_spi_priv *priv; 463 464 static inline struct omap3_spi_slave *to_omap3_spi(struct spi_slave *slave) 465 { 466 return container_of(slave, struct omap3_spi_slave, slave); 467 } 468 469 void spi_init(void) 470 { 471 /* do nothing */ 472 } 473 474 void spi_free_slave(struct spi_slave *slave) 475 { 476 struct omap3_spi_slave *ds = to_omap3_spi(slave); 477 478 free(ds); 479 } 480 481 int spi_claim_bus(struct spi_slave *slave) 482 { 483 _omap3_spi_claim_bus(priv); 484 _omap3_spi_set_wordlen(priv); 485 _omap3_spi_set_mode(priv); 486 _omap3_spi_set_speed(priv); 487 488 return 0; 489 } 490 491 void spi_release_bus(struct spi_slave *slave) 492 { 493 /* Reset the SPI hardware */ 494 spi_reset(priv->regs); 495 } 496 497 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 498 unsigned int max_hz, unsigned int mode) 499 { 500 struct omap3_spi_slave *ds; 501 struct mcspi *regs; 502 503 /* 504 * OMAP3 McSPI (MultiChannel SPI) has 4 busses (modules) 505 * with different number of chip selects (CS, channels): 506 * McSPI1 has 4 CS (bus 0, cs 0 - 3) 507 * McSPI2 has 2 CS (bus 1, cs 0 - 1) 508 * McSPI3 has 2 CS (bus 2, cs 0 - 1) 509 * McSPI4 has 1 CS (bus 3, cs 0) 510 */ 511 512 switch (bus) { 513 case 0: 514 regs = (struct mcspi *)OMAP3_MCSPI1_BASE; 515 break; 516 #ifdef OMAP3_MCSPI2_BASE 517 case 1: 518 regs = (struct mcspi *)OMAP3_MCSPI2_BASE; 519 break; 520 #endif 521 #ifdef OMAP3_MCSPI3_BASE 522 case 2: 523 regs = (struct mcspi *)OMAP3_MCSPI3_BASE; 524 break; 525 #endif 526 #ifdef OMAP3_MCSPI4_BASE 527 case 3: 528 regs = (struct mcspi *)OMAP3_MCSPI4_BASE; 529 break; 530 #endif 531 default: 532 printf("SPI error: unsupported bus %i. Supported busses 0 - 3\n", bus); 533 return NULL; 534 } 535 536 if (((bus == 0) && (cs > 3)) || 537 ((bus == 1) && (cs > 1)) || 538 ((bus == 2) && (cs > 1)) || 539 ((bus == 3) && (cs > 0))) { 540 printf("SPI error: unsupported chip select %i on bus %i\n", cs, bus); 541 return NULL; 542 } 543 544 if (max_hz > OMAP3_MCSPI_MAX_FREQ) { 545 printf("SPI error: unsupported frequency %i Hz. Max frequency is 48 Mhz\n", max_hz); 546 return NULL; 547 } 548 549 if (mode > SPI_MODE_3) { 550 printf("SPI error: unsupported SPI mode %i\n", mode); 551 return NULL; 552 } 553 554 ds = spi_alloc_slave(struct omap3_spi_slave, bus, cs); 555 if (!ds) { 556 printf("SPI error: malloc of SPI structure failed\n"); 557 return NULL; 558 } 559 560 priv = &ds->spi_priv; 561 562 priv->regs = regs; 563 priv->cs = cs; 564 priv->freq = max_hz; 565 priv->mode = mode; 566 priv->wordlen = ds->slave.wordlen; 567 #ifdef CONFIG_OMAP3_SPI_D0_D1_SWAPPED 568 priv->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN; 569 #endif 570 571 return &ds->slave; 572 } 573 574 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, 575 const void *dout, void *din, unsigned long flags) 576 { return _spi_xfer(priv, bitlen, dout, din, flags); } 577 578 #else 579 580 static int omap3_spi_claim_bus(struct udevice *dev) 581 { 582 struct udevice *bus = dev->parent; 583 struct omap3_spi_priv *priv = dev_get_priv(bus); 584 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 585 586 priv->cs = slave_plat->cs; 587 priv->mode = slave_plat->mode; 588 priv->freq = slave_plat->max_hz; 589 _omap3_spi_claim_bus(priv); 590 591 return 0; 592 } 593 594 static int omap3_spi_release_bus(struct udevice *dev) 595 { 596 struct udevice *bus = dev->parent; 597 struct omap3_spi_priv *priv = dev_get_priv(bus); 598 599 /* Reset the SPI hardware */ 600 spi_reset(priv->regs); 601 602 return 0; 603 } 604 605 static int omap3_spi_set_wordlen(struct udevice *dev, unsigned int wordlen) 606 { 607 struct udevice *bus = dev->parent; 608 struct omap3_spi_priv *priv = dev_get_priv(bus); 609 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 610 611 priv->cs = slave_plat->cs; 612 priv->wordlen = wordlen; 613 _omap3_spi_set_wordlen(priv); 614 615 return 0; 616 } 617 618 static int omap3_spi_probe(struct udevice *dev) 619 { 620 struct omap3_spi_priv *priv = dev_get_priv(dev); 621 const void *blob = gd->fdt_blob; 622 int node = dev->of_offset; 623 624 priv->regs = (struct mcspi *)dev_get_addr(dev); 625 priv->pin_dir = fdtdec_get_uint(blob, node, "ti,pindir-d0-out-d1-in", 626 MCSPI_PINDIR_D0_IN_D1_OUT); 627 priv->wordlen = SPI_DEFAULT_WORDLEN; 628 return 0; 629 } 630 631 static int omap3_spi_xfer(struct udevice *dev, unsigned int bitlen, 632 const void *dout, void *din, unsigned long flags) 633 { 634 struct udevice *bus = dev->parent; 635 struct omap3_spi_priv *priv = dev_get_priv(bus); 636 637 return _spi_xfer(priv, bitlen, dout, din, flags); 638 } 639 640 static int omap3_spi_set_speed(struct udevice *bus, unsigned int speed) 641 { 642 return 0; 643 } 644 645 static int omap3_spi_set_mode(struct udevice *bus, uint mode) 646 { 647 return 0; 648 } 649 650 static const struct dm_spi_ops omap3_spi_ops = { 651 .claim_bus = omap3_spi_claim_bus, 652 .release_bus = omap3_spi_release_bus, 653 .set_wordlen = omap3_spi_set_wordlen, 654 .xfer = omap3_spi_xfer, 655 .set_speed = omap3_spi_set_speed, 656 .set_mode = omap3_spi_set_mode, 657 /* 658 * cs_info is not needed, since we require all chip selects to be 659 * in the device tree explicitly 660 */ 661 }; 662 663 static const struct udevice_id omap3_spi_ids[] = { 664 { .compatible = "ti,omap2-mcspi" }, 665 { .compatible = "ti,omap4-mcspi" }, 666 { } 667 }; 668 669 U_BOOT_DRIVER(omap3_spi) = { 670 .name = "omap3_spi", 671 .id = UCLASS_SPI, 672 .of_match = omap3_spi_ids, 673 .probe = omap3_spi_probe, 674 .ops = &omap3_spi_ops, 675 .priv_auto_alloc_size = sizeof(struct omap3_spi_priv), 676 .probe = omap3_spi_probe, 677 }; 678 #endif 679