1 /* 2 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de> 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 * 19 */ 20 21 #include <common.h> 22 #include <malloc.h> 23 #include <spi.h> 24 #include <asm/errno.h> 25 #include <asm/io.h> 26 #include <mxc_gpio.h> 27 28 #ifdef CONFIG_MX27 29 /* i.MX27 has a completely wrong register layout and register definitions in the 30 * datasheet, the correct one is in the Freescale's Linux driver */ 31 32 #error "i.MX27 CSPI not supported due to drastic differences in register definisions" \ 33 "See linux mxc_spi driver from Freescale for details." 34 35 #elif defined(CONFIG_MX31) 36 37 #include <asm/arch/mx31.h> 38 39 #define MXC_CSPIRXDATA 0x00 40 #define MXC_CSPITXDATA 0x04 41 #define MXC_CSPICTRL 0x08 42 #define MXC_CSPIINT 0x0C 43 #define MXC_CSPIDMA 0x10 44 #define MXC_CSPISTAT 0x14 45 #define MXC_CSPIPERIOD 0x18 46 #define MXC_CSPITEST 0x1C 47 #define MXC_CSPIRESET 0x00 48 49 #define MXC_CSPICTRL_EN (1 << 0) 50 #define MXC_CSPICTRL_MODE (1 << 1) 51 #define MXC_CSPICTRL_XCH (1 << 2) 52 #define MXC_CSPICTRL_SMC (1 << 3) 53 #define MXC_CSPICTRL_POL (1 << 4) 54 #define MXC_CSPICTRL_PHA (1 << 5) 55 #define MXC_CSPICTRL_SSCTL (1 << 6) 56 #define MXC_CSPICTRL_SSPOL (1 << 7) 57 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24) 58 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8) 59 #define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16) 60 #define MXC_CSPICTRL_TC (1 << 8) 61 #define MXC_CSPICTRL_RXOVF (1 << 6) 62 #define MXC_CSPICTRL_MAXBITS 0x1f 63 64 #define MXC_CSPIPERIOD_32KHZ (1 << 15) 65 66 static unsigned long spi_bases[] = { 67 0x43fa4000, 68 0x50010000, 69 0x53f84000, 70 }; 71 72 #elif defined(CONFIG_MX51) 73 #include <asm/arch/imx-regs.h> 74 #include <asm/arch/clock.h> 75 76 #define MXC_CSPIRXDATA 0x00 77 #define MXC_CSPITXDATA 0x04 78 #define MXC_CSPICTRL 0x08 79 #define MXC_CSPICON 0x0C 80 #define MXC_CSPIINT 0x10 81 #define MXC_CSPIDMA 0x14 82 #define MXC_CSPISTAT 0x18 83 #define MXC_CSPIPERIOD 0x1C 84 #define MXC_CSPIRESET 0x00 85 #define MXC_CSPICTRL_EN (1 << 0) 86 #define MXC_CSPICTRL_MODE (1 << 1) 87 #define MXC_CSPICTRL_XCH (1 << 2) 88 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) 89 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) 90 #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) 91 #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) 92 #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) 93 #define MXC_CSPICTRL_MAXBITS 0xfff 94 #define MXC_CSPICTRL_TC (1 << 7) 95 #define MXC_CSPICTRL_RXOVF (1 << 6) 96 97 #define MXC_CSPIPERIOD_32KHZ (1 << 15) 98 99 /* Bit position inside CTRL register to be associated with SS */ 100 #define MXC_CSPICTRL_CHAN 18 101 102 /* Bit position inside CON register to be associated with SS */ 103 #define MXC_CSPICON_POL 4 104 #define MXC_CSPICON_PHA 0 105 #define MXC_CSPICON_SSPOL 12 106 107 static unsigned long spi_bases[] = { 108 CSPI1_BASE_ADDR, 109 CSPI2_BASE_ADDR, 110 CSPI3_BASE_ADDR, 111 }; 112 #else 113 #error "Unsupported architecture" 114 #endif 115 116 #define OUT MXC_GPIO_DIRECTION_OUT 117 118 struct mxc_spi_slave { 119 struct spi_slave slave; 120 unsigned long base; 121 u32 ctrl_reg; 122 #if defined(CONFIG_MX51) 123 u32 cfg_reg; 124 #endif 125 int gpio; 126 int ss_pol; 127 }; 128 129 static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave) 130 { 131 return container_of(slave, struct mxc_spi_slave, slave); 132 } 133 134 static inline u32 reg_read(unsigned long addr) 135 { 136 return *(volatile unsigned long*)addr; 137 } 138 139 static inline void reg_write(unsigned long addr, u32 val) 140 { 141 *(volatile unsigned long*)addr = val; 142 } 143 144 void spi_cs_activate(struct spi_slave *slave) 145 { 146 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 147 if (mxcs->gpio > 0) 148 mxc_gpio_set(mxcs->gpio, mxcs->ss_pol); 149 } 150 151 void spi_cs_deactivate(struct spi_slave *slave) 152 { 153 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 154 if (mxcs->gpio > 0) 155 mxc_gpio_set(mxcs->gpio, 156 !(mxcs->ss_pol)); 157 } 158 159 #ifdef CONFIG_MX51 160 static s32 spi_cfg(struct mxc_spi_slave *mxcs, unsigned int cs, 161 unsigned int max_hz, unsigned int mode) 162 { 163 u32 clk_src = mxc_get_clock(MXC_CSPI_CLK); 164 s32 pre_div = 0, post_div = 0, i, reg_ctrl, reg_config; 165 u32 ss_pol = 0, sclkpol = 0, sclkpha = 0; 166 167 if (max_hz == 0) { 168 printf("Error: desired clock is 0\n"); 169 return -1; 170 } 171 172 reg_ctrl = reg_read(mxcs->base + MXC_CSPICTRL); 173 174 /* Reset spi */ 175 reg_write(mxcs->base + MXC_CSPICTRL, 0); 176 reg_write(mxcs->base + MXC_CSPICTRL, (reg_ctrl | 0x1)); 177 178 /* 179 * The following computation is taken directly from Freescale's code. 180 */ 181 if (clk_src > max_hz) { 182 pre_div = clk_src / max_hz; 183 if (pre_div > 16) { 184 post_div = pre_div / 16; 185 pre_div = 15; 186 } 187 if (post_div != 0) { 188 for (i = 0; i < 16; i++) { 189 if ((1 << i) >= post_div) 190 break; 191 } 192 if (i == 16) { 193 printf("Error: no divider for the freq: %d\n", 194 max_hz); 195 return -1; 196 } 197 post_div = i; 198 } 199 } 200 201 debug("pre_div = %d, post_div=%d\n", pre_div, post_div); 202 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) | 203 MXC_CSPICTRL_SELCHAN(cs); 204 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) | 205 MXC_CSPICTRL_PREDIV(pre_div); 206 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) | 207 MXC_CSPICTRL_POSTDIV(post_div); 208 209 /* always set to master mode */ 210 reg_ctrl |= 1 << (cs + 4); 211 212 /* We need to disable SPI before changing registers */ 213 reg_ctrl &= ~MXC_CSPICTRL_EN; 214 215 if (mode & SPI_CS_HIGH) 216 ss_pol = 1; 217 218 if (!(mode & SPI_CPOL)) 219 sclkpol = 1; 220 221 if (mode & SPI_CPHA) 222 sclkpha = 1; 223 224 reg_config = reg_read(mxcs->base + MXC_CSPICON); 225 226 /* 227 * Configuration register setup 228 * The MX51 has support different setup for each SS 229 */ 230 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) | 231 (ss_pol << (cs + MXC_CSPICON_SSPOL)); 232 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) | 233 (sclkpol << (cs + MXC_CSPICON_POL)); 234 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) | 235 (sclkpha << (cs + MXC_CSPICON_PHA)); 236 237 debug("reg_ctrl = 0x%x\n", reg_ctrl); 238 reg_write(mxcs->base + MXC_CSPICTRL, reg_ctrl); 239 debug("reg_config = 0x%x\n", reg_config); 240 reg_write(mxcs->base + MXC_CSPICON, reg_config); 241 242 /* save config register and control register */ 243 mxcs->ctrl_reg = reg_ctrl; 244 mxcs->cfg_reg = reg_config; 245 246 /* clear interrupt reg */ 247 reg_write(mxcs->base + MXC_CSPIINT, 0); 248 reg_write(mxcs->base + MXC_CSPISTAT, 249 MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); 250 251 return 0; 252 } 253 #endif 254 255 static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen, 256 unsigned long flags) 257 { 258 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 259 260 if (flags & SPI_XFER_BEGIN) 261 spi_cs_activate(slave); 262 263 mxcs->ctrl_reg = (mxcs->ctrl_reg & 264 ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) | 265 MXC_CSPICTRL_BITCOUNT(bitlen - 1); 266 267 reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg | MXC_CSPICTRL_EN); 268 #ifdef CONFIG_MX51 269 reg_write(mxcs->base + MXC_CSPICON, mxcs->cfg_reg); 270 #endif 271 272 /* Clear interrupt register */ 273 reg_write(mxcs->base + MXC_CSPISTAT, 274 MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); 275 276 debug("Sending SPI 0x%x\n", data); 277 reg_write(mxcs->base + MXC_CSPITXDATA, data); 278 279 /* FIFO is written, now starts the transfer setting the XCH bit */ 280 reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg | 281 MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH); 282 283 /* Wait until the TC (Transfer completed) bit is set */ 284 while ((reg_read(mxcs->base + MXC_CSPISTAT) & MXC_CSPICTRL_TC) == 0) 285 ; 286 287 /* Transfer completed, clear any pending request */ 288 reg_write(mxcs->base + MXC_CSPISTAT, 289 MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); 290 291 data = reg_read(mxcs->base + MXC_CSPIRXDATA); 292 debug("SPI Rx: 0x%x\n", data); 293 294 if (flags & SPI_XFER_END) 295 spi_cs_deactivate(slave); 296 297 return data; 298 299 } 300 301 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, 302 void *din, unsigned long flags) 303 { 304 int n_blks = (bitlen + 31) / 32; 305 u32 *out_l, *in_l; 306 int i; 307 308 if ((int)dout & 3 || (int)din & 3) { 309 printf("Error: unaligned buffers in: %p, out: %p\n", din, dout); 310 return 1; 311 } 312 313 /* This driver is currently partly broken, alert the user */ 314 if (bitlen > 16 && (bitlen % 32)) { 315 printf("Error: SPI transfer with bitlen=%d is broken.\n", 316 bitlen); 317 return 1; 318 } 319 320 for (i = 0, in_l = (u32 *)din, out_l = (u32 *)dout; 321 i < n_blks; 322 i++, in_l++, out_l++, bitlen -= 32) { 323 u32 data = spi_xchg_single(slave, *out_l, bitlen, flags); 324 325 /* Check if we're only transfering 8 or 16 bits */ 326 if (!i) { 327 if (bitlen < 9) 328 *(u8 *)din = data; 329 else if (bitlen < 17) 330 *(u16 *)din = data; 331 else 332 *in_l = data; 333 } 334 } 335 336 return 0; 337 } 338 339 void spi_init(void) 340 { 341 } 342 343 static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs) 344 { 345 int ret; 346 347 /* 348 * Some SPI devices require active chip-select over multiple 349 * transactions, we achieve this using a GPIO. Still, the SPI 350 * controller has to be configured to use one of its own chipselects. 351 * To use this feature you have to call spi_setup_slave() with 352 * cs = internal_cs | (gpio << 8), and you have to use some unused 353 * on this SPI controller cs between 0 and 3. 354 */ 355 if (cs > 3) { 356 mxcs->gpio = cs >> 8; 357 cs &= 3; 358 ret = mxc_gpio_direction(mxcs->gpio, OUT); 359 if (ret) { 360 printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio); 361 return -EINVAL; 362 } 363 } else { 364 mxcs->gpio = -1; 365 } 366 367 return cs; 368 } 369 370 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 371 unsigned int max_hz, unsigned int mode) 372 { 373 unsigned int ctrl_reg; 374 struct mxc_spi_slave *mxcs; 375 int ret; 376 377 if (bus >= ARRAY_SIZE(spi_bases)) 378 return NULL; 379 380 mxcs = malloc(sizeof(struct mxc_spi_slave)); 381 if (!mxcs) 382 return NULL; 383 384 ret = decode_cs(mxcs, cs); 385 if (ret < 0) { 386 free(mxcs); 387 return NULL; 388 } 389 390 cs = ret; 391 392 mxcs->slave.bus = bus; 393 mxcs->slave.cs = cs; 394 mxcs->base = spi_bases[bus]; 395 mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0; 396 397 #ifdef CONFIG_MX51 398 /* Can be used for i.MX31 too ? */ 399 ctrl_reg = 0; 400 ret = spi_cfg(mxcs, cs, max_hz, mode); 401 if (ret) { 402 printf("mxc_spi: cannot setup SPI controller\n"); 403 free(mxcs); 404 return NULL; 405 } 406 #else 407 ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) | 408 MXC_CSPICTRL_BITCOUNT(31) | 409 MXC_CSPICTRL_DATARATE(7) | /* FIXME: calculate data rate */ 410 MXC_CSPICTRL_EN | 411 MXC_CSPICTRL_MODE; 412 413 if (mode & SPI_CPHA) 414 ctrl_reg |= MXC_CSPICTRL_PHA; 415 if (!(mode & SPI_CPOL)) 416 ctrl_reg |= MXC_CSPICTRL_POL; 417 if (mode & SPI_CS_HIGH) 418 ctrl_reg |= MXC_CSPICTRL_SSPOL; 419 mxcs->ctrl_reg = ctrl_reg; 420 #endif 421 return &mxcs->slave; 422 } 423 424 void spi_free_slave(struct spi_slave *slave) 425 { 426 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 427 428 free(mxcs); 429 } 430 431 int spi_claim_bus(struct spi_slave *slave) 432 { 433 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 434 435 reg_write(mxcs->base + MXC_CSPIRESET, 1); 436 udelay(1); 437 reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg); 438 reg_write(mxcs->base + MXC_CSPIPERIOD, 439 MXC_CSPIPERIOD_32KHZ); 440 reg_write(mxcs->base + MXC_CSPIINT, 0); 441 442 return 0; 443 } 444 445 void spi_release_bus(struct spi_slave *slave) 446 { 447 /* TODO: Shut the controller down */ 448 } 449