1 /* 2 * Copyright 2013-2014 Freescale Semiconductor, Inc. 3 * 4 * Freescale Quad Serial Peripheral Interface (QSPI) driver 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <malloc.h> 11 #include <spi.h> 12 #include <asm/io.h> 13 #include <linux/sizes.h> 14 #include "fsl_qspi.h" 15 16 #define RX_BUFFER_SIZE 0x80 17 #ifdef CONFIG_MX6SX 18 #define TX_BUFFER_SIZE 0x200 19 #else 20 #define TX_BUFFER_SIZE 0x40 21 #endif 22 23 #define OFFSET_BITS_MASK 0x00ffffff 24 25 #define FLASH_STATUS_WEL 0x02 26 27 /* SEQID */ 28 #define SEQID_WREN 1 29 #define SEQID_FAST_READ 2 30 #define SEQID_RDSR 3 31 #define SEQID_SE 4 32 #define SEQID_CHIP_ERASE 5 33 #define SEQID_PP 6 34 #define SEQID_RDID 7 35 36 /* QSPI CMD */ 37 #define QSPI_CMD_PP 0x02 /* Page program (up to 256 bytes) */ 38 #define QSPI_CMD_RDSR 0x05 /* Read status register */ 39 #define QSPI_CMD_WREN 0x06 /* Write enable */ 40 #define QSPI_CMD_FAST_READ 0x0b /* Read data bytes (high frequency) */ 41 #define QSPI_CMD_CHIP_ERASE 0xc7 /* Erase whole flash chip */ 42 #define QSPI_CMD_SE 0xd8 /* Sector erase (usually 64KiB) */ 43 #define QSPI_CMD_RDID 0x9f /* Read JEDEC ID */ 44 45 /* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */ 46 #define QSPI_CMD_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */ 47 #define QSPI_CMD_PP_4B 0x12 /* Page program (up to 256 bytes) */ 48 #define QSPI_CMD_SE_4B 0xdc /* Sector erase (usually 64KiB) */ 49 50 #ifdef CONFIG_SYS_FSL_QSPI_LE 51 #define qspi_read32 in_le32 52 #define qspi_write32 out_le32 53 #elif defined(CONFIG_SYS_FSL_QSPI_BE) 54 #define qspi_read32 in_be32 55 #define qspi_write32 out_be32 56 #endif 57 58 static unsigned long spi_bases[] = { 59 QSPI0_BASE_ADDR, 60 #ifdef CONFIG_MX6SX 61 QSPI1_BASE_ADDR, 62 #endif 63 }; 64 65 static unsigned long amba_bases[] = { 66 QSPI0_AMBA_BASE, 67 #ifdef CONFIG_MX6SX 68 QSPI1_AMBA_BASE, 69 #endif 70 }; 71 72 struct fsl_qspi { 73 struct spi_slave slave; 74 unsigned long reg_base; 75 unsigned long amba_base; 76 u32 sf_addr; 77 u8 cur_seqid; 78 }; 79 80 /* QSPI support swapping the flash read/write data 81 * in hardware for LS102xA, but not for VF610 */ 82 static inline u32 qspi_endian_xchg(u32 data) 83 { 84 #ifdef CONFIG_VF610 85 return swab32(data); 86 #else 87 return data; 88 #endif 89 } 90 91 static inline struct fsl_qspi *to_qspi_spi(struct spi_slave *slave) 92 { 93 return container_of(slave, struct fsl_qspi, slave); 94 } 95 96 static void qspi_set_lut(struct fsl_qspi *qspi) 97 { 98 struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base; 99 u32 lut_base; 100 101 /* Unlock the LUT */ 102 qspi_write32(®s->lutkey, LUT_KEY_VALUE); 103 qspi_write32(®s->lckcr, QSPI_LCKCR_UNLOCK); 104 105 /* Write Enable */ 106 lut_base = SEQID_WREN * 4; 107 qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_WREN) | 108 PAD0(LUT_PAD1) | INSTR0(LUT_CMD)); 109 qspi_write32(®s->lut[lut_base + 1], 0); 110 qspi_write32(®s->lut[lut_base + 2], 0); 111 qspi_write32(®s->lut[lut_base + 3], 0); 112 113 /* Fast Read */ 114 lut_base = SEQID_FAST_READ * 4; 115 if (FSL_QSPI_FLASH_SIZE <= SZ_16M) 116 qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_FAST_READ) | 117 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | 118 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); 119 else 120 qspi_write32(®s->lut[lut_base], 121 OPRND0(QSPI_CMD_FAST_READ_4B) | 122 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | 123 OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) | 124 INSTR1(LUT_ADDR)); 125 qspi_write32(®s->lut[lut_base + 1], OPRND0(8) | PAD0(LUT_PAD1) | 126 INSTR0(LUT_DUMMY) | OPRND1(RX_BUFFER_SIZE) | PAD1(LUT_PAD1) | 127 INSTR1(LUT_READ)); 128 qspi_write32(®s->lut[lut_base + 2], 0); 129 qspi_write32(®s->lut[lut_base + 3], 0); 130 131 /* Read Status */ 132 lut_base = SEQID_RDSR * 4; 133 qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_RDSR) | 134 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | 135 PAD1(LUT_PAD1) | INSTR1(LUT_READ)); 136 qspi_write32(®s->lut[lut_base + 1], 0); 137 qspi_write32(®s->lut[lut_base + 2], 0); 138 qspi_write32(®s->lut[lut_base + 3], 0); 139 140 /* Erase a sector */ 141 lut_base = SEQID_SE * 4; 142 if (FSL_QSPI_FLASH_SIZE <= SZ_16M) 143 qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_SE) | 144 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | 145 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); 146 else 147 qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_SE_4B) | 148 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) | 149 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); 150 qspi_write32(®s->lut[lut_base + 1], 0); 151 qspi_write32(®s->lut[lut_base + 2], 0); 152 qspi_write32(®s->lut[lut_base + 3], 0); 153 154 /* Erase the whole chip */ 155 lut_base = SEQID_CHIP_ERASE * 4; 156 qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_CHIP_ERASE) | 157 PAD0(LUT_PAD1) | INSTR0(LUT_CMD)); 158 qspi_write32(®s->lut[lut_base + 1], 0); 159 qspi_write32(®s->lut[lut_base + 2], 0); 160 qspi_write32(®s->lut[lut_base + 3], 0); 161 162 /* Page Program */ 163 lut_base = SEQID_PP * 4; 164 if (FSL_QSPI_FLASH_SIZE <= SZ_16M) 165 qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_PP) | 166 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | 167 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); 168 else 169 qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_PP_4B) | 170 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) | 171 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); 172 #ifdef CONFIG_MX6SX 173 /* 174 * To MX6SX, OPRND0(TX_BUFFER_SIZE) can not work correctly. 175 * So, Use IDATSZ in IPCR to determine the size and here set 0. 176 */ 177 qspi_write32(®s->lut[lut_base + 1], OPRND0(0) | 178 PAD0(LUT_PAD1) | INSTR0(LUT_WRITE)); 179 #else 180 qspi_write32(®s->lut[lut_base + 1], OPRND0(TX_BUFFER_SIZE) | 181 PAD0(LUT_PAD1) | INSTR0(LUT_WRITE)); 182 #endif 183 qspi_write32(®s->lut[lut_base + 2], 0); 184 qspi_write32(®s->lut[lut_base + 3], 0); 185 186 /* READ ID */ 187 lut_base = SEQID_RDID * 4; 188 qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_RDID) | 189 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(8) | 190 PAD1(LUT_PAD1) | INSTR1(LUT_READ)); 191 qspi_write32(®s->lut[lut_base + 1], 0); 192 qspi_write32(®s->lut[lut_base + 2], 0); 193 qspi_write32(®s->lut[lut_base + 3], 0); 194 195 /* Lock the LUT */ 196 qspi_write32(®s->lutkey, LUT_KEY_VALUE); 197 qspi_write32(®s->lckcr, QSPI_LCKCR_LOCK); 198 } 199 200 void spi_init() 201 { 202 /* do nothing */ 203 } 204 205 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 206 unsigned int max_hz, unsigned int mode) 207 { 208 struct fsl_qspi *qspi; 209 struct fsl_qspi_regs *regs; 210 u32 reg_val, smpr_val; 211 u32 total_size, seq_id; 212 213 if (bus >= ARRAY_SIZE(spi_bases)) 214 return NULL; 215 216 if (cs >= FSL_QSPI_FLASH_NUM) 217 return NULL; 218 219 qspi = spi_alloc_slave(struct fsl_qspi, bus, cs); 220 if (!qspi) 221 return NULL; 222 223 qspi->reg_base = spi_bases[bus]; 224 /* 225 * According cs, use different amba_base to choose the 226 * corresponding flash devices. 227 * 228 * If not, only one flash device is used even if passing 229 * different cs using `sf probe` 230 */ 231 qspi->amba_base = amba_bases[bus] + cs * FSL_QSPI_FLASH_SIZE; 232 233 qspi->slave.max_write_size = TX_BUFFER_SIZE; 234 235 regs = (struct fsl_qspi_regs *)qspi->reg_base; 236 qspi_write32(®s->mcr, QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK); 237 238 smpr_val = qspi_read32(®s->smpr); 239 qspi_write32(®s->smpr, smpr_val & ~(QSPI_SMPR_FSDLY_MASK | 240 QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK)); 241 qspi_write32(®s->mcr, QSPI_MCR_RESERVED_MASK); 242 243 total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM; 244 /* 245 * Any read access to non-implemented addresses will provide 246 * undefined results. 247 * 248 * In case single die flash devices, TOP_ADDR_MEMA2 and 249 * TOP_ADDR_MEMB2 should be initialized/programmed to 250 * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect, 251 * setting the size of these devices to 0. This would ensure 252 * that the complete memory map is assigned to only one flash device. 253 */ 254 qspi_write32(®s->sfa1ad, FSL_QSPI_FLASH_SIZE | amba_bases[bus]); 255 qspi_write32(®s->sfa2ad, FSL_QSPI_FLASH_SIZE | amba_bases[bus]); 256 qspi_write32(®s->sfb1ad, total_size | amba_bases[bus]); 257 qspi_write32(®s->sfb2ad, total_size | amba_bases[bus]); 258 259 qspi_set_lut(qspi); 260 261 smpr_val = qspi_read32(®s->smpr); 262 smpr_val &= ~QSPI_SMPR_DDRSMP_MASK; 263 qspi_write32(®s->smpr, smpr_val); 264 qspi_write32(®s->mcr, QSPI_MCR_RESERVED_MASK); 265 266 seq_id = 0; 267 reg_val = qspi_read32(®s->bfgencr); 268 reg_val &= ~QSPI_BFGENCR_SEQID_MASK; 269 reg_val |= (seq_id << QSPI_BFGENCR_SEQID_SHIFT); 270 reg_val &= ~QSPI_BFGENCR_PAR_EN_MASK; 271 qspi_write32(®s->bfgencr, reg_val); 272 273 return &qspi->slave; 274 } 275 276 void spi_free_slave(struct spi_slave *slave) 277 { 278 struct fsl_qspi *qspi = to_qspi_spi(slave); 279 280 free(qspi); 281 } 282 283 int spi_claim_bus(struct spi_slave *slave) 284 { 285 return 0; 286 } 287 288 static void qspi_op_rdid(struct fsl_qspi *qspi, u32 *rxbuf, u32 len) 289 { 290 struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base; 291 u32 mcr_reg, rbsr_reg, data; 292 int i, size; 293 294 mcr_reg = qspi_read32(®s->mcr); 295 qspi_write32(®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | 296 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); 297 qspi_write32(®s->rbct, QSPI_RBCT_RXBRD_USEIPS); 298 299 qspi_write32(®s->sfar, qspi->amba_base); 300 301 qspi_write32(®s->ipcr, (SEQID_RDID << QSPI_IPCR_SEQID_SHIFT) | 0); 302 while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK) 303 ; 304 305 i = 0; 306 size = len; 307 while ((RX_BUFFER_SIZE >= size) && (size > 0)) { 308 rbsr_reg = qspi_read32(®s->rbsr); 309 if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) { 310 data = qspi_read32(®s->rbdr[i]); 311 data = qspi_endian_xchg(data); 312 memcpy(rxbuf, &data, 4); 313 rxbuf++; 314 size -= 4; 315 i++; 316 } 317 } 318 319 qspi_write32(®s->mcr, mcr_reg); 320 } 321 322 static void qspi_op_read(struct fsl_qspi *qspi, u32 *rxbuf, u32 len) 323 { 324 struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base; 325 u32 mcr_reg, data; 326 int i, size; 327 u32 to_or_from; 328 329 mcr_reg = qspi_read32(®s->mcr); 330 qspi_write32(®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | 331 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); 332 qspi_write32(®s->rbct, QSPI_RBCT_RXBRD_USEIPS); 333 334 to_or_from = qspi->sf_addr + qspi->amba_base; 335 336 while (len > 0) { 337 qspi_write32(®s->sfar, to_or_from); 338 339 size = (len > RX_BUFFER_SIZE) ? 340 RX_BUFFER_SIZE : len; 341 342 qspi_write32(®s->ipcr, 343 (SEQID_FAST_READ << QSPI_IPCR_SEQID_SHIFT) | size); 344 while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK) 345 ; 346 347 to_or_from += size; 348 len -= size; 349 350 i = 0; 351 while ((RX_BUFFER_SIZE >= size) && (size > 0)) { 352 data = qspi_read32(®s->rbdr[i]); 353 data = qspi_endian_xchg(data); 354 memcpy(rxbuf, &data, 4); 355 rxbuf++; 356 size -= 4; 357 i++; 358 } 359 qspi_write32(®s->mcr, qspi_read32(®s->mcr) | 360 QSPI_MCR_CLR_RXF_MASK); 361 } 362 363 qspi_write32(®s->mcr, mcr_reg); 364 } 365 366 static void qspi_op_pp(struct fsl_qspi *qspi, u32 *txbuf, u32 len) 367 { 368 struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base; 369 u32 mcr_reg, data, reg, status_reg; 370 int i, size, tx_size; 371 u32 to_or_from = 0; 372 373 mcr_reg = qspi_read32(®s->mcr); 374 qspi_write32(®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | 375 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); 376 qspi_write32(®s->rbct, QSPI_RBCT_RXBRD_USEIPS); 377 378 status_reg = 0; 379 while ((status_reg & FLASH_STATUS_WEL) != FLASH_STATUS_WEL) { 380 qspi_write32(®s->ipcr, 381 (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0); 382 while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK) 383 ; 384 385 qspi_write32(®s->ipcr, 386 (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 1); 387 while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK) 388 ; 389 390 reg = qspi_read32(®s->rbsr); 391 if (reg & QSPI_RBSR_RDBFL_MASK) { 392 status_reg = qspi_read32(®s->rbdr[0]); 393 status_reg = qspi_endian_xchg(status_reg); 394 } 395 qspi_write32(®s->mcr, 396 qspi_read32(®s->mcr) | QSPI_MCR_CLR_RXF_MASK); 397 } 398 399 to_or_from = qspi->sf_addr + qspi->amba_base; 400 qspi_write32(®s->sfar, to_or_from); 401 402 tx_size = (len > TX_BUFFER_SIZE) ? 403 TX_BUFFER_SIZE : len; 404 405 size = (tx_size + 3) / 4; 406 407 for (i = 0; i < size; i++) { 408 data = qspi_endian_xchg(*txbuf); 409 qspi_write32(®s->tbdr, data); 410 txbuf++; 411 } 412 413 qspi_write32(®s->ipcr, 414 (SEQID_PP << QSPI_IPCR_SEQID_SHIFT) | tx_size); 415 while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK) 416 ; 417 418 qspi_write32(®s->mcr, mcr_reg); 419 } 420 421 static void qspi_op_rdsr(struct fsl_qspi *qspi, u32 *rxbuf) 422 { 423 struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base; 424 u32 mcr_reg, reg, data; 425 426 mcr_reg = qspi_read32(®s->mcr); 427 qspi_write32(®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | 428 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); 429 qspi_write32(®s->rbct, QSPI_RBCT_RXBRD_USEIPS); 430 431 qspi_write32(®s->sfar, qspi->amba_base); 432 433 qspi_write32(®s->ipcr, 434 (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 0); 435 while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK) 436 ; 437 438 while (1) { 439 reg = qspi_read32(®s->rbsr); 440 if (reg & QSPI_RBSR_RDBFL_MASK) { 441 data = qspi_read32(®s->rbdr[0]); 442 data = qspi_endian_xchg(data); 443 memcpy(rxbuf, &data, 4); 444 qspi_write32(®s->mcr, qspi_read32(®s->mcr) | 445 QSPI_MCR_CLR_RXF_MASK); 446 break; 447 } 448 } 449 450 qspi_write32(®s->mcr, mcr_reg); 451 } 452 453 static void qspi_op_se(struct fsl_qspi *qspi) 454 { 455 struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base; 456 u32 mcr_reg; 457 u32 to_or_from = 0; 458 459 mcr_reg = qspi_read32(®s->mcr); 460 qspi_write32(®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | 461 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); 462 qspi_write32(®s->rbct, QSPI_RBCT_RXBRD_USEIPS); 463 464 to_or_from = qspi->sf_addr + qspi->amba_base; 465 qspi_write32(®s->sfar, to_or_from); 466 467 qspi_write32(®s->ipcr, 468 (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0); 469 while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK) 470 ; 471 472 qspi_write32(®s->ipcr, 473 (SEQID_SE << QSPI_IPCR_SEQID_SHIFT) | 0); 474 while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK) 475 ; 476 477 qspi_write32(®s->mcr, mcr_reg); 478 } 479 480 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, 481 const void *dout, void *din, unsigned long flags) 482 { 483 struct fsl_qspi *qspi = to_qspi_spi(slave); 484 u32 bytes = DIV_ROUND_UP(bitlen, 8); 485 static u32 pp_sfaddr; 486 u32 txbuf; 487 488 if (dout) { 489 memcpy(&txbuf, dout, 4); 490 qspi->cur_seqid = *(u8 *)dout; 491 492 if (flags == SPI_XFER_END) { 493 qspi->sf_addr = pp_sfaddr; 494 qspi_op_pp(qspi, (u32 *)dout, bytes); 495 return 0; 496 } 497 498 if (qspi->cur_seqid == QSPI_CMD_FAST_READ) { 499 qspi->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK; 500 } else if (qspi->cur_seqid == QSPI_CMD_SE) { 501 qspi->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK; 502 qspi_op_se(qspi); 503 } else if (qspi->cur_seqid == QSPI_CMD_PP) { 504 pp_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK; 505 } 506 } 507 508 if (din) { 509 if (qspi->cur_seqid == QSPI_CMD_FAST_READ) 510 qspi_op_read(qspi, din, bytes); 511 else if (qspi->cur_seqid == QSPI_CMD_RDID) 512 qspi_op_rdid(qspi, din, bytes); 513 else if (qspi->cur_seqid == QSPI_CMD_RDSR) 514 qspi_op_rdsr(qspi, din); 515 } 516 517 return 0; 518 } 519 520 void spi_release_bus(struct spi_slave *slave) 521 { 522 /* Nothing to do */ 523 } 524