1 /* 2 * Designware master SPI core controller driver 3 * 4 * Copyright (C) 2014 Stefan Roese <sr@denx.de> 5 * 6 * Very loosely based on the Linux driver: 7 * drivers/spi/spi-dw.c, which is: 8 * Copyright (c) 2009, Intel Corporation. 9 * 10 * SPDX-License-Identifier: GPL-2.0 11 */ 12 13 #include <common.h> 14 #include <clk.h> 15 #include <dm.h> 16 #include <errno.h> 17 #include <malloc.h> 18 #include <spi.h> 19 #include <fdtdec.h> 20 #include <linux/compat.h> 21 #include <linux/iopoll.h> 22 #include <asm/io.h> 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 /* Register offsets */ 27 #define DW_SPI_CTRL0 0x00 28 #define DW_SPI_CTRL1 0x04 29 #define DW_SPI_SSIENR 0x08 30 #define DW_SPI_MWCR 0x0c 31 #define DW_SPI_SER 0x10 32 #define DW_SPI_BAUDR 0x14 33 #define DW_SPI_TXFLTR 0x18 34 #define DW_SPI_RXFLTR 0x1c 35 #define DW_SPI_TXFLR 0x20 36 #define DW_SPI_RXFLR 0x24 37 #define DW_SPI_SR 0x28 38 #define DW_SPI_IMR 0x2c 39 #define DW_SPI_ISR 0x30 40 #define DW_SPI_RISR 0x34 41 #define DW_SPI_TXOICR 0x38 42 #define DW_SPI_RXOICR 0x3c 43 #define DW_SPI_RXUICR 0x40 44 #define DW_SPI_MSTICR 0x44 45 #define DW_SPI_ICR 0x48 46 #define DW_SPI_DMACR 0x4c 47 #define DW_SPI_DMATDLR 0x50 48 #define DW_SPI_DMARDLR 0x54 49 #define DW_SPI_IDR 0x58 50 #define DW_SPI_VERSION 0x5c 51 #define DW_SPI_DR 0x60 52 53 /* Bit fields in CTRLR0 */ 54 #define SPI_DFS_OFFSET 0 55 56 #define SPI_FRF_OFFSET 4 57 #define SPI_FRF_SPI 0x0 58 #define SPI_FRF_SSP 0x1 59 #define SPI_FRF_MICROWIRE 0x2 60 #define SPI_FRF_RESV 0x3 61 62 #define SPI_MODE_OFFSET 6 63 #define SPI_SCPH_OFFSET 6 64 #define SPI_SCOL_OFFSET 7 65 66 #define SPI_TMOD_OFFSET 8 67 #define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET) 68 #define SPI_TMOD_TR 0x0 /* xmit & recv */ 69 #define SPI_TMOD_TO 0x1 /* xmit only */ 70 #define SPI_TMOD_RO 0x2 /* recv only */ 71 #define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */ 72 73 #define SPI_SLVOE_OFFSET 10 74 #define SPI_SRL_OFFSET 11 75 #define SPI_CFS_OFFSET 12 76 77 /* Bit fields in SR, 7 bits */ 78 #define SR_MASK GENMASK(6, 0) /* cover 7 bits */ 79 #define SR_BUSY BIT(0) 80 #define SR_TF_NOT_FULL BIT(1) 81 #define SR_TF_EMPT BIT(2) 82 #define SR_RF_NOT_EMPT BIT(3) 83 #define SR_RF_FULL BIT(4) 84 #define SR_TX_ERR BIT(5) 85 #define SR_DCOL BIT(6) 86 87 #define RX_TIMEOUT 1000 /* timeout in ms */ 88 89 struct dw_spi_platdata { 90 s32 frequency; /* Default clock frequency, -1 for none */ 91 void __iomem *regs; 92 }; 93 94 struct dw_spi_priv { 95 void __iomem *regs; 96 unsigned int freq; /* Default frequency */ 97 unsigned int mode; 98 struct clk clk; 99 unsigned long bus_clk_rate; 100 101 int bits_per_word; 102 u8 cs; /* chip select pin */ 103 u8 tmode; /* TR/TO/RO/EEPROM */ 104 u8 type; /* SPI/SSP/MicroWire */ 105 int len; 106 107 u32 fifo_len; /* depth of the FIFO buffer */ 108 void *tx; 109 void *tx_end; 110 void *rx; 111 void *rx_end; 112 }; 113 114 static inline u32 dw_readl(struct dw_spi_priv *priv, u32 offset) 115 { 116 return __raw_readl(priv->regs + offset); 117 } 118 119 static inline void dw_writel(struct dw_spi_priv *priv, u32 offset, u32 val) 120 { 121 __raw_writel(val, priv->regs + offset); 122 } 123 124 static inline u16 dw_readw(struct dw_spi_priv *priv, u32 offset) 125 { 126 return __raw_readw(priv->regs + offset); 127 } 128 129 static inline void dw_writew(struct dw_spi_priv *priv, u32 offset, u16 val) 130 { 131 __raw_writew(val, priv->regs + offset); 132 } 133 134 static int dw_spi_ofdata_to_platdata(struct udevice *bus) 135 { 136 struct dw_spi_platdata *plat = bus->platdata; 137 const void *blob = gd->fdt_blob; 138 int node = dev_of_offset(bus); 139 140 plat->regs = (struct dw_spi *)devfdt_get_addr(bus); 141 142 /* Use 500KHz as a suitable default */ 143 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", 144 500000); 145 debug("%s: regs=%p max-frequency=%d\n", __func__, plat->regs, 146 plat->frequency); 147 148 return 0; 149 } 150 151 static inline void spi_enable_chip(struct dw_spi_priv *priv, int enable) 152 { 153 dw_writel(priv, DW_SPI_SSIENR, (enable ? 1 : 0)); 154 } 155 156 /* Restart the controller, disable all interrupts, clean rx fifo */ 157 static void spi_hw_init(struct dw_spi_priv *priv) 158 { 159 spi_enable_chip(priv, 0); 160 dw_writel(priv, DW_SPI_IMR, 0xff); 161 spi_enable_chip(priv, 1); 162 163 /* 164 * Try to detect the FIFO depth if not set by interface driver, 165 * the depth could be from 2 to 256 from HW spec 166 */ 167 if (!priv->fifo_len) { 168 u32 fifo; 169 170 for (fifo = 1; fifo < 256; fifo++) { 171 dw_writew(priv, DW_SPI_TXFLTR, fifo); 172 if (fifo != dw_readw(priv, DW_SPI_TXFLTR)) 173 break; 174 } 175 176 priv->fifo_len = (fifo == 1) ? 0 : fifo; 177 dw_writew(priv, DW_SPI_TXFLTR, 0); 178 } 179 debug("%s: fifo_len=%d\n", __func__, priv->fifo_len); 180 } 181 182 /* 183 * We define dw_spi_get_clk function as 'weak' as some targets 184 * (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) don't use standard clock API 185 * and implement dw_spi_get_clk their own way in their clock manager. 186 */ 187 __weak int dw_spi_get_clk(struct udevice *bus, ulong *rate) 188 { 189 struct dw_spi_priv *priv = dev_get_priv(bus); 190 int ret; 191 192 ret = clk_get_by_index(bus, 0, &priv->clk); 193 if (ret) 194 return ret; 195 196 ret = clk_enable(&priv->clk); 197 if (ret && ret != -ENOSYS && ret != -ENOTSUPP) 198 return ret; 199 200 *rate = clk_get_rate(&priv->clk); 201 if (!*rate) 202 goto err_rate; 203 204 debug("%s: get spi controller clk via device tree: %lu Hz\n", 205 __func__, *rate); 206 207 return 0; 208 209 err_rate: 210 clk_disable(&priv->clk); 211 clk_free(&priv->clk); 212 213 return -EINVAL; 214 } 215 216 static int dw_spi_probe(struct udevice *bus) 217 { 218 struct dw_spi_platdata *plat = dev_get_platdata(bus); 219 struct dw_spi_priv *priv = dev_get_priv(bus); 220 int ret; 221 222 priv->regs = plat->regs; 223 priv->freq = plat->frequency; 224 225 ret = dw_spi_get_clk(bus, &priv->bus_clk_rate); 226 if (ret) 227 return ret; 228 229 /* Currently only bits_per_word == 8 supported */ 230 priv->bits_per_word = 8; 231 232 priv->tmode = 0; /* Tx & Rx */ 233 234 /* Basic HW init */ 235 spi_hw_init(priv); 236 237 return 0; 238 } 239 240 /* Return the max entries we can fill into tx fifo */ 241 static inline u32 tx_max(struct dw_spi_priv *priv) 242 { 243 u32 tx_left, tx_room, rxtx_gap; 244 245 tx_left = (priv->tx_end - priv->tx) / (priv->bits_per_word >> 3); 246 tx_room = priv->fifo_len - dw_readw(priv, DW_SPI_TXFLR); 247 248 /* 249 * Another concern is about the tx/rx mismatch, we 250 * thought about using (priv->fifo_len - rxflr - txflr) as 251 * one maximum value for tx, but it doesn't cover the 252 * data which is out of tx/rx fifo and inside the 253 * shift registers. So a control from sw point of 254 * view is taken. 255 */ 256 rxtx_gap = ((priv->rx_end - priv->rx) - (priv->tx_end - priv->tx)) / 257 (priv->bits_per_word >> 3); 258 259 return min3(tx_left, tx_room, (u32)(priv->fifo_len - rxtx_gap)); 260 } 261 262 /* Return the max entries we should read out of rx fifo */ 263 static inline u32 rx_max(struct dw_spi_priv *priv) 264 { 265 u32 rx_left = (priv->rx_end - priv->rx) / (priv->bits_per_word >> 3); 266 267 return min_t(u32, rx_left, dw_readw(priv, DW_SPI_RXFLR)); 268 } 269 270 static void dw_writer(struct dw_spi_priv *priv) 271 { 272 u32 max = tx_max(priv); 273 u16 txw = 0; 274 275 while (max--) { 276 /* Set the tx word if the transfer's original "tx" is not null */ 277 if (priv->tx_end - priv->len) { 278 if (priv->bits_per_word == 8) 279 txw = *(u8 *)(priv->tx); 280 else 281 txw = *(u16 *)(priv->tx); 282 } 283 dw_writew(priv, DW_SPI_DR, txw); 284 debug("%s: tx=0x%02x\n", __func__, txw); 285 priv->tx += priv->bits_per_word >> 3; 286 } 287 } 288 289 static int dw_reader(struct dw_spi_priv *priv) 290 { 291 unsigned start = get_timer(0); 292 u32 max; 293 u16 rxw; 294 295 /* Wait for rx data to be ready */ 296 while (rx_max(priv) == 0) { 297 if (get_timer(start) > RX_TIMEOUT) 298 return -ETIMEDOUT; 299 } 300 301 max = rx_max(priv); 302 303 while (max--) { 304 rxw = dw_readw(priv, DW_SPI_DR); 305 debug("%s: rx=0x%02x\n", __func__, rxw); 306 307 /* 308 * Care about rx only if the transfer's original "rx" is 309 * not null 310 */ 311 if (priv->rx_end - priv->len) { 312 if (priv->bits_per_word == 8) 313 *(u8 *)(priv->rx) = rxw; 314 else 315 *(u16 *)(priv->rx) = rxw; 316 } 317 priv->rx += priv->bits_per_word >> 3; 318 } 319 320 return 0; 321 } 322 323 static int poll_transfer(struct dw_spi_priv *priv) 324 { 325 int ret; 326 327 do { 328 dw_writer(priv); 329 ret = dw_reader(priv); 330 if (ret < 0) 331 return ret; 332 } while (priv->rx_end > priv->rx); 333 334 return 0; 335 } 336 337 static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen, 338 const void *dout, void *din, unsigned long flags) 339 { 340 struct udevice *bus = dev->parent; 341 struct dw_spi_priv *priv = dev_get_priv(bus); 342 const u8 *tx = dout; 343 u8 *rx = din; 344 int ret = 0; 345 u32 cr0 = 0; 346 u32 val; 347 u32 cs; 348 349 /* spi core configured to do 8 bit transfers */ 350 if (bitlen % 8) { 351 debug("Non byte aligned SPI transfer.\n"); 352 return -1; 353 } 354 355 cr0 = (priv->bits_per_word - 1) | (priv->type << SPI_FRF_OFFSET) | 356 (priv->mode << SPI_MODE_OFFSET) | 357 (priv->tmode << SPI_TMOD_OFFSET); 358 359 if (rx && tx) 360 priv->tmode = SPI_TMOD_TR; 361 else if (rx) 362 priv->tmode = SPI_TMOD_RO; 363 else 364 priv->tmode = SPI_TMOD_TO; 365 366 cr0 &= ~SPI_TMOD_MASK; 367 cr0 |= (priv->tmode << SPI_TMOD_OFFSET); 368 369 priv->len = bitlen >> 3; 370 debug("%s: rx=%p tx=%p len=%d [bytes]\n", __func__, rx, tx, priv->len); 371 372 priv->tx = (void *)tx; 373 priv->tx_end = priv->tx + priv->len; 374 priv->rx = rx; 375 priv->rx_end = priv->rx + priv->len; 376 377 /* Disable controller before writing control registers */ 378 spi_enable_chip(priv, 0); 379 380 debug("%s: cr0=%08x\n", __func__, cr0); 381 /* Reprogram cr0 only if changed */ 382 if (dw_readw(priv, DW_SPI_CTRL0) != cr0) 383 dw_writew(priv, DW_SPI_CTRL0, cr0); 384 385 /* 386 * Configure the desired SS (slave select 0...3) in the controller 387 * The DW SPI controller will activate and deactivate this CS 388 * automatically. So no cs_activate() etc is needed in this driver. 389 */ 390 cs = spi_chip_select(dev); 391 dw_writel(priv, DW_SPI_SER, 1 << cs); 392 393 /* Enable controller after writing control registers */ 394 spi_enable_chip(priv, 1); 395 396 /* Start transfer in a polling loop */ 397 ret = poll_transfer(priv); 398 399 /* 400 * Wait for current transmit operation to complete. 401 * Otherwise if some data still exists in Tx FIFO it can be 402 * silently flushed, i.e. dropped on disabling of the controller, 403 * which happens when writing 0 to DW_SPI_SSIENR which happens 404 * in the beginning of new transfer. 405 */ 406 if (readl_poll_timeout(priv->regs + DW_SPI_SR, val, 407 !(val & SR_TF_EMPT) || (val & SR_BUSY), 408 RX_TIMEOUT * 1000)) { 409 ret = -ETIMEDOUT; 410 } 411 412 return ret; 413 } 414 415 static int dw_spi_set_speed(struct udevice *bus, uint speed) 416 { 417 struct dw_spi_platdata *plat = bus->platdata; 418 struct dw_spi_priv *priv = dev_get_priv(bus); 419 u16 clk_div; 420 421 if (speed > plat->frequency) 422 speed = plat->frequency; 423 424 /* Disable controller before writing control registers */ 425 spi_enable_chip(priv, 0); 426 427 /* clk_div doesn't support odd number */ 428 clk_div = priv->bus_clk_rate / speed; 429 clk_div = (clk_div + 1) & 0xfffe; 430 dw_writel(priv, DW_SPI_BAUDR, clk_div); 431 432 /* Enable controller after writing control registers */ 433 spi_enable_chip(priv, 1); 434 435 priv->freq = speed; 436 debug("%s: regs=%p speed=%d clk_div=%d\n", __func__, priv->regs, 437 priv->freq, clk_div); 438 439 return 0; 440 } 441 442 static int dw_spi_set_mode(struct udevice *bus, uint mode) 443 { 444 struct dw_spi_priv *priv = dev_get_priv(bus); 445 446 /* 447 * Can't set mode yet. Since this depends on if rx, tx, or 448 * rx & tx is requested. So we have to defer this to the 449 * real transfer function. 450 */ 451 priv->mode = mode; 452 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode); 453 454 return 0; 455 } 456 457 static const struct dm_spi_ops dw_spi_ops = { 458 .xfer = dw_spi_xfer, 459 .set_speed = dw_spi_set_speed, 460 .set_mode = dw_spi_set_mode, 461 /* 462 * cs_info is not needed, since we require all chip selects to be 463 * in the device tree explicitly 464 */ 465 }; 466 467 static const struct udevice_id dw_spi_ids[] = { 468 { .compatible = "snps,dw-apb-ssi" }, 469 { } 470 }; 471 472 U_BOOT_DRIVER(dw_spi) = { 473 .name = "dw_spi", 474 .id = UCLASS_SPI, 475 .of_match = dw_spi_ids, 476 .ops = &dw_spi_ops, 477 .ofdata_to_platdata = dw_spi_ofdata_to_platdata, 478 .platdata_auto_alloc_size = sizeof(struct dw_spi_platdata), 479 .priv_auto_alloc_size = sizeof(struct dw_spi_priv), 480 .probe = dw_spi_probe, 481 }; 482