1 /* 2 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Driver for SPI controller on DaVinci. Based on atmel_spi.c 5 * by Atmel Corporation 6 * 7 * Copyright (C) 2007 Atmel Corporation 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 #include <common.h> 12 #include <spi.h> 13 #include <malloc.h> 14 #include <asm/io.h> 15 #include <asm/arch/hardware.h> 16 17 struct davinci_spi_regs { 18 dv_reg gcr0; /* 0x00 */ 19 dv_reg gcr1; /* 0x04 */ 20 dv_reg int0; /* 0x08 */ 21 dv_reg lvl; /* 0x0c */ 22 dv_reg flg; /* 0x10 */ 23 dv_reg pc0; /* 0x14 */ 24 dv_reg pc1; /* 0x18 */ 25 dv_reg pc2; /* 0x1c */ 26 dv_reg pc3; /* 0x20 */ 27 dv_reg pc4; /* 0x24 */ 28 dv_reg pc5; /* 0x28 */ 29 dv_reg rsvd[3]; 30 dv_reg dat0; /* 0x38 */ 31 dv_reg dat1; /* 0x3c */ 32 dv_reg buf; /* 0x40 */ 33 dv_reg emu; /* 0x44 */ 34 dv_reg delay; /* 0x48 */ 35 dv_reg def; /* 0x4c */ 36 dv_reg fmt0; /* 0x50 */ 37 dv_reg fmt1; /* 0x54 */ 38 dv_reg fmt2; /* 0x58 */ 39 dv_reg fmt3; /* 0x5c */ 40 dv_reg intvec0; /* 0x60 */ 41 dv_reg intvec1; /* 0x64 */ 42 }; 43 44 #define BIT(x) (1 << (x)) 45 46 /* SPIGCR0 */ 47 #define SPIGCR0_SPIENA_MASK 0x1 48 #define SPIGCR0_SPIRST_MASK 0x0 49 50 /* SPIGCR0 */ 51 #define SPIGCR1_CLKMOD_MASK BIT(1) 52 #define SPIGCR1_MASTER_MASK BIT(0) 53 #define SPIGCR1_SPIENA_MASK BIT(24) 54 55 /* SPIPC0 */ 56 #define SPIPC0_DIFUN_MASK BIT(11) /* SIMO */ 57 #define SPIPC0_DOFUN_MASK BIT(10) /* SOMI */ 58 #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */ 59 #define SPIPC0_EN0FUN_MASK BIT(0) 60 61 /* SPIFMT0 */ 62 #define SPIFMT_SHIFTDIR_SHIFT 20 63 #define SPIFMT_POLARITY_SHIFT 17 64 #define SPIFMT_PHASE_SHIFT 16 65 #define SPIFMT_PRESCALE_SHIFT 8 66 67 /* SPIDAT1 */ 68 #define SPIDAT1_CSHOLD_SHIFT 28 69 #define SPIDAT1_CSNR_SHIFT 16 70 71 /* SPIDELAY */ 72 #define SPI_C2TDELAY_SHIFT 24 73 #define SPI_T2CDELAY_SHIFT 16 74 75 /* SPIBUF */ 76 #define SPIBUF_RXEMPTY_MASK BIT(31) 77 #define SPIBUF_TXFULL_MASK BIT(29) 78 79 /* SPIDEF */ 80 #define SPIDEF_CSDEF0_MASK BIT(0) 81 82 #define SPI0_BUS 0 83 #define SPI0_BASE CONFIG_SYS_SPI_BASE 84 /* 85 * Define default SPI0_NUM_CS as 1 for existing platforms that uses this 86 * driver. Platform can configure number of CS using CONFIG_SYS_SPI0_NUM_CS 87 * if more than one CS is supported and by defining CONFIG_SYS_SPI0. 88 */ 89 #ifndef CONFIG_SYS_SPI0 90 #define SPI0_NUM_CS 1 91 #else 92 #define SPI0_NUM_CS CONFIG_SYS_SPI0_NUM_CS 93 #endif 94 95 /* 96 * define CONFIG_SYS_SPI1 when platform has spi-1 device (bus #1) and 97 * CONFIG_SYS_SPI1_NUM_CS defines number of CS on this bus 98 */ 99 #ifdef CONFIG_SYS_SPI1 100 #define SPI1_BUS 1 101 #define SPI1_NUM_CS CONFIG_SYS_SPI1_NUM_CS 102 #define SPI1_BASE CONFIG_SYS_SPI1_BASE 103 #endif 104 105 /* 106 * define CONFIG_SYS_SPI2 when platform has spi-2 device (bus #2) and 107 * CONFIG_SYS_SPI2_NUM_CS defines number of CS on this bus 108 */ 109 #ifdef CONFIG_SYS_SPI2 110 #define SPI2_BUS 2 111 #define SPI2_NUM_CS CONFIG_SYS_SPI2_NUM_CS 112 #define SPI2_BASE CONFIG_SYS_SPI2_BASE 113 #endif 114 115 struct davinci_spi_slave { 116 struct spi_slave slave; 117 struct davinci_spi_regs *regs; 118 unsigned int freq; 119 }; 120 121 static inline struct davinci_spi_slave *to_davinci_spi(struct spi_slave *slave) 122 { 123 return container_of(slave, struct davinci_spi_slave, slave); 124 } 125 126 void spi_init() 127 { 128 /* do nothing */ 129 } 130 131 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 132 unsigned int max_hz, unsigned int mode) 133 { 134 struct davinci_spi_slave *ds; 135 136 if (!spi_cs_is_valid(bus, cs)) 137 return NULL; 138 139 ds = spi_alloc_slave(struct davinci_spi_slave, bus, cs); 140 if (!ds) 141 return NULL; 142 143 switch (bus) { 144 case SPI0_BUS: 145 ds->regs = (struct davinci_spi_regs *)SPI0_BASE; 146 break; 147 #ifdef CONFIG_SYS_SPI1 148 case SPI1_BUS: 149 ds->regs = (struct davinci_spi_regs *)SPI1_BASE; 150 break; 151 #endif 152 #ifdef CONFIG_SYS_SPI2 153 case SPI2_BUS: 154 ds->regs = (struct davinci_spi_regs *)SPI2_BASE; 155 break; 156 #endif 157 default: /* Invalid bus number */ 158 return NULL; 159 } 160 161 ds->freq = max_hz; 162 163 return &ds->slave; 164 } 165 166 void spi_free_slave(struct spi_slave *slave) 167 { 168 struct davinci_spi_slave *ds = to_davinci_spi(slave); 169 170 free(ds); 171 } 172 173 int spi_claim_bus(struct spi_slave *slave) 174 { 175 struct davinci_spi_slave *ds = to_davinci_spi(slave); 176 unsigned int scalar; 177 178 /* Enable the SPI hardware */ 179 writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0); 180 udelay(1000); 181 writel(SPIGCR0_SPIENA_MASK, &ds->regs->gcr0); 182 183 /* Set master mode, powered up and not activated */ 184 writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &ds->regs->gcr1); 185 186 /* CS, CLK, SIMO and SOMI are functional pins */ 187 writel(((1 << slave->cs) | SPIPC0_CLKFUN_MASK | 188 SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0); 189 190 /* setup format */ 191 scalar = ((CONFIG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF; 192 193 /* 194 * Use following format: 195 * character length = 8, 196 * clock signal delayed by half clk cycle, 197 * clock low in idle state - Mode 0, 198 * MSB shifted out first 199 */ 200 writel(8 | (scalar << SPIFMT_PRESCALE_SHIFT) | 201 (1 << SPIFMT_PHASE_SHIFT), &ds->regs->fmt0); 202 203 /* 204 * Including a minor delay. No science here. Should be good even with 205 * no delay 206 */ 207 writel((50 << SPI_C2TDELAY_SHIFT) | 208 (50 << SPI_T2CDELAY_SHIFT), &ds->regs->delay); 209 210 /* default chip select register */ 211 writel(SPIDEF_CSDEF0_MASK, &ds->regs->def); 212 213 /* no interrupts */ 214 writel(0, &ds->regs->int0); 215 writel(0, &ds->regs->lvl); 216 217 /* enable SPI */ 218 writel((readl(&ds->regs->gcr1) | SPIGCR1_SPIENA_MASK), &ds->regs->gcr1); 219 220 return 0; 221 } 222 223 void spi_release_bus(struct spi_slave *slave) 224 { 225 struct davinci_spi_slave *ds = to_davinci_spi(slave); 226 227 /* Disable the SPI hardware */ 228 writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0); 229 } 230 231 /* 232 * This functions needs to act like a macro to avoid pipeline reloads in the 233 * loops below. Use always_inline. This gains us about 160KiB/s and the bloat 234 * appears to be zero bytes (da830). 235 */ 236 __attribute__((always_inline)) 237 static inline u32 davinci_spi_xfer_data(struct davinci_spi_slave *ds, u32 data) 238 { 239 u32 buf_reg_val; 240 241 /* send out data */ 242 writel(data, &ds->regs->dat1); 243 244 /* wait for the data to clock in/out */ 245 while ((buf_reg_val = readl(&ds->regs->buf)) & SPIBUF_RXEMPTY_MASK) 246 ; 247 248 return buf_reg_val; 249 } 250 251 static int davinci_spi_read(struct spi_slave *slave, unsigned int len, 252 u8 *rxp, unsigned long flags) 253 { 254 struct davinci_spi_slave *ds = to_davinci_spi(slave); 255 unsigned int data1_reg_val; 256 257 /* enable CS hold, CS[n] and clear the data bits */ 258 data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) | 259 (slave->cs << SPIDAT1_CSNR_SHIFT)); 260 261 /* wait till TXFULL is deasserted */ 262 while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK) 263 ; 264 265 /* preload the TX buffer to avoid clock starvation */ 266 writel(data1_reg_val, &ds->regs->dat1); 267 268 /* keep reading 1 byte until only 1 byte left */ 269 while ((len--) > 1) 270 *rxp++ = davinci_spi_xfer_data(ds, data1_reg_val); 271 272 /* clear CS hold when we reach the end */ 273 if (flags & SPI_XFER_END) 274 data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT); 275 276 /* read the last byte */ 277 *rxp = davinci_spi_xfer_data(ds, data1_reg_val); 278 279 return 0; 280 } 281 282 static int davinci_spi_write(struct spi_slave *slave, unsigned int len, 283 const u8 *txp, unsigned long flags) 284 { 285 struct davinci_spi_slave *ds = to_davinci_spi(slave); 286 unsigned int data1_reg_val; 287 288 /* enable CS hold and clear the data bits */ 289 data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) | 290 (slave->cs << SPIDAT1_CSNR_SHIFT)); 291 292 /* wait till TXFULL is deasserted */ 293 while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK) 294 ; 295 296 /* preload the TX buffer to avoid clock starvation */ 297 if (len > 2) { 298 writel(data1_reg_val | *txp++, &ds->regs->dat1); 299 len--; 300 } 301 302 /* keep writing 1 byte until only 1 byte left */ 303 while ((len--) > 1) 304 davinci_spi_xfer_data(ds, data1_reg_val | *txp++); 305 306 /* clear CS hold when we reach the end */ 307 if (flags & SPI_XFER_END) 308 data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT); 309 310 /* write the last byte */ 311 davinci_spi_xfer_data(ds, data1_reg_val | *txp); 312 313 return 0; 314 } 315 316 #ifndef CONFIG_SPI_HALF_DUPLEX 317 static int davinci_spi_read_write(struct spi_slave *slave, unsigned int len, 318 u8 *rxp, const u8 *txp, unsigned long flags) 319 { 320 struct davinci_spi_slave *ds = to_davinci_spi(slave); 321 unsigned int data1_reg_val; 322 323 /* enable CS hold and clear the data bits */ 324 data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) | 325 (slave->cs << SPIDAT1_CSNR_SHIFT)); 326 327 /* wait till TXFULL is deasserted */ 328 while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK) 329 ; 330 331 /* keep reading and writing 1 byte until only 1 byte left */ 332 while ((len--) > 1) 333 *rxp++ = davinci_spi_xfer_data(ds, data1_reg_val | *txp++); 334 335 /* clear CS hold when we reach the end */ 336 if (flags & SPI_XFER_END) 337 data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT); 338 339 /* read and write the last byte */ 340 *rxp = davinci_spi_xfer_data(ds, data1_reg_val | *txp); 341 342 return 0; 343 } 344 #endif 345 346 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, 347 const void *dout, void *din, unsigned long flags) 348 { 349 unsigned int len; 350 351 if (bitlen == 0) 352 /* Finish any previously submitted transfers */ 353 goto out; 354 355 /* 356 * It's not clear how non-8-bit-aligned transfers are supposed to be 357 * represented as a stream of bytes...this is a limitation of 358 * the current SPI interface - here we terminate on receiving such a 359 * transfer request. 360 */ 361 if (bitlen % 8) { 362 /* Errors always terminate an ongoing transfer */ 363 flags |= SPI_XFER_END; 364 goto out; 365 } 366 367 len = bitlen / 8; 368 369 if (!dout) 370 return davinci_spi_read(slave, len, din, flags); 371 else if (!din) 372 return davinci_spi_write(slave, len, dout, flags); 373 #ifndef CONFIG_SPI_HALF_DUPLEX 374 else 375 return davinci_spi_read_write(slave, len, din, dout, flags); 376 #else 377 printf("SPI full duplex transaction requested with " 378 "CONFIG_SPI_HALF_DUPLEX defined.\n"); 379 flags |= SPI_XFER_END; 380 #endif 381 382 out: 383 if (flags & SPI_XFER_END) { 384 u8 dummy = 0; 385 davinci_spi_write(slave, 1, &dummy, flags); 386 } 387 return 0; 388 } 389 390 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 391 { 392 int ret = 0; 393 394 switch (bus) { 395 case SPI0_BUS: 396 if (cs < SPI0_NUM_CS) 397 ret = 1; 398 break; 399 #ifdef CONFIG_SYS_SPI1 400 case SPI1_BUS: 401 if (cs < SPI1_NUM_CS) 402 ret = 1; 403 break; 404 #endif 405 #ifdef CONFIG_SYS_SPI2 406 case SPI2_BUS: 407 if (cs < SPI2_NUM_CS) 408 ret = 1; 409 break; 410 #endif 411 default: 412 /* Invalid bus number. Do nothing */ 413 break; 414 } 415 return ret; 416 } 417 418 void spi_cs_activate(struct spi_slave *slave) 419 { 420 /* do nothing */ 421 } 422 423 void spi_cs_deactivate(struct spi_slave *slave) 424 { 425 /* do nothing */ 426 } 427