1 /* 2 * Copyright (C) 2012 3 * Altera Corporation <www.altera.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <fdtdec.h> 11 #include <malloc.h> 12 #include <spi.h> 13 #include <asm/errno.h> 14 #include "cadence_qspi.h" 15 16 #define CQSPI_STIG_READ 0 17 #define CQSPI_STIG_WRITE 1 18 #define CQSPI_INDIRECT_READ 2 19 #define CQSPI_INDIRECT_WRITE 3 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 static int cadence_spi_write_speed(struct udevice *bus, uint hz) 24 { 25 struct cadence_spi_platdata *plat = bus->platdata; 26 struct cadence_spi_priv *priv = dev_get_priv(bus); 27 28 cadence_qspi_apb_config_baudrate_div(priv->regbase, 29 CONFIG_CQSPI_REF_CLK, hz); 30 31 /* Reconfigure delay timing if speed is changed. */ 32 cadence_qspi_apb_delay(priv->regbase, CONFIG_CQSPI_REF_CLK, hz, 33 plat->tshsl_ns, plat->tsd2d_ns, 34 plat->tchsh_ns, plat->tslch_ns); 35 36 return 0; 37 } 38 39 /* Calibration sequence to determine the read data capture delay register */ 40 static int spi_calibration(struct udevice *bus, uint hz) 41 { 42 struct cadence_spi_priv *priv = dev_get_priv(bus); 43 void *base = priv->regbase; 44 u8 opcode_rdid = 0x9F; 45 unsigned int idcode = 0, temp = 0; 46 int err = 0, i, range_lo = -1, range_hi = -1; 47 48 /* start with slowest clock (1 MHz) */ 49 cadence_spi_write_speed(bus, 1000000); 50 51 /* configure the read data capture delay register to 0 */ 52 cadence_qspi_apb_readdata_capture(base, 1, 0); 53 54 /* Enable QSPI */ 55 cadence_qspi_apb_controller_enable(base); 56 57 /* read the ID which will be our golden value */ 58 err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid, 59 3, (u8 *)&idcode); 60 if (err) { 61 puts("SF: Calibration failed (read)\n"); 62 return err; 63 } 64 65 /* use back the intended clock and find low range */ 66 cadence_spi_write_speed(bus, hz); 67 for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) { 68 /* Disable QSPI */ 69 cadence_qspi_apb_controller_disable(base); 70 71 /* reconfigure the read data capture delay register */ 72 cadence_qspi_apb_readdata_capture(base, 1, i); 73 74 /* Enable back QSPI */ 75 cadence_qspi_apb_controller_enable(base); 76 77 /* issue a RDID to get the ID value */ 78 err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid, 79 3, (u8 *)&temp); 80 if (err) { 81 puts("SF: Calibration failed (read)\n"); 82 return err; 83 } 84 85 /* search for range lo */ 86 if (range_lo == -1 && temp == idcode) { 87 range_lo = i; 88 continue; 89 } 90 91 /* search for range hi */ 92 if (range_lo != -1 && temp != idcode) { 93 range_hi = i - 1; 94 break; 95 } 96 range_hi = i; 97 } 98 99 if (range_lo == -1) { 100 puts("SF: Calibration failed (low range)\n"); 101 return err; 102 } 103 104 /* Disable QSPI for subsequent initialization */ 105 cadence_qspi_apb_controller_disable(base); 106 107 /* configure the final value for read data capture delay register */ 108 cadence_qspi_apb_readdata_capture(base, 1, (range_hi + range_lo) / 2); 109 debug("SF: Read data capture delay calibrated to %i (%i - %i)\n", 110 (range_hi + range_lo) / 2, range_lo, range_hi); 111 112 /* just to ensure we do once only when speed or chip select change */ 113 priv->qspi_calibrated_hz = hz; 114 priv->qspi_calibrated_cs = spi_chip_select(bus); 115 116 return 0; 117 } 118 119 static int cadence_spi_set_speed(struct udevice *bus, uint hz) 120 { 121 struct cadence_spi_platdata *plat = bus->platdata; 122 struct cadence_spi_priv *priv = dev_get_priv(bus); 123 int err; 124 125 /* Disable QSPI */ 126 cadence_qspi_apb_controller_disable(priv->regbase); 127 128 /* 129 * Calibration required for different current SCLK speed, requested 130 * SCLK speed or chip select 131 */ 132 if (priv->previous_hz != hz || 133 priv->qspi_calibrated_hz != hz || 134 priv->qspi_calibrated_cs != spi_chip_select(bus)) { 135 err = spi_calibration(bus, hz); 136 if (err) 137 return err; 138 139 /* prevent calibration run when same as previous request */ 140 priv->previous_hz = hz; 141 } 142 143 /* Enable QSPI */ 144 cadence_qspi_apb_controller_enable(priv->regbase); 145 146 debug("%s: speed=%d\n", __func__, hz); 147 148 return 0; 149 } 150 151 static int cadence_spi_probe(struct udevice *bus) 152 { 153 struct cadence_spi_platdata *plat = bus->platdata; 154 struct cadence_spi_priv *priv = dev_get_priv(bus); 155 156 priv->regbase = plat->regbase; 157 priv->ahbbase = plat->ahbbase; 158 159 if (!priv->qspi_is_init) { 160 cadence_qspi_apb_controller_init(plat); 161 priv->qspi_is_init = 1; 162 } 163 164 return 0; 165 } 166 167 static int cadence_spi_set_mode(struct udevice *bus, uint mode) 168 { 169 struct cadence_spi_priv *priv = dev_get_priv(bus); 170 unsigned int clk_pol = (mode & SPI_CPOL) ? 1 : 0; 171 unsigned int clk_pha = (mode & SPI_CPHA) ? 1 : 0; 172 173 /* Disable QSPI */ 174 cadence_qspi_apb_controller_disable(priv->regbase); 175 176 /* Set SPI mode */ 177 cadence_qspi_apb_set_clk_mode(priv->regbase, clk_pol, clk_pha); 178 179 /* Enable QSPI */ 180 cadence_qspi_apb_controller_enable(priv->regbase); 181 182 return 0; 183 } 184 185 static int cadence_spi_xfer(struct udevice *dev, unsigned int bitlen, 186 const void *dout, void *din, unsigned long flags) 187 { 188 struct udevice *bus = dev->parent; 189 struct cadence_spi_platdata *plat = bus->platdata; 190 struct cadence_spi_priv *priv = dev_get_priv(bus); 191 void *base = priv->regbase; 192 u8 *cmd_buf = priv->cmd_buf; 193 size_t data_bytes; 194 int err = 0; 195 u32 mode = CQSPI_STIG_WRITE; 196 197 if (flags & SPI_XFER_BEGIN) { 198 /* copy command to local buffer */ 199 priv->cmd_len = bitlen / 8; 200 memcpy(cmd_buf, dout, priv->cmd_len); 201 } 202 203 if (flags == (SPI_XFER_BEGIN | SPI_XFER_END)) { 204 /* if start and end bit are set, the data bytes is 0. */ 205 data_bytes = 0; 206 } else { 207 data_bytes = bitlen / 8; 208 } 209 debug("%s: len=%d [bytes]\n", __func__, data_bytes); 210 211 /* Set Chip select */ 212 cadence_qspi_apb_chipselect(base, spi_chip_select(dev), 213 CONFIG_CQSPI_DECODER); 214 215 if ((flags & SPI_XFER_END) || (flags == 0)) { 216 if (priv->cmd_len == 0) { 217 printf("QSPI: Error, command is empty.\n"); 218 return -1; 219 } 220 221 if (din && data_bytes) { 222 /* read */ 223 /* Use STIG if no address. */ 224 if (!CQSPI_IS_ADDR(priv->cmd_len)) 225 mode = CQSPI_STIG_READ; 226 else 227 mode = CQSPI_INDIRECT_READ; 228 } else if (dout && !(flags & SPI_XFER_BEGIN)) { 229 /* write */ 230 if (!CQSPI_IS_ADDR(priv->cmd_len)) 231 mode = CQSPI_STIG_WRITE; 232 else 233 mode = CQSPI_INDIRECT_WRITE; 234 } 235 236 switch (mode) { 237 case CQSPI_STIG_READ: 238 err = cadence_qspi_apb_command_read( 239 base, priv->cmd_len, cmd_buf, 240 data_bytes, din); 241 242 break; 243 case CQSPI_STIG_WRITE: 244 err = cadence_qspi_apb_command_write(base, 245 priv->cmd_len, cmd_buf, 246 data_bytes, dout); 247 break; 248 case CQSPI_INDIRECT_READ: 249 err = cadence_qspi_apb_indirect_read_setup(plat, 250 priv->cmd_len, cmd_buf); 251 if (!err) { 252 err = cadence_qspi_apb_indirect_read_execute 253 (plat, data_bytes, din); 254 } 255 break; 256 case CQSPI_INDIRECT_WRITE: 257 err = cadence_qspi_apb_indirect_write_setup 258 (plat, priv->cmd_len, cmd_buf); 259 if (!err) { 260 err = cadence_qspi_apb_indirect_write_execute 261 (plat, data_bytes, dout); 262 } 263 break; 264 default: 265 err = -1; 266 break; 267 } 268 269 if (flags & SPI_XFER_END) { 270 /* clear command buffer */ 271 memset(cmd_buf, 0, sizeof(priv->cmd_buf)); 272 priv->cmd_len = 0; 273 } 274 } 275 276 return err; 277 } 278 279 static int cadence_spi_ofdata_to_platdata(struct udevice *bus) 280 { 281 struct cadence_spi_platdata *plat = bus->platdata; 282 const void *blob = gd->fdt_blob; 283 int node = bus->of_offset; 284 int subnode; 285 u32 data[4]; 286 int ret; 287 288 /* 2 base addresses are needed, lets get them from the DT */ 289 ret = fdtdec_get_int_array(blob, node, "reg", data, ARRAY_SIZE(data)); 290 if (ret) { 291 printf("Error: Can't get base addresses (ret=%d)!\n", ret); 292 return -ENODEV; 293 } 294 295 plat->regbase = (void *)data[0]; 296 plat->ahbbase = (void *)data[2]; 297 298 /* All other paramters are embedded in the child node */ 299 subnode = fdt_first_subnode(blob, node); 300 if (subnode < 0) { 301 printf("Error: subnode with SPI flash config missing!\n"); 302 return -ENODEV; 303 } 304 305 /* Use 500 KHz as a suitable default */ 306 plat->max_hz = fdtdec_get_uint(blob, subnode, "spi-max-frequency", 307 500000); 308 309 /* Read other parameters from DT */ 310 plat->page_size = fdtdec_get_int(blob, subnode, "page-size", 256); 311 plat->block_size = fdtdec_get_int(blob, subnode, "block-size", 16); 312 plat->tshsl_ns = fdtdec_get_int(blob, subnode, "tshsl-ns", 200); 313 plat->tsd2d_ns = fdtdec_get_int(blob, subnode, "tsd2d-ns", 255); 314 plat->tchsh_ns = fdtdec_get_int(blob, subnode, "tchsh-ns", 20); 315 plat->tslch_ns = fdtdec_get_int(blob, subnode, "tslch-ns", 20); 316 plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128); 317 318 debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n", 319 __func__, plat->regbase, plat->ahbbase, plat->max_hz, 320 plat->page_size); 321 322 return 0; 323 } 324 325 static const struct dm_spi_ops cadence_spi_ops = { 326 .xfer = cadence_spi_xfer, 327 .set_speed = cadence_spi_set_speed, 328 .set_mode = cadence_spi_set_mode, 329 /* 330 * cs_info is not needed, since we require all chip selects to be 331 * in the device tree explicitly 332 */ 333 }; 334 335 static const struct udevice_id cadence_spi_ids[] = { 336 { .compatible = "cadence,qspi" }, 337 { } 338 }; 339 340 U_BOOT_DRIVER(cadence_spi) = { 341 .name = "cadence_spi", 342 .id = UCLASS_SPI, 343 .of_match = cadence_spi_ids, 344 .ops = &cadence_spi_ops, 345 .ofdata_to_platdata = cadence_spi_ofdata_to_platdata, 346 .platdata_auto_alloc_size = sizeof(struct cadence_spi_platdata), 347 .priv_auto_alloc_size = sizeof(struct cadence_spi_priv), 348 .probe = cadence_spi_probe, 349 }; 350