1menu "SPI Support" 2 3config DM_SPI 4 bool "Enable Driver Model for SPI drivers" 5 depends on DM 6 help 7 Enable driver model for SPI. The SPI slave interface 8 (spi_setup_slave(), spi_xfer(), etc.) is then implemented by 9 the SPI uclass. Drivers provide methods to access the SPI 10 buses that they control. The uclass interface is defined in 11 include/spi.h. The existing spi_slave structure is attached 12 as 'parent data' to every slave on each bus. Slaves 13 typically use driver-private data instead of extending the 14 spi_slave structure. 15 16config SPI_MEM 17 bool "SPI memory extension" 18 help 19 Enable this option if you want to enable the SPI memory extension. 20 This extension is meant to simplify interaction with SPI memories 21 by providing an high-level interface to send memory-like commands. 22 23if DM_SPI 24 25config ALTERA_SPI 26 bool "Altera SPI driver" 27 help 28 Enable the Altera SPI driver. This driver can be used to 29 access the SPI NOR flash on platforms embedding this Altera 30 IP core. Please find details on the "Embedded Peripherals IP 31 User Guide" of Altera. 32 33config ATH79_SPI 34 bool "Atheros SPI driver" 35 depends on ARCH_ATH79 36 help 37 Enable the Atheros ar7xxx/ar9xxx SoC SPI driver, it was used 38 to access SPI NOR flash and other SPI peripherals. This driver 39 uses driver model and requires a device tree binding to operate. 40 please refer to doc/device-tree-bindings/spi/spi-ath79.txt. 41 42config ATMEL_SPI 43 bool "Atmel SPI driver" 44 depends on ARCH_AT91 45 help 46 This enables driver for the Atmel SPI Controller, present on 47 many AT91 (ARM) chips. This driver can be used to access 48 the SPI Flash, such as AT25DF321. 49 50config CADENCE_QSPI 51 bool "Cadence QSPI driver" 52 help 53 Enable the Cadence Quad-SPI (QSPI) driver. This driver can be 54 used to access the SPI NOR flash on platforms embedding this 55 Cadence IP core. 56 57config DESIGNWARE_SPI 58 bool "Designware SPI driver" 59 help 60 Enable the Designware SPI driver. This driver can be used to 61 access the SPI NOR flash on platforms embedding this Designware 62 IP core. 63 64config EXYNOS_SPI 65 bool "Samsung Exynos SPI driver" 66 help 67 Enable the Samsung Exynos SPI driver. This driver can be used to 68 access the SPI NOR flash on platforms embedding this Samsung 69 Exynos IP core. 70 71config FSL_DSPI 72 bool "Freescale DSPI driver" 73 help 74 Enable the Freescale DSPI driver. This driver can be used to 75 access the SPI NOR flash and SPI Data flash on platforms embedding 76 this Freescale DSPI IP core. LS102xA and Colibri VF50/VF61 platforms 77 use this driver. 78 79config ICH_SPI 80 bool "Intel ICH SPI driver" 81 help 82 Enable the Intel ICH SPI driver. This driver can be used to 83 access the SPI NOR flash on platforms embedding this Intel 84 ICH IP core. 85 86config MVEBU_A3700_SPI 87 bool "Marvell Armada 3700 SPI driver" 88 help 89 Enable the Marvell Armada 3700 SPI driver. This driver can be 90 used to access the SPI NOR flash on platforms embedding this 91 Marvell IP core. 92 93config PIC32_SPI 94 bool "Microchip PIC32 SPI driver" 95 depends on MACH_PIC32 96 help 97 Enable the Microchip PIC32 SPI driver. This driver can be used 98 to access the SPI NOR flash, MMC-over-SPI on platforms based on 99 Microchip PIC32 family devices. 100 101config ROCKCHIP_SPI 102 bool "Rockchip SPI driver" 103 help 104 Enable the Rockchip SPI driver, used to access SPI NOR flash and 105 other SPI peripherals (such as the Chrome OS EC) on Rockchip SoCs. 106 This uses driver model and requires a device tree binding to 107 operate. 108 109config ROCKCHIP_SFC 110 bool "Rockchip SFC driver" 111 help 112 Enable the Rockchip SFC driver, used to access SPI NOR flash 113 on Rockchip SoCs. 114 This uses driver model and requires a device tree binding to 115 operate. 116 117config SANDBOX_SPI 118 bool "Sandbox SPI driver" 119 depends on SANDBOX && DM 120 help 121 Enable SPI support for sandbox. This is an emulation of a real SPI 122 bus. Devices can be attached to the bus using the device tree 123 which specifies the driver to use. As an example, see this device 124 tree fragment from sandbox.dts. It shows that the SPI bus has a 125 single flash device on chip select 0 which is emulated by the driver 126 for "sandbox,spi-flash", which is in drivers/mtd/spi/sandbox.c. 127 128 spi@0 { 129 #address-cells = <1>; 130 #size-cells = <0>; 131 reg = <0>; 132 compatible = "sandbox,spi"; 133 cs-gpios = <0>, <&gpio_a 0>; 134 flash@0 { 135 reg = <0>; 136 compatible = "spansion,m25p16", "sandbox,spi-flash"; 137 spi-max-frequency = <40000000>; 138 sandbox,filename = "spi.bin"; 139 }; 140 }; 141 142config STM32_QSPI 143 bool "STM32F7 QSPI driver" 144 depends on STM32F7 145 help 146 Enable the STM32F7 Quad-SPI (QSPI) driver. This driver can be 147 used to access the SPI NOR flash chips on platforms embedding 148 this ST IP core. 149 150config TEGRA114_SPI 151 bool "nVidia Tegra114 SPI driver" 152 help 153 Enable the nVidia Tegra114 SPI driver. This driver can be used to 154 access the SPI NOR flash on platforms embedding this nVidia Tegra114 155 IP core. 156 157 This controller is different than the older SoCs SPI controller and 158 also register interface get changed with this controller. 159 160config TEGRA20_SFLASH 161 bool "nVidia Tegra20 Serial Flash controller driver" 162 help 163 Enable the nVidia Tegra20 Serial Flash controller driver. This driver 164 can be used to access the SPI NOR flash on platforms embedding this 165 nVidia Tegra20 IP core. 166 167config TEGRA20_SLINK 168 bool "nVidia Tegra20/Tegra30 SLINK driver" 169 help 170 Enable the nVidia Tegra20/Tegra30 SLINK driver. This driver can 171 be used to access the SPI NOR flash on platforms embedding this 172 nVidia Tegra20/Tegra30 IP cores. 173 174config TEGRA210_QSPI 175 bool "nVidia Tegra210 QSPI driver" 176 help 177 Enable the Tegra Quad-SPI (QSPI) driver for T210. This driver 178 be used to access SPI chips on platforms embedding this 179 NVIDIA Tegra210 IP core. 180 181config XILINX_SPI 182 bool "Xilinx SPI driver" 183 help 184 Enable the Xilinx SPI driver from the Xilinx EDK. This SPI 185 controller support 8 bit SPI transfers only, with or w/o FIFO. 186 For more info on Xilinx SPI Register Definitions and Overview 187 see driver file - drivers/spi/xilinx_spi.c 188 189config ZYNQ_SPI 190 bool "Zynq SPI driver" 191 depends on ARCH_ZYNQ || ARCH_ZYNQMP 192 help 193 Enable the Zynq SPI driver. This driver can be used to 194 access the SPI NOR flash on platforms embedding this Zynq 195 SPI IP core. 196 197config ZYNQ_QSPI 198 bool "Zynq QSPI driver" 199 depends on ARCH_ZYNQ 200 help 201 Enable the Zynq Quad-SPI (QSPI) driver. This driver can be 202 used to access the SPI NOR flash on platforms embedding this 203 Zynq QSPI IP core. This IP is used to connect the flash in 204 4-bit qspi, 8-bit dual stacked and shared 4-bit dual parallel. 205 206endif # if DM_SPI 207 208config SOFT_SPI 209 bool "Soft SPI driver" 210 help 211 Enable Soft SPI driver. This driver is to use GPIO simulate 212 the SPI protocol. 213 214config FSL_ESPI 215 bool "Freescale eSPI driver" 216 help 217 Enable the Freescale eSPI driver. This driver can be used to 218 access the SPI interface and SPI NOR flash on platforms embedding 219 this Freescale eSPI IP core. 220 221config FSL_QSPI 222 bool "Freescale QSPI driver" 223 help 224 Enable the Freescale Quad-SPI (QSPI) driver. This driver can be 225 used to access the SPI NOR flash on platforms embedding this 226 Freescale IP core. 227 228config TI_QSPI 229 bool "TI QSPI driver" 230 help 231 Enable the TI Quad-SPI (QSPI) driver for DRA7xx and AM43xx evms. 232 This driver support spi flash single, quad and memory reads. 233 234config MPC8XX_SPI 235 bool "MPC8XX SPI Driver" 236 depends on 8xx 237 help 238 Enable support for SPI on MPC8XX 239 240config OMAP3_SPI 241 bool "McSPI driver for OMAP" 242 help 243 SPI master controller for OMAP24XX and later Multichannel SPI 244 (McSPI). This driver be used to access SPI chips on platforms 245 embedding this OMAP3 McSPI IP core. 246 247endmenu # menu "SPI Support" 248