1menu "SPI Support" 2 3config DM_SPI 4 bool "Enable Driver Model for SPI drivers" 5 depends on DM 6 help 7 Enable driver model for SPI. The SPI slave interface 8 (spi_setup_slave(), spi_xfer(), etc.) is then implemented by 9 the SPI uclass. Drivers provide methods to access the SPI 10 buses that they control. The uclass interface is defined in 11 include/spi.h. The existing spi_slave structure is attached 12 as 'parent data' to every slave on each bus. Slaves 13 typically use driver-private data instead of extending the 14 spi_slave structure. 15 16if DM_SPI 17 18config ALTERA_SPI 19 bool "Altera SPI driver" 20 help 21 Enable the Altera SPI driver. This driver can be used to 22 access the SPI NOR flash on platforms embedding this Altera 23 IP core. Please find details on the "Embedded Peripherals IP 24 User Guide" of Altera. 25 26config ATH79_SPI 27 bool "Atheros SPI driver" 28 depends on ARCH_ATH79 29 help 30 Enable the Atheros ar7xxx/ar9xxx SoC SPI driver, it was used 31 to access SPI NOR flash and other SPI peripherals. This driver 32 uses driver model and requires a device tree binding to operate. 33 please refer to doc/device-tree-bindings/spi/spi-ath79.txt. 34 35config ATMEL_SPI 36 bool "Atmel SPI driver" 37 depends on ARCH_AT91 38 help 39 This enables driver for the Atmel SPI Controller, present on 40 many AT91 (ARM) chips. This driver can be used to access 41 the SPI Flash, such as AT25DF321. 42 43config CADENCE_QSPI 44 bool "Cadence QSPI driver" 45 help 46 Enable the Cadence Quad-SPI (QSPI) driver. This driver can be 47 used to access the SPI NOR flash on platforms embedding this 48 Cadence IP core. 49 50config DESIGNWARE_SPI 51 bool "Designware SPI driver" 52 help 53 Enable the Designware SPI driver. This driver can be used to 54 access the SPI NOR flash on platforms embedding this Designware 55 IP core. 56 57config EXYNOS_SPI 58 bool "Samsung Exynos SPI driver" 59 help 60 Enable the Samsung Exynos SPI driver. This driver can be used to 61 access the SPI NOR flash on platforms embedding this Samsung 62 Exynos IP core. 63 64config FSL_DSPI 65 bool "Freescale DSPI driver" 66 help 67 Enable the Freescale DSPI driver. This driver can be used to 68 access the SPI NOR flash and SPI Data flash on platforms embedding 69 this Freescale DSPI IP core. LS102xA and Colibri VF50/VF61 platforms 70 use this driver. 71 72config ICH_SPI 73 bool "Intel ICH SPI driver" 74 help 75 Enable the Intel ICH SPI driver. This driver can be used to 76 access the SPI NOR flash on platforms embedding this Intel 77 ICH IP core. 78 79config MVEBU_A3700_SPI 80 bool "Marvell Armada 3700 SPI driver" 81 help 82 Enable the Marvell Armada 3700 SPI driver. This driver can be 83 used to access the SPI NOR flash on platforms embedding this 84 Marvell IP core. 85 86config PIC32_SPI 87 bool "Microchip PIC32 SPI driver" 88 depends on MACH_PIC32 89 help 90 Enable the Microchip PIC32 SPI driver. This driver can be used 91 to access the SPI NOR flash, MMC-over-SPI on platforms based on 92 Microchip PIC32 family devices. 93 94config ROCKCHIP_SPI 95 bool "Rockchip SPI driver" 96 help 97 Enable the Rockchip SPI driver, used to access SPI NOR flash and 98 other SPI peripherals (such as the Chrome OS EC) on Rockchip SoCs. 99 This uses driver model and requires a device tree binding to 100 operate. 101 102config ROCKCHIP_SFC 103 bool "Rockchip SFC driver" 104 help 105 Enable the Rockchip SFC driver, used to access SPI NOR flash 106 on Rockchip SoCs. 107 This uses driver model and requires a device tree binding to 108 operate. 109 110config SANDBOX_SPI 111 bool "Sandbox SPI driver" 112 depends on SANDBOX && DM 113 help 114 Enable SPI support for sandbox. This is an emulation of a real SPI 115 bus. Devices can be attached to the bus using the device tree 116 which specifies the driver to use. As an example, see this device 117 tree fragment from sandbox.dts. It shows that the SPI bus has a 118 single flash device on chip select 0 which is emulated by the driver 119 for "sandbox,spi-flash", which is in drivers/mtd/spi/sandbox.c. 120 121 spi@0 { 122 #address-cells = <1>; 123 #size-cells = <0>; 124 reg = <0>; 125 compatible = "sandbox,spi"; 126 cs-gpios = <0>, <&gpio_a 0>; 127 flash@0 { 128 reg = <0>; 129 compatible = "spansion,m25p16", "sandbox,spi-flash"; 130 spi-max-frequency = <40000000>; 131 sandbox,filename = "spi.bin"; 132 }; 133 }; 134 135config STM32_QSPI 136 bool "STM32F7 QSPI driver" 137 depends on STM32F7 138 help 139 Enable the STM32F7 Quad-SPI (QSPI) driver. This driver can be 140 used to access the SPI NOR flash chips on platforms embedding 141 this ST IP core. 142 143config TEGRA114_SPI 144 bool "nVidia Tegra114 SPI driver" 145 help 146 Enable the nVidia Tegra114 SPI driver. This driver can be used to 147 access the SPI NOR flash on platforms embedding this nVidia Tegra114 148 IP core. 149 150 This controller is different than the older SoCs SPI controller and 151 also register interface get changed with this controller. 152 153config TEGRA20_SFLASH 154 bool "nVidia Tegra20 Serial Flash controller driver" 155 help 156 Enable the nVidia Tegra20 Serial Flash controller driver. This driver 157 can be used to access the SPI NOR flash on platforms embedding this 158 nVidia Tegra20 IP core. 159 160config TEGRA20_SLINK 161 bool "nVidia Tegra20/Tegra30 SLINK driver" 162 help 163 Enable the nVidia Tegra20/Tegra30 SLINK driver. This driver can 164 be used to access the SPI NOR flash on platforms embedding this 165 nVidia Tegra20/Tegra30 IP cores. 166 167config TEGRA210_QSPI 168 bool "nVidia Tegra210 QSPI driver" 169 help 170 Enable the Tegra Quad-SPI (QSPI) driver for T210. This driver 171 be used to access SPI chips on platforms embedding this 172 NVIDIA Tegra210 IP core. 173 174config XILINX_SPI 175 bool "Xilinx SPI driver" 176 help 177 Enable the Xilinx SPI driver from the Xilinx EDK. This SPI 178 controller support 8 bit SPI transfers only, with or w/o FIFO. 179 For more info on Xilinx SPI Register Definitions and Overview 180 see driver file - drivers/spi/xilinx_spi.c 181 182config ZYNQ_SPI 183 bool "Zynq SPI driver" 184 depends on ARCH_ZYNQ || ARCH_ZYNQMP 185 help 186 Enable the Zynq SPI driver. This driver can be used to 187 access the SPI NOR flash on platforms embedding this Zynq 188 SPI IP core. 189 190config ZYNQ_QSPI 191 bool "Zynq QSPI driver" 192 depends on ARCH_ZYNQ 193 help 194 Enable the Zynq Quad-SPI (QSPI) driver. This driver can be 195 used to access the SPI NOR flash on platforms embedding this 196 Zynq QSPI IP core. This IP is used to connect the flash in 197 4-bit qspi, 8-bit dual stacked and shared 4-bit dual parallel. 198 199endif # if DM_SPI 200 201config SOFT_SPI 202 bool "Soft SPI driver" 203 help 204 Enable Soft SPI driver. This driver is to use GPIO simulate 205 the SPI protocol. 206 207config FSL_ESPI 208 bool "Freescale eSPI driver" 209 help 210 Enable the Freescale eSPI driver. This driver can be used to 211 access the SPI interface and SPI NOR flash on platforms embedding 212 this Freescale eSPI IP core. 213 214config FSL_QSPI 215 bool "Freescale QSPI driver" 216 help 217 Enable the Freescale Quad-SPI (QSPI) driver. This driver can be 218 used to access the SPI NOR flash on platforms embedding this 219 Freescale IP core. 220 221config TI_QSPI 222 bool "TI QSPI driver" 223 help 224 Enable the TI Quad-SPI (QSPI) driver for DRA7xx and AM43xx evms. 225 This driver support spi flash single, quad and memory reads. 226 227config MPC8XX_SPI 228 bool "MPC8XX SPI Driver" 229 depends on 8xx 230 help 231 Enable support for SPI on MPC8XX 232 233config OMAP3_SPI 234 bool "McSPI driver for OMAP" 235 help 236 SPI master controller for OMAP24XX and later Multichannel SPI 237 (McSPI). This driver be used to access SPI chips on platforms 238 embedding this OMAP3 McSPI IP core. 239 240endmenu # menu "SPI Support" 241