16a12cebdSVikas Manocha /* 26a12cebdSVikas Manocha * (C) Copyright 2016 36a12cebdSVikas Manocha * Vikas Manocha, <vikas.manocha@st.com> 46a12cebdSVikas Manocha * 56a12cebdSVikas Manocha * SPDX-License-Identifier: GPL-2.0+ 66a12cebdSVikas Manocha */ 76a12cebdSVikas Manocha 86a12cebdSVikas Manocha #ifndef _SERIAL_STM32_X7_ 96a12cebdSVikas Manocha #define _SERIAL_STM32_X7_ 106a12cebdSVikas Manocha 116a12cebdSVikas Manocha struct stm32_usart { 126a12cebdSVikas Manocha u32 cr1; 136a12cebdSVikas Manocha u32 cr2; 146a12cebdSVikas Manocha u32 cr3; 156a12cebdSVikas Manocha u32 brr; 166a12cebdSVikas Manocha u32 gtpr; 176a12cebdSVikas Manocha u32 rtor; 186a12cebdSVikas Manocha u32 rqr; 196a12cebdSVikas Manocha u32 sr; 206a12cebdSVikas Manocha u32 icr; 216a12cebdSVikas Manocha u32 rd_dr; 226a12cebdSVikas Manocha u32 tx_dr; 236a12cebdSVikas Manocha }; 246a12cebdSVikas Manocha 25122b2d47SPatrice Chotard /* Information about a serial port */ 26122b2d47SPatrice Chotard struct stm32x7_serial_platdata { 27122b2d47SPatrice Chotard struct stm32_usart *base; /* address of registers in physical memory */ 28*27265ceeSPatrice Chotard unsigned long int clock_rate; 29122b2d47SPatrice Chotard }; 306a12cebdSVikas Manocha 311afcf9cbSPatrice Chotard #define USART_CR1_OVER8 (1 << 15) 326a12cebdSVikas Manocha #define USART_CR1_TE (1 << 3) 331afcf9cbSPatrice Chotard #define USART_CR1_RE (1 << 2) 346a12cebdSVikas Manocha #define USART_CR1_UE (1 << 0) 356a12cebdSVikas Manocha 366c0c3ce8SVikas Manocha #define USART_CR3_OVRDIS (1 << 12) 376c0c3ce8SVikas Manocha 386a12cebdSVikas Manocha #define USART_SR_FLAG_RXNE (1 << 5) 396a12cebdSVikas Manocha #define USART_SR_FLAG_TXE (1 << 7) 406a12cebdSVikas Manocha 416a12cebdSVikas Manocha #define USART_BRR_F_MASK 0xFF 426a12cebdSVikas Manocha #define USART_BRR_M_SHIFT 4 436a12cebdSVikas Manocha #define USART_BRR_M_MASK 0xFFF0 446a12cebdSVikas Manocha 456a12cebdSVikas Manocha #endif 46