1 /* 2 * SuperH SCIF device driver. 3 * Copyright (c) 2007,2008 Nobuhiro Iwamatsu 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 20 #include <common.h> 21 #include <asm/processor.h> 22 23 #ifdef CFG_SCIF_CONSOLE 24 25 #if defined (CONFIG_CONS_SCIF0) 26 #define SCIF_BASE SCIF0_BASE 27 #elif defined (CONFIG_CONS_SCIF1) 28 #define SCIF_BASE SCIF1_BASE 29 #else 30 #error "Default SCIF doesn't set....." 31 #endif 32 33 /* Base register */ 34 #define SCSMR (vu_short *)(SCIF_BASE + 0x0) 35 #define SCBRR (vu_char *)(SCIF_BASE + 0x4) 36 #define SCSCR (vu_short *)(SCIF_BASE + 0x8) 37 #define SCFCR (vu_short *)(SCIF_BASE + 0x18) 38 #define SCFDR (vu_short *)(SCIF_BASE + 0x1C) 39 #ifdef CONFIG_CPU_SH7720 /* SH7720 specific */ 40 #define SCFSR (vu_short *)(SCIF_BASE + 0x14) /* SCSSR */ 41 #define SCFTDR (vu_char *)(SCIF_BASE + 0x20) 42 #define SCFRDR (vu_char *)(SCIF_BASE + 0x24) 43 #else 44 #define SCFTDR (vu_char *)(SCIF_BASE + 0xC) 45 #define SCFSR (vu_short *)(SCIF_BASE + 0x10) 46 #define SCFRDR (vu_char *)(SCIF_BASE + 0x14) 47 #endif 48 49 #if defined(CONFIG_CPU_SH7780) || \ 50 defined(CONFIG_CPU_SH7785) 51 #define SCRFDR (vu_short *)(SCIF_BASE + 0x20) 52 #define SCSPTR (vu_short *)(SCIF_BASE + 0x24) 53 #define SCLSR (vu_short *)(SCIF_BASE + 0x28) 54 #define SCRER (vu_short *)(SCIF_BASE + 0x2C) 55 #define LSR_ORER 1 56 #elif defined(CONFIG_CPU_SH7750) || \ 57 defined(CONFIG_CPU_SH7722) 58 #define SCSPTR (vu_short *)(SCIF_BASE + 0x20) 59 #define SCLSR (vu_short *)(SCIF_BASE + 0x24) 60 #define LSR_ORER 1 61 #elif defined(CONFIG_CPU_SH7720) 62 #define SCLSR (vu_short *)(SCIF_BASE + 0x24) 63 #define LSR_ORER 0x0200 64 #elif defined(CONFIG_CPU_SH7710) 65 defined(CONFIG_CPU_SH7712) 66 #define SCLSR SCFSR /* SCSSR */ 67 #define LSR_ORER 1 68 #endif 69 70 /* SCBRR register value setting */ 71 #if defined(CONFIG_CPU_SH7720) 72 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) 73 #else /* Generic SuperH */ 74 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) 75 #endif 76 77 #define SCR_RE (1 << 4) 78 #define SCR_TE (1 << 5) 79 #define FCR_RFRST (1 << 1) /* RFCL */ 80 #define FCR_TFRST (1 << 2) /* TFCL */ 81 #define FSR_DR (1 << 0) 82 #define FSR_RDF (1 << 1) 83 #define FSR_FER (1 << 3) 84 #define FSR_BRK (1 << 4) 85 #define FSR_FER (1 << 3) 86 #define FSR_TEND (1 << 6) 87 #define FSR_ER (1 << 7) 88 89 /*----------------------------------------------------------------------*/ 90 91 void serial_setbrg (void) 92 { 93 DECLARE_GLOBAL_DATA_PTR; 94 *SCBRR = SCBRR_VALUE(gd->baudrate,CONFIG_SYS_CLK_FREQ); 95 } 96 97 int serial_init (void) 98 { 99 *SCSCR = (SCR_RE | SCR_TE); 100 *SCSMR = 0 ; 101 *SCSMR = 0; 102 *SCFCR = (FCR_RFRST | FCR_TFRST); 103 *SCFCR; 104 *SCFCR = 0; 105 106 serial_setbrg(); 107 return 0; 108 } 109 110 static int serial_tx_fifo_level (void) 111 { 112 return (*SCFDR >> 8) & 0x1F; 113 } 114 115 static int serial_rx_fifo_level (void) 116 { 117 return (*SCFDR >> 0) & 0x1F; 118 } 119 120 void serial_raw_putc (const char c) 121 { 122 unsigned int fsr_bits_to_clear; 123 124 while (1) { 125 if (*SCFSR & FSR_TEND) { /* Tx fifo is empty */ 126 fsr_bits_to_clear = FSR_TEND; 127 break; 128 } 129 } 130 131 *SCFTDR = c; 132 if (fsr_bits_to_clear != 0) 133 *SCFSR &= ~fsr_bits_to_clear; 134 } 135 136 void serial_putc (const char c) 137 { 138 if (c == '\n') 139 serial_raw_putc ('\r'); 140 serial_raw_putc (c); 141 } 142 143 void serial_puts (const char *s) 144 { 145 char c; 146 while ((c = *s++) != 0) 147 serial_putc (c); 148 } 149 150 int serial_tstc (void) 151 { 152 return serial_rx_fifo_level() ? 1 : 0; 153 } 154 155 #define FSR_ERR_CLEAR 0x0063 156 #define RDRF_CLEAR 0x00fc 157 void handle_error( void ){ 158 159 (void)*SCFSR ; 160 *SCFSR = FSR_ERR_CLEAR ; 161 (void)*SCLSR ; 162 *SCLSR = 0x00 ; 163 } 164 165 int serial_getc_check( void ){ 166 unsigned short status; 167 168 status = *SCFSR ; 169 170 if (status & (FSR_FER | FSR_FER | FSR_ER | FSR_BRK)) 171 handle_error(); 172 if( *SCLSR & LSR_ORER ) 173 handle_error(); 174 return (status & ( FSR_DR | FSR_RDF )); 175 } 176 177 int serial_getc (void) 178 { 179 unsigned short status ; 180 char ch; 181 while(!serial_getc_check()); 182 183 ch = *SCFRDR; 184 status = *SCFSR ; 185 186 *SCFSR = RDRF_CLEAR ; 187 188 if (status & (FSR_FER | FSR_FER | FSR_ER | FSR_BRK)) 189 handle_error(); 190 191 if( *SCLSR & LSR_ORER ) 192 handle_error(); 193 194 return ch ; 195 } 196 197 #endif /* CFG_SCIF_CONSOLE */ 198