1 /* 2 * SuperH SCIF device driver. 3 * Copyright (c) 2007,2008 Nobuhiro Iwamatsu 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 20 #include <common.h> 21 #include <asm/processor.h> 22 23 #if defined (CONFIG_CONS_SCIF0) 24 #define SCIF_BASE SCIF0_BASE 25 #elif defined (CONFIG_CONS_SCIF1) 26 #define SCIF_BASE SCIF1_BASE 27 #elif defined (CONFIG_CONS_SCIF2) 28 #define SCIF_BASE SCIF2_BASE 29 #else 30 #error "Default SCIF doesn't set....." 31 #endif 32 33 /* Base register */ 34 #define SCSMR (vu_short *)(SCIF_BASE + 0x0) 35 #define SCBRR (vu_char *)(SCIF_BASE + 0x4) 36 #define SCSCR (vu_short *)(SCIF_BASE + 0x8) 37 #define SCFCR (vu_short *)(SCIF_BASE + 0x18) 38 #define SCFDR (vu_short *)(SCIF_BASE + 0x1C) 39 #ifdef CONFIG_CPU_SH7720 /* SH7720 specific */ 40 # define SCFSR (vu_short *)(SCIF_BASE + 0x14) /* SCSSR */ 41 # define SCFTDR (vu_char *)(SCIF_BASE + 0x20) 42 # define SCFRDR (vu_char *)(SCIF_BASE + 0x24) 43 #else 44 # define SCFTDR (vu_char *)(SCIF_BASE + 0xC) 45 # define SCFSR (vu_short *)(SCIF_BASE + 0x10) 46 # define SCFRDR (vu_char *)(SCIF_BASE + 0x14) 47 #endif 48 49 #if defined(CONFIG_CPU_SH7780) || \ 50 defined(CONFIG_CPU_SH7785) 51 # define SCRFDR (vu_short *)(SCIF_BASE + 0x20) 52 # define SCSPTR (vu_short *)(SCIF_BASE + 0x24) 53 # define SCLSR (vu_short *)(SCIF_BASE + 0x28) 54 # define SCRER (vu_short *)(SCIF_BASE + 0x2C) 55 # define LSR_ORER 1 56 # define FIFOLEVEL_MASK 0xFF 57 #elif defined(CONFIG_CPU_SH7763) 58 # if defined (CONFIG_CONS_SCIF2) 59 # define SCSPTR (vu_short *)(SCIF_BASE + 0x20) 60 # define SCLSR (vu_short *)(SCIF_BASE + 0x24) 61 # define LSR_ORER 1 62 # define FIFOLEVEL_MASK 0x1F 63 # else 64 # define SCRFDR (vu_short *)(SCIF_BASE + 0x20) 65 # define SCSPTR (vu_short *)(SCIF_BASE + 0x24) 66 # define SCLSR (vu_short *)(SCIF_BASE + 0x28) 67 # define SCRER (vu_short *)(SCIF_BASE + 0x2C) 68 # define LSR_ORER 1 69 # define FIFOLEVEL_MASK 0xFF 70 # endif 71 #elif defined(CONFIG_CPU_SH7750) || \ 72 defined(CONFIG_CPU_SH7751) || \ 73 defined(CONFIG_CPU_SH7722) 74 # define SCSPTR (vu_short *)(SCIF_BASE + 0x20) 75 # define SCLSR (vu_short *)(SCIF_BASE + 0x24) 76 # define LSR_ORER 1 77 # define FIFOLEVEL_MASK 0x1F 78 #elif defined(CONFIG_CPU_SH7720) 79 # define SCLSR (vu_short *)(SCIF_BASE + 0x24) 80 # define LSR_ORER 0x0200 81 # define FIFOLEVEL_MASK 0x1F 82 #elif defined(CONFIG_CPU_SH7710) || \ 83 defined(CONFIG_CPU_SH7712) 84 # define SCLSR SCFSR /* SCSSR */ 85 # define LSR_ORER 1 86 # define FIFOLEVEL_MASK 0x1F 87 #endif 88 89 /* SCBRR register value setting */ 90 #if defined(CONFIG_CPU_SH7720) 91 # define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) 92 #else /* Generic SuperH */ 93 # define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) 94 #endif 95 96 #define SCR_RE (1 << 4) 97 #define SCR_TE (1 << 5) 98 #define FCR_RFRST (1 << 1) /* RFCL */ 99 #define FCR_TFRST (1 << 2) /* TFCL */ 100 #define FSR_DR (1 << 0) 101 #define FSR_RDF (1 << 1) 102 #define FSR_FER (1 << 3) 103 #define FSR_BRK (1 << 4) 104 #define FSR_FER (1 << 3) 105 #define FSR_TEND (1 << 6) 106 #define FSR_ER (1 << 7) 107 108 /*----------------------------------------------------------------------*/ 109 110 void serial_setbrg(void) 111 { 112 DECLARE_GLOBAL_DATA_PTR; 113 *SCBRR = SCBRR_VALUE(gd->baudrate, CONFIG_SYS_CLK_FREQ); 114 } 115 116 int serial_init(void) 117 { 118 *SCSCR = (SCR_RE | SCR_TE); 119 *SCSMR = 0; 120 *SCSMR = 0; 121 *SCFCR = (FCR_RFRST | FCR_TFRST); 122 *SCFCR; 123 *SCFCR = 0; 124 125 serial_setbrg(); 126 return 0; 127 } 128 129 static int serial_rx_fifo_level(void) 130 { 131 #if defined(SCRFDR) 132 return (*SCRFDR >> 0) & FIFOLEVEL_MASK; 133 #else 134 return (*SCFDR >> 0) & FIFOLEVEL_MASK; 135 #endif 136 } 137 138 void serial_raw_putc(const char c) 139 { 140 unsigned int fsr_bits_to_clear; 141 142 while (1) { 143 if (*SCFSR & FSR_TEND) { /* Tx fifo is empty */ 144 fsr_bits_to_clear = FSR_TEND; 145 break; 146 } 147 } 148 149 *SCFTDR = c; 150 if (fsr_bits_to_clear != 0) 151 *SCFSR &= ~fsr_bits_to_clear; 152 } 153 154 void serial_putc(const char c) 155 { 156 if (c == '\n') 157 serial_raw_putc('\r'); 158 serial_raw_putc(c); 159 } 160 161 void serial_puts(const char *s) 162 { 163 char c; 164 while ((c = *s++) != 0) 165 serial_putc(c); 166 } 167 168 int serial_tstc(void) 169 { 170 return serial_rx_fifo_level()? 1 : 0; 171 } 172 173 #define FSR_ERR_CLEAR 0x0063 174 #define RDRF_CLEAR 0x00fc 175 void handle_error(void) 176 { 177 178 (void)*SCFSR; 179 *SCFSR = FSR_ERR_CLEAR; 180 (void)*SCLSR; 181 *SCLSR = 0x00; 182 } 183 184 int serial_getc_check(void) 185 { 186 unsigned short status; 187 188 status = *SCFSR; 189 190 if (status & (FSR_FER | FSR_ER | FSR_BRK)) 191 handle_error(); 192 if (*SCLSR & LSR_ORER) 193 handle_error(); 194 return (status & (FSR_DR | FSR_RDF)); 195 } 196 197 int serial_getc(void) 198 { 199 unsigned short status; 200 char ch; 201 while (!serial_getc_check()) ; 202 203 ch = *SCFRDR; 204 status = *SCFSR; 205 206 *SCFSR = RDRF_CLEAR; 207 208 if (status & (FSR_FER | FSR_FER | FSR_ER | FSR_BRK)) 209 handle_error(); 210 211 if (*SCLSR & LSR_ORER) 212 handle_error(); 213 214 return ch; 215 } 216