1 /* 2 * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <errno.h> 10 #include <watchdog.h> 11 #include <asm/arch/imx-regs.h> 12 #include <asm/arch/clock.h> 13 #include <dm/platform_data/serial_mxc.h> 14 #include <serial.h> 15 #include <linux/compiler.h> 16 17 /* UART Control Register Bit Fields.*/ 18 #define URXD_CHARRDY (1<<15) 19 #define URXD_ERR (1<<14) 20 #define URXD_OVRRUN (1<<13) 21 #define URXD_FRMERR (1<<12) 22 #define URXD_BRK (1<<11) 23 #define URXD_PRERR (1<<10) 24 #define URXD_RX_DATA (0xFF) 25 #define UCR1_ADEN (1<<15) /* Auto dectect interrupt */ 26 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 27 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 28 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 29 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 30 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ 31 #define UCR1_IREN (1<<7) /* Infrared interface enable */ 32 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 33 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 34 #define UCR1_SNDBRK (1<<4) /* Send break */ 35 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ 36 #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ 37 #define UCR1_DOZE (1<<1) /* Doze */ 38 #define UCR1_UARTEN (1<<0) /* UART enabled */ 39 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 40 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 41 #define UCR2_CTSC (1<<13) /* CTS pin control */ 42 #define UCR2_CTS (1<<12) /* Clear to send */ 43 #define UCR2_ESCEN (1<<11) /* Escape enable */ 44 #define UCR2_PREN (1<<8) /* Parity enable */ 45 #define UCR2_PROE (1<<7) /* Parity odd/even */ 46 #define UCR2_STPB (1<<6) /* Stop */ 47 #define UCR2_WS (1<<5) /* Word size */ 48 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 49 #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 50 #define UCR2_RXEN (1<<1) /* Receiver enabled */ 51 #define UCR2_SRST (1<<0) /* SW reset */ 52 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 53 #define UCR3_PARERREN (1<<12) /* Parity enable */ 54 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 55 #define UCR3_DSR (1<<10) /* Data set ready */ 56 #define UCR3_DCD (1<<9) /* Data carrier detect */ 57 #define UCR3_RI (1<<8) /* Ring indicator */ 58 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ 59 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 60 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 61 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 62 #define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */ 63 #define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */ 64 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 65 #define UCR3_BPEN (1<<0) /* Preset registers enable */ 66 #define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */ 67 #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 68 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 69 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 70 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 71 #define UCR4_IRSC (1<<5) /* IR special case */ 72 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 73 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 74 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 75 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 76 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 77 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 78 #define UFCR_RFDIV_SHF 7 /* Reference freq divider shift */ 79 #define RFDIV 4 /* divide input clock by 2 */ 80 #define UFCR_DCEDTE (1<<6) /* DTE mode select */ 81 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 82 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 83 #define USR1_RTSS (1<<14) /* RTS pin status */ 84 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 85 #define USR1_RTSD (1<<12) /* RTS delta */ 86 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 87 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 88 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 89 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ 90 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 91 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 92 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 93 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 94 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 95 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 96 #define USR2_IDLE (1<<12) /* Idle condition */ 97 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 98 #define USR2_WAKE (1<<7) /* Wake */ 99 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 100 #define USR2_TXDC (1<<3) /* Transmitter complete */ 101 #define USR2_BRCD (1<<2) /* Break condition */ 102 #define USR2_ORE (1<<1) /* Overrun error */ 103 #define USR2_RDR (1<<0) /* Recv data ready */ 104 #define UTS_FRCPERR (1<<13) /* Force parity error */ 105 #define UTS_LOOP (1<<12) /* Loop tx and rx */ 106 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 107 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 108 #define UTS_TXFULL (1<<4) /* TxFIFO full */ 109 #define UTS_RXFULL (1<<3) /* RxFIFO full */ 110 #define UTS_SOFTRS (1<<0) /* Software reset */ 111 112 DECLARE_GLOBAL_DATA_PTR; 113 114 struct mxc_uart { 115 u32 rxd; 116 u32 spare0[15]; 117 118 u32 txd; 119 u32 spare1[15]; 120 121 u32 cr1; 122 u32 cr2; 123 u32 cr3; 124 u32 cr4; 125 126 u32 fcr; 127 u32 sr1; 128 u32 sr2; 129 u32 esc; 130 131 u32 tim; 132 u32 bir; 133 u32 bmr; 134 u32 brc; 135 136 u32 onems; 137 u32 ts; 138 }; 139 140 #ifndef CONFIG_DM_SERIAL 141 142 #ifndef CONFIG_MXC_UART_BASE 143 #error "define CONFIG_MXC_UART_BASE to use the MXC UART driver" 144 #endif 145 146 #define mxc_base ((struct mxc_uart *)CONFIG_MXC_UART_BASE) 147 148 #define TXTL 2 /* reset default */ 149 #define RXTL 1 /* reset default */ 150 151 static void mxc_serial_setbrg(void) 152 { 153 u32 clk = imx_get_uartclk(); 154 155 if (!gd->baudrate) 156 gd->baudrate = CONFIG_BAUDRATE; 157 158 writel(((RFDIV << UFCR_RFDIV_SHF) | 159 (TXTL << UFCR_TXTL_SHF) | 160 (RXTL << UFCR_RXTL_SHF)), 161 &mxc_base->fcr); 162 writel(0xf, &mxc_base->bir); 163 writel(clk / (2 * gd->baudrate), &mxc_base->bmr); 164 165 writel(UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST, 166 &mxc_base->cr2); 167 writel(UCR1_UARTEN, &mxc_base->cr1); 168 } 169 170 static int mxc_serial_getc(void) 171 { 172 while (readl(&mxc_base->ts) & UTS_RXEMPTY) 173 WATCHDOG_RESET(); 174 return (readl(&mxc_base->rxd) & URXD_RX_DATA); /* mask out status from upper word */ 175 } 176 177 static void mxc_serial_putc(const char c) 178 { 179 /* If \n, also do \r */ 180 if (c == '\n') 181 serial_putc('\r'); 182 183 writel(c, &mxc_base->txd); 184 185 /* wait for transmitter to be ready */ 186 while (!(readl(&mxc_base->ts) & UTS_TXEMPTY)) 187 WATCHDOG_RESET(); 188 } 189 190 /* 191 * Test whether a character is in the RX buffer 192 */ 193 static int mxc_serial_tstc(void) 194 { 195 /* If receive fifo is empty, return false */ 196 if (readl(&mxc_base->ts) & UTS_RXEMPTY) 197 return 0; 198 return 1; 199 } 200 201 /* 202 * Initialise the serial port with the given baudrate. The settings 203 * are always 8 data bits, no parity, 1 stop bit, no start bits. 204 * 205 */ 206 static int mxc_serial_init(void) 207 { 208 writel(0, &mxc_base->cr1); 209 writel(0, &mxc_base->cr2); 210 211 while (!(readl(&mxc_base->cr2) & UCR2_SRST)); 212 213 writel(0x704 | UCR3_ADNIMP, &mxc_base->cr3); 214 writel(0x8000, &mxc_base->cr4); 215 writel(0x2b, &mxc_base->esc); 216 writel(0, &mxc_base->tim); 217 218 writel(0, &mxc_base->ts); 219 220 serial_setbrg(); 221 222 return 0; 223 } 224 225 static struct serial_device mxc_serial_drv = { 226 .name = "mxc_serial", 227 .start = mxc_serial_init, 228 .stop = NULL, 229 .setbrg = mxc_serial_setbrg, 230 .putc = mxc_serial_putc, 231 .puts = default_serial_puts, 232 .getc = mxc_serial_getc, 233 .tstc = mxc_serial_tstc, 234 }; 235 236 void mxc_serial_initialize(void) 237 { 238 serial_register(&mxc_serial_drv); 239 } 240 241 __weak struct serial_device *default_serial_console(void) 242 { 243 return &mxc_serial_drv; 244 } 245 #endif 246 247 #ifdef CONFIG_DM_SERIAL 248 249 int mxc_serial_setbrg(struct udevice *dev, int baudrate) 250 { 251 struct mxc_serial_platdata *plat = dev->platdata; 252 struct mxc_uart *const uart = plat->reg; 253 u32 clk = imx_get_uartclk(); 254 u32 tmp; 255 256 tmp = RFDIV << UFCR_RFDIV_SHF; 257 if (plat->use_dte) 258 tmp |= UFCR_DCEDTE; 259 writel(tmp, &uart->fcr); 260 261 writel(0xf, &uart->bir); 262 writel(clk / (2 * baudrate), &uart->bmr); 263 264 writel(UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST, 265 &uart->cr2); 266 writel(UCR1_UARTEN, &uart->cr1); 267 268 return 0; 269 } 270 271 static int mxc_serial_probe(struct udevice *dev) 272 { 273 struct mxc_serial_platdata *plat = dev->platdata; 274 struct mxc_uart *const uart = plat->reg; 275 276 writel(0, &uart->cr1); 277 writel(0, &uart->cr2); 278 while (!(readl(&uart->cr2) & UCR2_SRST)); 279 writel(0x704 | UCR3_ADNIMP, &uart->cr3); 280 writel(0x8000, &uart->cr4); 281 writel(0x2b, &uart->esc); 282 writel(0, &uart->tim); 283 writel(0, &uart->ts); 284 285 return 0; 286 } 287 288 static int mxc_serial_getc(struct udevice *dev) 289 { 290 struct mxc_serial_platdata *plat = dev->platdata; 291 struct mxc_uart *const uart = plat->reg; 292 293 if (readl(&uart->ts) & UTS_RXEMPTY) 294 return -EAGAIN; 295 296 return readl(&uart->rxd) & URXD_RX_DATA; 297 } 298 299 static int mxc_serial_putc(struct udevice *dev, const char ch) 300 { 301 struct mxc_serial_platdata *plat = dev->platdata; 302 struct mxc_uart *const uart = plat->reg; 303 304 if (!(readl(&uart->ts) & UTS_TXEMPTY)) 305 return -EAGAIN; 306 307 writel(ch, &uart->txd); 308 309 return 0; 310 } 311 312 static int mxc_serial_pending(struct udevice *dev, bool input) 313 { 314 struct mxc_serial_platdata *plat = dev->platdata; 315 struct mxc_uart *const uart = plat->reg; 316 uint32_t sr2 = readl(&uart->sr2); 317 318 if (input) 319 return sr2 & USR2_RDR ? 1 : 0; 320 else 321 return sr2 & USR2_TXDC ? 0 : 1; 322 } 323 324 static const struct dm_serial_ops mxc_serial_ops = { 325 .putc = mxc_serial_putc, 326 .pending = mxc_serial_pending, 327 .getc = mxc_serial_getc, 328 .setbrg = mxc_serial_setbrg, 329 }; 330 331 #if CONFIG_IS_ENABLED(OF_CONTROL) 332 static int mxc_serial_ofdata_to_platdata(struct udevice *dev) 333 { 334 struct mxc_serial_platdata *plat = dev->platdata; 335 fdt_addr_t addr; 336 337 addr = devfdt_get_addr(dev); 338 if (addr == FDT_ADDR_T_NONE) 339 return -EINVAL; 340 341 plat->reg = (struct mxc_uart *)addr; 342 343 plat->use_dte = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev), 344 "fsl,dte-mode"); 345 return 0; 346 } 347 348 static const struct udevice_id mxc_serial_ids[] = { 349 { .compatible = "fsl,imx6ul-uart" }, 350 { .compatible = "fsl,imx7d-uart" }, 351 { } 352 }; 353 #endif 354 355 U_BOOT_DRIVER(serial_mxc) = { 356 .name = "serial_mxc", 357 .id = UCLASS_SERIAL, 358 #if CONFIG_IS_ENABLED(OF_CONTROL) 359 .of_match = mxc_serial_ids, 360 .ofdata_to_platdata = mxc_serial_ofdata_to_platdata, 361 .platdata_auto_alloc_size = sizeof(struct mxc_serial_platdata), 362 #endif 363 .probe = mxc_serial_probe, 364 .ops = &mxc_serial_ops, 365 .flags = DM_FLAG_PRE_RELOC, 366 }; 367 #endif 368