1 /* 2 * COM1 NS16550 support 3 * originally from linux source (arch/powerpc/boot/ns16550.c) 4 * modified to use CONFIG_SYS_ISA_MEM and new defines 5 */ 6 7 #include <common.h> 8 #include <clk.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <ns16550.h> 12 #include <serial.h> 13 #include <watchdog.h> 14 #include <linux/types.h> 15 #include <asm/io.h> 16 17 DECLARE_GLOBAL_DATA_PTR; 18 19 #define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */ 20 #define UART_MCRVAL (UART_MCR_DTR | \ 21 UART_MCR_RTS) /* RTS/DTR */ 22 23 #ifndef CONFIG_DM_SERIAL 24 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED 25 #define serial_out(x, y) outb(x, (ulong)y) 26 #define serial_in(y) inb((ulong)y) 27 #elif defined(CONFIG_SYS_NS16550_MEM32) && (CONFIG_SYS_NS16550_REG_SIZE > 0) 28 #define serial_out(x, y) out_be32(y, x) 29 #define serial_in(y) in_be32(y) 30 #elif defined(CONFIG_SYS_NS16550_MEM32) && (CONFIG_SYS_NS16550_REG_SIZE < 0) 31 #define serial_out(x, y) out_le32(y, x) 32 #define serial_in(y) in_le32(y) 33 #else 34 #define serial_out(x, y) writeb(x, y) 35 #define serial_in(y) readb(y) 36 #endif 37 #endif /* !CONFIG_DM_SERIAL */ 38 39 #if defined(CONFIG_SOC_KEYSTONE) 40 #define UART_REG_VAL_PWREMU_MGMT_UART_DISABLE 0 41 #define UART_REG_VAL_PWREMU_MGMT_UART_ENABLE ((1 << 14) | (1 << 13) | (1 << 0)) 42 #undef UART_MCRVAL 43 #ifdef CONFIG_SERIAL_HW_FLOW_CONTROL 44 #define UART_MCRVAL (UART_MCR_RTS | UART_MCR_AFE) 45 #else 46 #define UART_MCRVAL (UART_MCR_RTS) 47 #endif 48 #endif 49 50 #ifndef CONFIG_SYS_NS16550_IER 51 #define CONFIG_SYS_NS16550_IER 0x00 52 #endif /* CONFIG_SYS_NS16550_IER */ 53 54 static inline void serial_out_shift(void *addr, int shift, int value) 55 { 56 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED 57 outb(value, (ulong)addr); 58 #elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_SYS_BIG_ENDIAN) 59 out_le32(addr, value); 60 #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN) 61 out_be32(addr, value); 62 #elif defined(CONFIG_SYS_NS16550_MEM32) 63 writel(value, addr); 64 #elif defined(CONFIG_SYS_BIG_ENDIAN) 65 writeb(value, addr + (1 << shift) - 1); 66 #else 67 writeb(value, addr); 68 #endif 69 } 70 71 static inline int serial_in_shift(void *addr, int shift) 72 { 73 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED 74 return inb((ulong)addr); 75 #elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_SYS_BIG_ENDIAN) 76 return in_le32(addr); 77 #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN) 78 return in_be32(addr); 79 #elif defined(CONFIG_SYS_NS16550_MEM32) 80 return readl(addr); 81 #elif defined(CONFIG_SYS_BIG_ENDIAN) 82 return readb(addr + (1 << shift) - 1); 83 #else 84 return readb(addr); 85 #endif 86 } 87 88 #ifdef CONFIG_DM_SERIAL 89 90 #ifndef CONFIG_SYS_NS16550_CLK 91 #define CONFIG_SYS_NS16550_CLK 0 92 #endif 93 94 static void ns16550_writeb(NS16550_t port, int offset, int value) 95 { 96 struct ns16550_platdata *plat = port->plat; 97 unsigned char *addr; 98 99 offset *= 1 << plat->reg_shift; 100 addr = (unsigned char *)plat->base + offset; 101 102 /* 103 * As far as we know it doesn't make sense to support selection of 104 * these options at run-time, so use the existing CONFIG options. 105 */ 106 serial_out_shift(addr + plat->reg_offset, plat->reg_shift, value); 107 } 108 109 static int ns16550_readb(NS16550_t port, int offset) 110 { 111 struct ns16550_platdata *plat = port->plat; 112 unsigned char *addr; 113 114 offset *= 1 << plat->reg_shift; 115 addr = (unsigned char *)plat->base + offset; 116 117 return serial_in_shift(addr + plat->reg_offset, plat->reg_shift); 118 } 119 120 static u32 ns16550_getfcr(NS16550_t port) 121 { 122 struct ns16550_platdata *plat = port->plat; 123 124 return plat->fcr; 125 } 126 127 /* We can clean these up once everything is moved to driver model */ 128 #define serial_out(value, addr) \ 129 ns16550_writeb(com_port, \ 130 (unsigned char *)addr - (unsigned char *)com_port, value) 131 #define serial_in(addr) \ 132 ns16550_readb(com_port, \ 133 (unsigned char *)addr - (unsigned char *)com_port) 134 #else 135 static u32 ns16550_getfcr(NS16550_t port) 136 { 137 return UART_FCR_DEFVAL; 138 } 139 #endif 140 141 int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate) 142 { 143 const unsigned int mode_x_div = 16; 144 145 return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate); 146 } 147 148 static void NS16550_setbrg(NS16550_t com_port, int baud_divisor) 149 { 150 serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr); 151 serial_out(baud_divisor & 0xff, &com_port->dll); 152 serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm); 153 serial_out(UART_LCRVAL, &com_port->lcr); 154 } 155 156 void NS16550_init(NS16550_t com_port, int baud_divisor) 157 { 158 #if (defined(CONFIG_SPL_BUILD) && \ 159 (defined(CONFIG_OMAP34XX) || defined(CONFIG_OMAP44XX))) 160 /* 161 * On some OMAP3/OMAP4 devices when UART3 is configured for boot mode 162 * before SPL starts only THRE bit is set. We have to empty the 163 * transmitter before initialization starts. 164 */ 165 if ((serial_in(&com_port->lsr) & (UART_LSR_TEMT | UART_LSR_THRE)) 166 == UART_LSR_THRE) { 167 if (baud_divisor != -1) 168 NS16550_setbrg(com_port, baud_divisor); 169 serial_out(0, &com_port->mdr1); 170 } 171 #endif 172 173 while (!(serial_in(&com_port->lsr) & UART_LSR_TEMT)) 174 ; 175 176 serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier); 177 #if defined(CONFIG_ARCH_OMAP2PLUS) 178 serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/ 179 #endif 180 serial_out(UART_MCRVAL, &com_port->mcr); 181 serial_out(ns16550_getfcr(com_port), &com_port->fcr); 182 if (baud_divisor != -1) 183 NS16550_setbrg(com_port, baud_divisor); 184 #if defined(CONFIG_ARCH_OMAP2PLUS) || defined(CONFIG_SOC_DA8XX) 185 /* /16 is proper to hit 115200 with 48MHz */ 186 serial_out(0, &com_port->mdr1); 187 #endif 188 #if defined(CONFIG_SOC_KEYSTONE) 189 serial_out(UART_REG_VAL_PWREMU_MGMT_UART_ENABLE, &com_port->regC); 190 #endif 191 } 192 193 #ifndef CONFIG_NS16550_MIN_FUNCTIONS 194 void NS16550_reinit(NS16550_t com_port, int baud_divisor) 195 { 196 serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier); 197 NS16550_setbrg(com_port, 0); 198 serial_out(UART_MCRVAL, &com_port->mcr); 199 serial_out(ns16550_getfcr(com_port), &com_port->fcr); 200 NS16550_setbrg(com_port, baud_divisor); 201 } 202 #endif /* CONFIG_NS16550_MIN_FUNCTIONS */ 203 204 void NS16550_putc(NS16550_t com_port, char c) 205 { 206 while ((serial_in(&com_port->lsr) & UART_LSR_THRE) == 0) 207 ; 208 serial_out(c, &com_port->thr); 209 210 /* 211 * Call watchdog_reset() upon newline. This is done here in putc 212 * since the environment code uses a single puts() to print the complete 213 * environment upon "printenv". So we can't put this watchdog call 214 * in puts(). 215 */ 216 if (c == '\n') 217 WATCHDOG_RESET(); 218 } 219 220 #ifndef CONFIG_NS16550_MIN_FUNCTIONS 221 char NS16550_getc(NS16550_t com_port) 222 { 223 while ((serial_in(&com_port->lsr) & UART_LSR_DR) == 0) { 224 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_USB_TTY) 225 extern void usbtty_poll(void); 226 usbtty_poll(); 227 #endif 228 WATCHDOG_RESET(); 229 } 230 return serial_in(&com_port->rbr); 231 } 232 233 int NS16550_tstc(NS16550_t com_port) 234 { 235 return (serial_in(&com_port->lsr) & UART_LSR_DR) != 0; 236 } 237 238 #endif /* CONFIG_NS16550_MIN_FUNCTIONS */ 239 240 #ifdef CONFIG_DEBUG_UART_NS16550 241 242 #include <debug_uart.h> 243 244 static inline void _debug_uart_init(void) 245 { 246 struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE; 247 int baud_divisor; 248 249 /* 250 * We copy the code from above because it is already horribly messy. 251 * Trying to refactor to nicely remove the duplication doesn't seem 252 * feasible. The better fix is to move all users of this driver to 253 * driver model. 254 */ 255 baud_divisor = ns16550_calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK, 256 CONFIG_BAUDRATE); 257 serial_dout(&com_port->ier, CONFIG_SYS_NS16550_IER); 258 serial_dout(&com_port->mcr, UART_MCRVAL); 259 serial_dout(&com_port->fcr, UART_FCR_DEFVAL); 260 261 serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL); 262 serial_dout(&com_port->dll, baud_divisor & 0xff); 263 serial_dout(&com_port->dlm, (baud_divisor >> 8) & 0xff); 264 serial_dout(&com_port->lcr, UART_LCRVAL); 265 } 266 267 static inline void _debug_uart_putc(int ch) 268 { 269 struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE; 270 271 while (!(serial_din(&com_port->lsr) & UART_LSR_THRE)) 272 ; 273 serial_dout(&com_port->thr, ch); 274 } 275 276 DEBUG_UART_FUNCS 277 278 #endif 279 280 #ifdef CONFIG_DEBUG_UART_OMAP 281 282 #include <debug_uart.h> 283 284 static inline void _debug_uart_init(void) 285 { 286 struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE; 287 int baud_divisor; 288 289 baud_divisor = ns16550_calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK, 290 CONFIG_BAUDRATE); 291 serial_dout(&com_port->ier, CONFIG_SYS_NS16550_IER); 292 serial_dout(&com_port->mdr1, 0x7); 293 serial_dout(&com_port->mcr, UART_MCRVAL); 294 serial_dout(&com_port->fcr, UART_FCR_DEFVAL); 295 296 serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL); 297 serial_dout(&com_port->dll, baud_divisor & 0xff); 298 serial_dout(&com_port->dlm, (baud_divisor >> 8) & 0xff); 299 serial_dout(&com_port->lcr, UART_LCRVAL); 300 serial_dout(&com_port->mdr1, 0x0); 301 } 302 303 static inline void _debug_uart_putc(int ch) 304 { 305 struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE; 306 307 while (!(serial_din(&com_port->lsr) & UART_LSR_THRE)) 308 ; 309 serial_dout(&com_port->thr, ch); 310 } 311 312 DEBUG_UART_FUNCS 313 314 #endif 315 316 #ifdef CONFIG_DM_SERIAL 317 static int ns16550_serial_putc(struct udevice *dev, const char ch) 318 { 319 struct NS16550 *const com_port = dev_get_priv(dev); 320 321 #ifdef CONFIG_ARCH_ROCKCHIP 322 /* 323 * Use fifo function. 324 * 325 * UART_USR: bit1 trans_fifo_not_full: 326 * 0 = Transmit FIFO is full; 327 * 1 = Transmit FIFO is not full; 328 */ 329 while (!(serial_in(&com_port->rbr + 0x1f) & 0x02)) 330 ; 331 #else 332 if (!(serial_in(&com_port->lsr) & UART_LSR_THRE)) 333 return -EAGAIN; 334 #endif 335 serial_out(ch, &com_port->thr); 336 337 /* 338 * Call watchdog_reset() upon newline. This is done here in putc 339 * since the environment code uses a single puts() to print the complete 340 * environment upon "printenv". So we can't put this watchdog call 341 * in puts(). 342 */ 343 if (ch == '\n') 344 WATCHDOG_RESET(); 345 346 #ifdef CONFIG_ARCH_ROCKCHIP 347 /* 348 * Wait fifo flush. 349 * 350 * UART_USR: bit2 trans_fifo_empty: 351 * 0 = Transmit FIFO is not empty 352 * 1 = Transmit FIFO is empty 353 */ 354 if (gd->flags & GD_FLG_OS_RUN) { 355 while (!(serial_in(&com_port->rbr + 0x1f) & 0x04)) 356 ; 357 } 358 #endif 359 360 return 0; 361 } 362 363 static int ns16550_serial_pending(struct udevice *dev, bool input) 364 { 365 struct NS16550 *const com_port = dev_get_priv(dev); 366 367 if (input) 368 return serial_in(&com_port->lsr) & UART_LSR_DR ? 1 : 0; 369 else 370 return serial_in(&com_port->lsr) & UART_LSR_THRE ? 0 : 1; 371 } 372 373 static int ns16550_serial_getc(struct udevice *dev) 374 { 375 struct NS16550 *const com_port = dev_get_priv(dev); 376 377 if (!(serial_in(&com_port->lsr) & UART_LSR_DR)) 378 return -EAGAIN; 379 380 return serial_in(&com_port->rbr); 381 } 382 383 static int ns16550_serial_setbrg(struct udevice *dev, int baudrate) 384 { 385 struct NS16550 *const com_port = dev_get_priv(dev); 386 struct ns16550_platdata *plat = com_port->plat; 387 int clock_divisor; 388 389 clock_divisor = ns16550_calc_divisor(com_port, plat->clock, baudrate); 390 391 NS16550_setbrg(com_port, clock_divisor); 392 393 return 0; 394 } 395 396 int ns16550_serial_probe(struct udevice *dev) 397 { 398 struct NS16550 *const com_port = dev_get_priv(dev); 399 400 com_port->plat = dev_get_platdata(dev); 401 NS16550_init(com_port, -1); 402 403 return 0; 404 } 405 406 #if CONFIG_IS_ENABLED(OF_CONTROL) 407 enum { 408 PORT_NS16550 = 0, 409 PORT_JZ4780, 410 }; 411 #endif 412 413 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 414 int ns16550_serial_ofdata_to_platdata(struct udevice *dev) 415 { 416 struct ns16550_platdata *plat = dev->platdata; 417 const u32 port_type = dev_get_driver_data(dev); 418 fdt_addr_t addr; 419 struct clk clk; 420 int err; 421 422 /* try Processor Local Bus device first */ 423 addr = dev_read_addr(dev); 424 #if defined(CONFIG_PCI) && defined(CONFIG_DM_PCI) 425 if (addr == FDT_ADDR_T_NONE) { 426 /* then try pci device */ 427 struct fdt_pci_addr pci_addr; 428 u32 bar; 429 int ret; 430 431 /* we prefer to use a memory-mapped register */ 432 ret = fdtdec_get_pci_addr(gd->fdt_blob, dev_of_offset(dev), 433 FDT_PCI_SPACE_MEM32, "reg", 434 &pci_addr); 435 if (ret) { 436 /* try if there is any i/o-mapped register */ 437 ret = fdtdec_get_pci_addr(gd->fdt_blob, 438 dev_of_offset(dev), 439 FDT_PCI_SPACE_IO, 440 "reg", &pci_addr); 441 if (ret) 442 return ret; 443 } 444 445 ret = fdtdec_get_pci_bar32(dev, &pci_addr, &bar); 446 if (ret) 447 return ret; 448 449 addr = bar; 450 } 451 #endif 452 453 if (addr == FDT_ADDR_T_NONE) 454 return -EINVAL; 455 456 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED 457 plat->base = addr; 458 #else 459 plat->base = (unsigned long)map_physmem(addr, 0, MAP_NOCACHE); 460 #endif 461 462 plat->reg_offset = dev_read_u32_default(dev, "reg-offset", 0); 463 plat->reg_shift = dev_read_u32_default(dev, "reg-shift", 0); 464 465 err = clk_get_by_index(dev, 0, &clk); 466 if (!err) { 467 err = clk_get_rate(&clk); 468 if (!IS_ERR_VALUE(err)) 469 plat->clock = err; 470 } else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) { 471 debug("ns16550 failed to get clock\n"); 472 #ifdef CONFIG_USING_KERNEL_DTB 473 /* With kernel dtb support, serial ofnode not able to get cru phandle */ 474 if(err != -EINVAL) 475 #endif 476 return err; 477 } 478 479 if (!plat->clock) 480 plat->clock = dev_read_u32_default(dev, "clock-frequency", 481 CONFIG_SYS_NS16550_CLK); 482 if (!plat->clock) { 483 debug("ns16550 clock not defined\n"); 484 return -EINVAL; 485 } 486 487 plat->fcr = UART_FCR_DEFVAL; 488 if (port_type == PORT_JZ4780) 489 plat->fcr |= UART_FCR_UME; 490 491 return 0; 492 } 493 #endif 494 495 const struct dm_serial_ops ns16550_serial_ops = { 496 .putc = ns16550_serial_putc, 497 .pending = ns16550_serial_pending, 498 .getc = ns16550_serial_getc, 499 .setbrg = ns16550_serial_setbrg, 500 }; 501 502 #if CONFIG_IS_ENABLED(SERIAL_PRESENT) 503 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 504 /* 505 * Please consider existing compatible strings before adding a new 506 * one to keep this table compact. Or you may add a generic "ns16550" 507 * compatible string to your dts. 508 */ 509 static const struct udevice_id ns16550_serial_ids[] = { 510 { .compatible = "ns16550", .data = PORT_NS16550 }, 511 { .compatible = "ns16550a", .data = PORT_NS16550 }, 512 { .compatible = "ingenic,jz4780-uart", .data = PORT_JZ4780 }, 513 { .compatible = "nvidia,tegra20-uart", .data = PORT_NS16550 }, 514 { .compatible = "snps,dw-apb-uart", .data = PORT_NS16550 }, 515 { .compatible = "ti,omap2-uart", .data = PORT_NS16550 }, 516 { .compatible = "ti,omap3-uart", .data = PORT_NS16550 }, 517 { .compatible = "ti,omap4-uart", .data = PORT_NS16550 }, 518 { .compatible = "ti,am3352-uart", .data = PORT_NS16550 }, 519 { .compatible = "ti,am4372-uart", .data = PORT_NS16550 }, 520 { .compatible = "ti,dra742-uart", .data = PORT_NS16550 }, 521 {} 522 }; 523 #endif /* OF_CONTROL && !OF_PLATDATA */ 524 525 /* TODO(sjg@chromium.org): Integrate this into a macro like CONFIG_IS_ENABLED */ 526 #if !defined(CONFIG_TPL_BUILD) || defined(CONFIG_TPL_DM_SERIAL) 527 U_BOOT_DRIVER(ns16550_serial) = { 528 .name = "ns16550_serial", 529 .id = UCLASS_SERIAL, 530 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 531 .of_match = ns16550_serial_ids, 532 .ofdata_to_platdata = ns16550_serial_ofdata_to_platdata, 533 .platdata_auto_alloc_size = sizeof(struct ns16550_platdata), 534 #endif 535 .priv_auto_alloc_size = sizeof(struct NS16550), 536 .probe = ns16550_serial_probe, 537 .ops = &ns16550_serial_ops, 538 .flags = DM_FLAG_PRE_RELOC, 539 }; 540 #endif 541 #endif /* SERIAL_PRESENT */ 542 543 #endif /* CONFIG_DM_SERIAL */ 544