1*9536dfccSTor Krill /* 2*9536dfccSTor Krill * (C) Copyright 2008 3*9536dfccSTor Krill * Tor Krill, Excito Elektronik i Skåne , tor@excito.com 4*9536dfccSTor Krill * 5*9536dfccSTor Krill * Modelled after the ds1337 driver 6*9536dfccSTor Krill * 7*9536dfccSTor Krill * This program is free software; you can redistribute it and/or 8*9536dfccSTor Krill * modify it under the terms of the GNU General Public License as 9*9536dfccSTor Krill * published by the Free Software Foundation; either version 2 of 10*9536dfccSTor Krill * the License, or (at your option) any later version. 11*9536dfccSTor Krill * 12*9536dfccSTor Krill * This program is distributed in the hope that it will be useful, 13*9536dfccSTor Krill * but WITHOUT ANY WARRANTY; without even the implied warranty of 14*9536dfccSTor Krill * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15*9536dfccSTor Krill * GNU General Public License for more details. 16*9536dfccSTor Krill * 17*9536dfccSTor Krill * You should have received a copy of the GNU General Public License 18*9536dfccSTor Krill * along with this program; if not, write to the Free Software 19*9536dfccSTor Krill * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20*9536dfccSTor Krill * MA 02111-1307 USA 21*9536dfccSTor Krill */ 22*9536dfccSTor Krill 23*9536dfccSTor Krill /* 24*9536dfccSTor Krill * Date & Time support (no alarms) for Intersil 25*9536dfccSTor Krill * ISL1208 Real Time Clock (RTC). 26*9536dfccSTor Krill */ 27*9536dfccSTor Krill 28*9536dfccSTor Krill #include <common.h> 29*9536dfccSTor Krill #include <command.h> 30*9536dfccSTor Krill #include <rtc.h> 31*9536dfccSTor Krill #include <i2c.h> 32*9536dfccSTor Krill 33*9536dfccSTor Krill /*---------------------------------------------------------------------*/ 34*9536dfccSTor Krill #ifdef DEBUG_RTC 35*9536dfccSTor Krill #define DEBUGR(fmt,args...) printf(fmt ,##args) 36*9536dfccSTor Krill #else 37*9536dfccSTor Krill #define DEBUGR(fmt,args...) 38*9536dfccSTor Krill #endif 39*9536dfccSTor Krill /*---------------------------------------------------------------------*/ 40*9536dfccSTor Krill 41*9536dfccSTor Krill /* 42*9536dfccSTor Krill * RTC register addresses 43*9536dfccSTor Krill */ 44*9536dfccSTor Krill 45*9536dfccSTor Krill #define RTC_SEC_REG_ADDR 0x0 46*9536dfccSTor Krill #define RTC_MIN_REG_ADDR 0x1 47*9536dfccSTor Krill #define RTC_HR_REG_ADDR 0x2 48*9536dfccSTor Krill #define RTC_DATE_REG_ADDR 0x3 49*9536dfccSTor Krill #define RTC_MON_REG_ADDR 0x4 50*9536dfccSTor Krill #define RTC_YR_REG_ADDR 0x5 51*9536dfccSTor Krill #define RTC_DAY_REG_ADDR 0x6 52*9536dfccSTor Krill #define RTC_STAT_REG_ADDR 0x7 53*9536dfccSTor Krill /* 54*9536dfccSTor Krill * RTC control register bits 55*9536dfccSTor Krill */ 56*9536dfccSTor Krill 57*9536dfccSTor Krill /* 58*9536dfccSTor Krill * RTC status register bits 59*9536dfccSTor Krill */ 60*9536dfccSTor Krill #define RTC_STAT_BIT_ARST 0x80 /* AUTO RESET ENABLE BIT */ 61*9536dfccSTor Krill #define RTC_STAT_BIT_XTOSCB 0x40 /* CRYSTAL OSCILLATOR ENABLE BIT */ 62*9536dfccSTor Krill #define RTC_STAT_BIT_WRTC 0x10 /* WRITE RTC ENABLE BIT */ 63*9536dfccSTor Krill #define RTC_STAT_BIT_ALM 0x04 /* ALARM BIT */ 64*9536dfccSTor Krill #define RTC_STAT_BIT_BAT 0x02 /* BATTERY BIT */ 65*9536dfccSTor Krill #define RTC_STAT_BIT_RTCF 0x01 /* REAL TIME CLOCK FAIL BIT */ 66*9536dfccSTor Krill 67*9536dfccSTor Krill static uchar rtc_read (uchar reg); 68*9536dfccSTor Krill static void rtc_write (uchar reg, uchar val); 69*9536dfccSTor Krill static uchar bin2bcd (unsigned int n); 70*9536dfccSTor Krill static unsigned bcd2bin (uchar c); 71*9536dfccSTor Krill 72*9536dfccSTor Krill /* 73*9536dfccSTor Krill * Get the current time from the RTC 74*9536dfccSTor Krill */ 75*9536dfccSTor Krill 76*9536dfccSTor Krill void rtc_get (struct rtc_time *tmp) 77*9536dfccSTor Krill { 78*9536dfccSTor Krill uchar sec, min, hour, mday, wday, mon, year, status; 79*9536dfccSTor Krill 80*9536dfccSTor Krill status = rtc_read (RTC_STAT_REG_ADDR); 81*9536dfccSTor Krill sec = rtc_read (RTC_SEC_REG_ADDR); 82*9536dfccSTor Krill min = rtc_read (RTC_MIN_REG_ADDR); 83*9536dfccSTor Krill hour = rtc_read (RTC_HR_REG_ADDR); 84*9536dfccSTor Krill wday = rtc_read (RTC_DAY_REG_ADDR); 85*9536dfccSTor Krill mday = rtc_read (RTC_DATE_REG_ADDR); 86*9536dfccSTor Krill mon = rtc_read (RTC_MON_REG_ADDR); 87*9536dfccSTor Krill year = rtc_read (RTC_YR_REG_ADDR); 88*9536dfccSTor Krill 89*9536dfccSTor Krill DEBUGR ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x " 90*9536dfccSTor Krill "hr: %02x min: %02x sec: %02x status: %02x\n", 91*9536dfccSTor Krill year, mon, mday, wday, hour, min, sec, status); 92*9536dfccSTor Krill 93*9536dfccSTor Krill if (status & RTC_STAT_BIT_RTCF) { 94*9536dfccSTor Krill printf ("### Warning: RTC oscillator has stopped\n"); 95*9536dfccSTor Krill rtc_write(RTC_STAT_REG_ADDR, 96*9536dfccSTor Krill rtc_read(RTC_STAT_REG_ADDR) &~ (RTC_STAT_BIT_BAT|RTC_STAT_BIT_RTCF)); 97*9536dfccSTor Krill } 98*9536dfccSTor Krill 99*9536dfccSTor Krill tmp->tm_sec = bcd2bin (sec & 0x7F); 100*9536dfccSTor Krill tmp->tm_min = bcd2bin (min & 0x7F); 101*9536dfccSTor Krill tmp->tm_hour = bcd2bin (hour & 0x3F); 102*9536dfccSTor Krill tmp->tm_mday = bcd2bin (mday & 0x3F); 103*9536dfccSTor Krill tmp->tm_mon = bcd2bin (mon & 0x1F); 104*9536dfccSTor Krill tmp->tm_year = bcd2bin (year)+2000; 105*9536dfccSTor Krill tmp->tm_wday = bcd2bin (wday & 0x07); 106*9536dfccSTor Krill tmp->tm_yday = 0; 107*9536dfccSTor Krill tmp->tm_isdst= 0; 108*9536dfccSTor Krill 109*9536dfccSTor Krill DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", 110*9536dfccSTor Krill tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, 111*9536dfccSTor Krill tmp->tm_hour, tmp->tm_min, tmp->tm_sec); 112*9536dfccSTor Krill } 113*9536dfccSTor Krill 114*9536dfccSTor Krill /* 115*9536dfccSTor Krill * Set the RTC 116*9536dfccSTor Krill */ 117*9536dfccSTor Krill void rtc_set (struct rtc_time *tmp) 118*9536dfccSTor Krill { 119*9536dfccSTor Krill DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", 120*9536dfccSTor Krill tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, 121*9536dfccSTor Krill tmp->tm_hour, tmp->tm_min, tmp->tm_sec); 122*9536dfccSTor Krill 123*9536dfccSTor Krill /* enable write */ 124*9536dfccSTor Krill rtc_write(RTC_STAT_REG_ADDR, 125*9536dfccSTor Krill rtc_read(RTC_STAT_REG_ADDR) | RTC_STAT_BIT_WRTC); 126*9536dfccSTor Krill 127*9536dfccSTor Krill rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100)); 128*9536dfccSTor Krill rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon)); 129*9536dfccSTor Krill rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday)); 130*9536dfccSTor Krill rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday)); 131*9536dfccSTor Krill rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour) | 0x80 ); /* 24h clock */ 132*9536dfccSTor Krill rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min)); 133*9536dfccSTor Krill rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec)); 134*9536dfccSTor Krill 135*9536dfccSTor Krill /* disable write */ 136*9536dfccSTor Krill rtc_write(RTC_STAT_REG_ADDR, 137*9536dfccSTor Krill rtc_read(RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_WRTC); 138*9536dfccSTor Krill } 139*9536dfccSTor Krill 140*9536dfccSTor Krill void rtc_reset (void) 141*9536dfccSTor Krill { 142*9536dfccSTor Krill } 143*9536dfccSTor Krill 144*9536dfccSTor Krill /* 145*9536dfccSTor Krill * Helper functions 146*9536dfccSTor Krill */ 147*9536dfccSTor Krill 148*9536dfccSTor Krill static uchar rtc_read (uchar reg) 149*9536dfccSTor Krill { 150*9536dfccSTor Krill return (i2c_reg_read (CFG_I2C_RTC_ADDR, reg)); 151*9536dfccSTor Krill } 152*9536dfccSTor Krill 153*9536dfccSTor Krill static void rtc_write (uchar reg, uchar val) 154*9536dfccSTor Krill { 155*9536dfccSTor Krill i2c_reg_write (CFG_I2C_RTC_ADDR, reg, val); 156*9536dfccSTor Krill } 157*9536dfccSTor Krill 158*9536dfccSTor Krill static unsigned bcd2bin (uchar n) 159*9536dfccSTor Krill { 160*9536dfccSTor Krill return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); 161*9536dfccSTor Krill } 162*9536dfccSTor Krill 163*9536dfccSTor Krill static unsigned char bin2bcd (unsigned int n) 164*9536dfccSTor Krill { 165*9536dfccSTor Krill return (((n / 10) << 4) | (n % 10)); 166*9536dfccSTor Krill } 167